Akira Hatanaka
7398bf01c2
Modify LowerFCOPYSIGN to handle Mips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:48:50 +00:00
Chad Rosier
cbbb09687f
Begin adding experimental support for preserving use-list ordering of bitcode
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files. First, add a new block USELIST_BLOCK to the bitcode format. This is
where USELIST_CODE_ENTRYs will be stored. The format of the USELIST_CODE_ENTRYs
have not yet been defined. Add support in the BitcodeReader for parsing the
USELIST_BLOCK.
Part of rdar://9860654 and PR5680.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:44:12 +00:00
Nick Lewycky
e77ae2d692
These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me
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that he isn't using these any more, so just delete them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:35:59 +00:00
Chad Rosier
4e6c03fc3d
ValueEnumerator - debug dump().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:44:46 +00:00
Akira Hatanaka
bd15090aa2
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:15:01 +00:00
Akira Hatanaka
3bdc03a592
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:13:53 +00:00
Akira Hatanaka
4d0eb637f0
Fix 64-bit immediate patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:10:24 +00:00
Jim Grosbach
4f66a050a2
Nuke inadvertant debugging commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:56:16 +00:00
Jim Grosbach
577b09155f
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:46:59 +00:00
Jakub Staszak
feb468ab24
Remove unneeded semicolon.
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Skip two looking up at BlockChain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:46:10 +00:00
Jim Grosbach
8524bca750
Thumb2 alias for long-form pop and friends.
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rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca
ARM support the .arm and .thumb directives for assembly mode switching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:51:15 +00:00
Duncan Sands
0ea3a0c236
Remove unused include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146037 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:18:31 +00:00
Craig Topper
d802326335
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 08:30:53 +00:00
Bill Wendling
b3ec329c14
Adjust the stack by one pointer size for all frameless stacks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:58:55 +00:00
Bill Wendling
c61751373a
Fix off-by-one error when encoding the stack size for a frameless stack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:49:49 +00:00
Evan Cheng
5a96b3dad2
Add bundle aware API for querying instruction properties and switch the code
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generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
David Blaikie
5729c5848c
Adding missing anchor to DATDeltaAlgorithm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:44:23 +00:00
Hal Finkel
234bb38d6c
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:34:06 +00:00
Hal Finkel
6d0e014b1f
make base register selection used in eliminateFrameIndex 64-bit clean
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:34:02 +00:00
Hal Finkel
ae37cd0a37
set mayStore and mayLoad on CR pseudos
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:33:57 +00:00
Hal Finkel
7ad6b7d359
64-bit LR8 load should use X11 not R11
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:32:37 +00:00
Jakob Stoklund Olesen
2fe71c5ef4
Eliminate delta argument from AdjustBBOffsetsAfter.
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The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen
a26811ec83
Compute some alignment information for each basic block.
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These fields are not used for anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 04:17:35 +00:00
Eli Friedman
1c663fee56
Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this doesn't affect any in-tree target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 03:55:52 +00:00
Jim Grosbach
1ceef1a491
ARM tidy up and remove no longer needed InstAlias definitions.
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The TokenAlias handling of data type suffices renders these unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen
5bb32530bc
Move common expression into a method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:22:52 +00:00
Jim Grosbach
9f3d220c63
ARM Implement ARM ARM Table A7-3 via TokenAlias.
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Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen
a3f331bd81
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
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No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:08:25 +00:00
Jakob Stoklund Olesen
0400345198
Add missing check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:08:22 +00:00
Jim Grosbach
3b8991cc98
ARM: NEON SHLL instruction immediate operand range checking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:07:24 +00:00
Eli Friedman
f91abd22be
Support vector bitcasts in the AsmPrinter. PR11495.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:50:54 +00:00
Bruno Cardoso Lopes
e3d3572e28
Add a few moreLocal/Global R_MIPS_GOT related fixups and
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make the addend fixup code a bit more generic
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:28:57 +00:00
Jakob Stoklund Olesen
2068215e85
Add MachineOperand IsInternalRead flag.
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This flag is used when bundling machine instructions. It indicates
whether the operand reads a value defined inside or outside its bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:22:07 +00:00
Eli Friedman
26323442d5
Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:11:56 +00:00
Jakub Staszak
c9040b3b13
Remove unneeded type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:08:00 +00:00
Jim Grosbach
4e4139588c
ARM: Parameterize the immediate operand type for NEON VSHLL.
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No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:02:17 +00:00
Jakub Staszak
e6d81ad6a5
- Remove unneeded #includes.
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- Remove unused types/fields.
- Add some constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 23:59:33 +00:00
Jakob Stoklund Olesen
6fbea43b0b
Revert r145971: "Use conservative size estimate for tBR_JTr."
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This caused more offset errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:41:31 +00:00
Bill Wendling
054a8be154
Re-enable compact unwind. It seems to work now. <rdar://problem/10441838>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:18:12 +00:00
Bill Wendling
84d518af19
Explicitly check for the different SUB instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:14:27 +00:00
Evan Cheng
7c2a4a30e0
First chunk of MachineInstr bundle support.
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1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen
d25c27807e
Use conservative size estimate for tBR_JTr.
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This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen
305e5fe797
Remove alignment from deserted constant islands.
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ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:55:35 +00:00
Bill Wendling
581ac2723c
Encode the total stack if there isn't a frame.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:34:01 +00:00
Bill Wendling
57a3cd2f32
* Add a macro to remove a magic number.
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* Rename variables to reflect what they're actually used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:23:42 +00:00
Jakob Stoklund Olesen
f2e944523c
Pretty-print basic block alignment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:08:39 +00:00
Hal Finkel
d21e930eac
add RESTORE_CR and support CR unspills
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 20:55:36 +00:00
Hal Finkel
16588e794c
remove old FIXME
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 20:52:56 +00:00
Bill Wendling
5b2c4978ce
Check the correct value for small stack sizes. Also modify some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 19:16:17 +00:00
Bill Wendling
75e14e0ebd
For a small sized stack, we encode that value directly with no "stack adjust" value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 19:09:06 +00:00
Justin Holewinski
4c7ffb6a7e
PTX: Continue to fix up the register mess.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:39:48 +00:00
Justin Holewinski
e37a83f66b
PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:39:46 +00:00
Sebastian Pop
464f3a332f
use space star instead of star space
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:34:16 +00:00
Sebastian Pop
f6f77e90a1
add missing point at the end of sentences
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:34:11 +00:00
Benjamin Kramer
88c09143b6
Simplify common predecessor finding.
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- Walking over pred_begin/pred_end is an expensive operation.
- PHINodes contain a value for each predecessor anyway.
- While it may look like we used to save a few iterations with the set,
be aware that getIncomingValueForBlock does a linear search on
the values of the phi node.
- Another -5% on ARMDisassembler.cpp (Release build). This was the last
entry in the profile that was obviously wasting time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 16:14:29 +00:00
Benjamin Kramer
85dadecbd6
Push StringRefs through the metadata interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 11:50:26 +00:00
Craig Topper
fe03315925
Add X86ISD::HADD/HSUB to getTargetNodeName
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 09:31:36 +00:00
Craig Topper
cb6bd11bd6
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 09:04:59 +00:00
Craig Topper
34671b812a
Merge floating point and integer UNPCK X86ISD node types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 08:21:25 +00:00
Craig Topper
3d8c2ce3e4
Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145924 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:31:16 +00:00
Jim Grosbach
23261af193
ARM mode 'mul' operand ordering tweak.
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Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2
Thumb2: MUL two-operand form encoding operand order fix.
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Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:03:45 +00:00
Craig Topper
1ff73d7a67
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 04:59:07 +00:00
Jim Grosbach
df33e0d05e
Thumb2 encoding choice correction for PLD.
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Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 04:49:29 +00:00
Bruno Cardoso Lopes
ff452f5349
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes
a00a62acd0
Explicit symbols for gnu mimicing relocations. Patch by Jack Carter
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145911 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:34:42 +00:00
Bruno Cardoso Lopes
2bcc789a9d
Add register HWR29 numbering. Patch by Jack Carter
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:34:36 +00:00
Andrew Trick
8a5d792944
LSR: prune undesirable formulae early.
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It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:13:31 +00:00
Evan Cheng
89dae971b1
Mix some minor misuse of MachineBasicBlock iterator.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 02:49:06 +00:00
Pete Cooper
d3743fc092
Removed isWinToJoinCrossClass from the register coalescer.
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The new register allocator is much more able to split back up ranges too constrained by register classes.
Fixes <rdar://problem/10466609>
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2011-12-06 02:06:50 +00:00
Lang Hames
bae56b4c21
Kill off the LoopSplitter. It's not being used or maintained.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:57:59 +00:00
Bill Wendling
80caf9c273
Add a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:57:48 +00:00
Jim Grosbach
cb86509e7a
Tidy up value checking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:53:17 +00:00
NAKAMURA Takumi
6482e91149
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145894 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:48:32 +00:00
Lang Hames
9ad7e07a0f
Update PBQP's analysis usage to reflect the requirements of the inline spiller.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145893 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:45:57 +00:00
Chad Rosier
ed42c5f778
[arm-fast-isel] Doublewords only require word-alignment.
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rdar://10528060
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2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
3e572ac2fb
Align ARM constant pool islands via their basic block.
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Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
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2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen
8c741b8064
Use logarithmic units for basic block alignment.
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This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.
CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.
Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.
Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.
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2011-12-06 01:26:19 +00:00
Bill Wendling
79df986c60
The compact encoding of the registers are 3-bits each. Make sure we shift the
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value over that much.
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2011-12-06 01:26:14 +00:00
Jim Grosbach
d9a6e8978d
Fix ARM handling of tBcc branch relaxation.
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rdar://10069056
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2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen
e80fba0e6c
Use an existing function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145883 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 00:51:12 +00:00
Jim Grosbach
370b78d795
Move target-specific logic out of generic MCAssembler.
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Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
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2011-12-06 00:47:03 +00:00
Nick Lewycky
7c06741004
Expose a switch for the new gcov format.
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2011-12-06 00:29:13 +00:00
Chad Rosier
dce42b75dc
Probably not a good idea to convert a single vector load into a memcpy. We
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don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684
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2011-12-06 00:19:08 +00:00
Jim Grosbach
f68a26b5d8
Tidy up. Hard tabs.
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2011-12-06 00:13:09 +00:00
Jim Grosbach
f77d5b14af
Switch MCAssembler to method names starting w/ lower-case.
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per http://llvm.org/docs/CodingStandards.html#ll_naming
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2011-12-06 00:03:48 +00:00
Jim Grosbach
f503ef6800
Simple branch relaxation for Thumb2 Bcc instructions.
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Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
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2011-12-05 23:45:46 +00:00
Nick Lewycky
aa21e417f2
Silence tsan false-positives (tsan can't track things which are only safe due to
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memory fences) in statistics registration, which works the same way that
ManagedStatic registration does.
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2011-12-05 23:07:05 +00:00
Chad Rosier
a4b6fd5be0
Update comment.
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2011-12-05 22:53:09 +00:00
Chad Rosier
d8bd26ee24
Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio
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where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150
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2011-12-05 22:37:00 +00:00
Jim Grosbach
713c70238c
Tweak ADDrr fix. Bad check for explicit .w
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2011-12-05 22:27:04 +00:00
Jim Grosbach
927b9df4c6
Thumb2 prefer ADD register encoding T2 to T3 when possible.
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rdar://10529664
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2011-12-05 22:16:39 +00:00
Akira Hatanaka
d6bc5237d8
Add definitions of 64-bit extract and insert instrucions and make
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PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
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2011-12-05 21:26:34 +00:00
Akira Hatanaka
cee46abc16
Split ExtIns into two base classes and have instructions EXT and INS derive from
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them.
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2011-12-05 21:14:28 +00:00
Jim Grosbach
da84786bee
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
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2011-12-05 21:06:26 +00:00
Akira Hatanaka
2bf08ec854
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
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O32 with relocation-model=pic too.
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2011-12-05 21:03:03 +00:00
Jim Grosbach
253ef7a779
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
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2011-12-05 20:29:59 +00:00
Jim Grosbach
422faab909
Fix previous commit. Oops.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 20:12:26 +00:00