6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-10 02:29:32 +00:00
Code Issues Projects Releases Wiki Activity
27,365 Commits 39 Branches 0 Tags 277 MiB
e6e97e66a3
Commit Graph

1376 Commits

Author SHA1 Message Date
Evan Cheng
e6e97e66a3 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31414 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 07:31:32 +00:00
Evan Cheng
1a854be352 Rename 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31413 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 07:21:16 +00:00
Reid Spencer
b8f4e0aa17 Remove dead variable. Fix 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31412 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 03:30:34 +00:00
Evan Cheng
7fc033a24d Added DAG combiner transformation to generate pre-indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31410 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 03:06:21 +00:00
Evan Cheng
c5fc57dcae Added isPredecessor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31409 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 03:05:24 +00:00
Chris Lattner
02cb49ee67 silence warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31397 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:28:29 +00:00
Reid Spencer
3ed469ccd7 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 20:25:50 +00:00
Reid Spencer
0a783f783c For PR950: 
Replace the REM instruction with UREM, SREM and FREM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31369 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 01:53:59 +00:00
Chris Lattner
2a821601f1 Allow the getRegForInlineAsmConstraint method to return a register class with 
no fixes physreg.  Treat this as permission to use any register in the register
class.  When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time.  This eliminates a ton
of copies around common inline asms.  For example:

int test2(int Y, int X) {
  asm("foo %0, %1" : "=r"(X): "r"(X));
  return X;
}

now compiles to:

_test2:
        foo r3, r4
        blr

instead of:

_test2:
        mr r2, r4
        foo r2, r2
        mr r3, r2
        blr

GCC produces:

_test2:
        foo r4, r4
        mr r3,r4
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31366 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 01:41:49 +00:00
Evan Cheng
1dabb68ab4 Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31359 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 22:39:30 +00:00
Evan Cheng
93467e7fe3 CopyFromReg starts a live range so its use should not be considered a floater. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31356 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 22:17:06 +00:00
Evan Cheng
6cc31ae4da Print jumptable index. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31340 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 04:48:30 +00:00
Chris Lattner
0ccb500fa7 Compile CodeGen/PowerPC/fp-branch.ll to: 
_intcoord_cond_next55:
LBB1_3: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
        li r3, 1
        blr
LBB1_2: ;cond_next62.exitStub
        li r3, 0
        blr

instead of:

_intcoord_cond_next55:
LBB1_3: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
        li r3, 1
        blr
LBB1_2: ;cond_next62.exitStub
        li r3, 0
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31330 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 23:06:00 +00:00
Chris Lattner
df19f27d03 look through isunordered to inline it into branch blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31328 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 22:37:42 +00:00
Chris Lattner
efa46ce87b handle global address constant sdnodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31323 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 20:01:56 +00:00
Chris Lattner
53069fbbae TargetLowering::isOperandValidForConstraint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31319 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 19:41:18 +00:00
Chris Lattner
dba1aeedd8 Change the prototype for TargetLowering::isOperandValidForConstraint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 19:40:43 +00:00
Chris Lattner
d03f1581c8 Turn an assert into an error message. This is commonly triggered when 
we don't support a specific constraint yet.  When this happens, print the
unsupported constraint.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31310 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 07:33:13 +00:00
Evan Cheng
d063189c09 Fix a typo which can break jumptables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31305 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 02:31:00 +00:00
Evan Cheng
3d4ce11085 Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the target custom lower it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31293 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-30 08:00:44 +00:00
Evan Cheng
c41cd9c391 Added a new SDNode type: BR_JT for jumptable branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31292 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-30 07:59:36 +00:00
Chris Lattner
6a586c8d9a fix Generic/2006-10-29-Crash.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31281 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-29 21:01:20 +00:00
Chris Lattner
5a145f0094 Fix a load folding issue that Evan noticed: there is no need to export values 
used by comparisons in the main block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31279 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-29 18:23:37 +00:00
Evan Cheng
ba726ab3ec VLOAD is not the LoadSDNode opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31276 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-29 06:14:47 +00:00
Nick Lewycky
f6aaaaa39e Remove spurious case. EXTLOAD is not one of the node opcodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31275 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-29 02:26:30 +00:00
Chris Lattner
bad7f48c70 split critical edges more carefully and intelligently. In particular, critical 
edges whose destinations are not phi nodes don't bother us.  Also, share
split edges, since the split edge can't have a phi.  This significantly
reduces the complexity of generated code in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31274 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 19:22:10 +00:00
Jim Laskey
1c6f01aaa5 Load and stores have not been uniqued properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31261 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 17:25:28 +00:00
Chris Lattner
47e32e6b83 Split *all* critical edges before isel. This resolves issues with spill code 
being inserted on unsplit critical edges, which introduces (sometimes large
amounts of) partially dead spill code.

This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31260 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 17:04:37 +00:00
Chris Lattner
6fb6ef4d65 Fix a serious bug that caused any x86 vector stuff to infinite loop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31254 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 06:15:26 +00:00
Jim Laskey
def69b92e7 Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31243 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 23:52:51 +00:00
Chris Lattner
8c494ab759 Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll). 
Add many fewer CFG edges and PHI node entries.  If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31242 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 23:50:33 +00:00
Jim Laskey
583bd47f77 Switch over from SelectionNodeCSEMap to FoldingSet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31240 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 23:46:08 +00:00
Chris Lattner
1c9b2f312d remove debug code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31233 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 21:58:03 +00:00
Chris Lattner
d2f9ee9ea7 Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to: 
cmpwi cr0, r4, 4
        bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
        cmplwi cr0, r3, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r3, r4, r3
        rlwinm r2, r2, 30, 31, 31
        or r2, r2, r3
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31232 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 21:54:23 +00:00
Chris Lattner
571e434a34 Turn conditions like x<Y|z==q into multiple blocks. 
This compiles Regression/CodeGen/X86/or-branch.ll into:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $5, %eax
        jl LBB1_1       #cond_true
LBB1_3: #entry
        testl %ecx, %ecx
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

instead of:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $4, %eax
        setg %al
        testl %ecx, %ecx
        setne %cl
        testb %cl, %al
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

And on ppc to:

        cmpwi cr0, r29, 5
        blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
        cmplwi cr0, r30, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r30, r4, r3
        rlwinm r29, r2, 30, 31, 31
        and r2, r29, r30
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 21:36:01 +00:00
Evan Cheng
5270cf1b77 getPreIndexedLoad -> getIndexedLoad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31209 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-26 21:53:40 +00:00
Reid Spencer
1628cec4d7 For PR950: 
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31195 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-26 06:15:43 +00:00
Chris Lattner
2452595927 visitSwitchCase knows how to insert conditional branches well. Change 
visitBr to just call visitSwitchCase, eliminating duplicate logic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31167 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 18:07:37 +00:00
Chris Lattner
57ab65972e Generalize CaseBlock a bit more: 
Rename LHSBB/RHSBB to TrueBB/FalseBB.  Allow the RHS value to be null,
in which case the LHS is treated as a bool.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31166 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 17:57:59 +00:00
Chris Lattner
7b248d9866 generalize 'CaseBlock'. It really allows any comparison to be inserted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31161 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-24 17:03:35 +00:00
Chris Lattner
b354343af7 Minor tweak. Instead of generating: 
movl 32(%esp), %eax
        cmpl $1, %eax
        je LBB1_1       #bb
LBB1_4: #entry
        cmpl $2, %eax
        je LBB1_2       #bb2
        jmp LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb

notice that we would miss the fall through and emit this instead:

        movl 32(%esp), %eax
        cmpl $2, %eax
        je LBB1_2       #bb2
LBB1_4: #entry
        cmpl $1, %eax
        jne LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31130 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-23 18:38:22 +00:00
Chris Lattner
b2e806eecd Fix phi node updating for switches lowered to linear sequences of branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31125 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-22 23:00:53 +00:00
Chris Lattner
e236ac64a2 disable this code for now, it's not yet safely updating phi nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31124 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-22 22:47:10 +00:00
Chris Lattner
d2c1d2200b Implement PR964 and Regression/CodeGen/Generic/SwitchLowering.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31119 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-22 21:36:53 +00:00
Chris Lattner
34ab4d45d2 Make flag and chain edges visually distinguishable from value edges in DOT 
output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31067 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-20 18:06:09 +00:00
Reid Spencer
b83eb6447b For PR950: 
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31063 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-20 07:07:24 +00:00
Bill Wendling
c70ddad2b7 Partially in response to PR926: insert the newly created machine basic 
blocks into the basic block list when lowering the switch inst. into a
binary tree of if-then statements. This allows the "visitSwitchCase" func
to allow for fall-through behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31057 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-19 21:46:38 +00:00
Jim Laskey
07a2709e9d Add option for controlling inclusion of global AA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31040 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 19:08:31 +00:00
Jim Laskey
096c22ea3d Use global info for alias analysis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31035 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-18 12:29:57 +00:00
Chris Lattner
b360729873 Trivial patch to speed up legalizing common i64 constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31020 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-17 21:47:13 +00:00