Richard Trieu
a785a7bf51
Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 23:06:23 +00:00
Richard Trieu
d1fe8d5212
Change assert(0 && "text") to llvm_unreachable(0 && "text")
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 23:46:19 +00:00
Richard Trieu
c09324483c
Fix broken asserts that never fire.
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Change assert("text") to assert(0 && "text"). The first case is a const char *
to bool conversion, which always evaluates to true, never triggering the
assert. The second case will always trigger the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 21:54:25 +00:00
Chad Rosier
5b3fca50a0
The getRegForInlineAsmConstraint function should only accept MVT value types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-22 18:37:38 +00:00
Bill Wendling
ba54bca472
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
David Blaikie
0187e7a9ba
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
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Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:27 +00:00
Andrew Trick
b86a0cdb67
Machine Model: Add MicroOpBufferSize and resource BufferSize.
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Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize
These can be used to more precisely model instruction execution if desired.
Disabled some misched tests temporarily. They'll be reenabled in a few commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:49:57 +00:00
Bill Wendling
54a56fad36
Don't cache the instruction and register info from the TargetMachine, because
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the internals of TargetMachine could change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 06:19:56 +00:00
Bill Wendling
6a2e7ac0b6
Cache the TargetLowering info object as a pointer.
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Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:43:09 +00:00
Ahmed Bougacha
23ed37a6b7
Make SubRegIndex size mandatory, following r183020.
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This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:45:26 +00:00
Andrew Trick
6e0b2a0cb0
Order CALLSEQ_START and CALLSEQ_END nodes.
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Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29 22:03:55 +00:00
Jyotsna Verma
ee6e242e78
Hexagon: Typo fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-28 19:01:45 +00:00
Andrew Trick
ac6d9bec67
Track IR ordering of SelectionDAG nodes 2/4.
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Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-25 02:42:55 +00:00
Benjamin Kramer
a32218a7ec
Hexagon: Make helper functions static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182588 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 15:43:11 +00:00
Jyotsna Verma
b4b14070a4
Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 15:54:32 +00:00
Matt Arsenault
225ed7069c
Add LLVMContext argument to getSetCCResultType
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 00:21:46 +00:00
Benjamin Kramer
033f3b7eb6
Don't cast away constness.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 11:39:41 +00:00
Rafael Espindola
992c3817ea
Remove dead calls to addFrameMove.
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Without a PROLOG_LABEL present, the cfi instructions are never printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 15:08:37 +00:00
Jyotsna Verma
a29a8965e2
Hexagon: Pass to replace tranfer/copy instructions into combine instruction
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where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 18:54:06 +00:00
Jyotsna Verma
36e1b51438
Hexagon: Add patterns to generate 'combine' instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 17:16:38 +00:00
Jyotsna Verma
91eadc6d69
Hexagon: ArePredicatesComplement should not restrict itself to TFRs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 16:36:34 +00:00
Jyotsna Verma
9c9bf9a240
Hexagon: Remove dead-code after unconditional return from addPreSched2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 15:33:27 +00:00
Duncan Sands
b99052ce4a
Suppress GCC compiler warnings in release builds about variables that are only
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read in asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 07:50:47 +00:00
Rafael Espindola
4a971705bc
Remove the MachineMove class.
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It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 01:16:13 +00:00
Rafael Espindola
d84ccfaf50
Change getFrameMoves to return a const reference.
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To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 02:38:11 +00:00
Jyotsna Verma
fd4ccda4a5
Fix unused variable error.
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Earlier, this variable was used in an assert and was causing failure on
darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181630 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 21:44:02 +00:00
Jyotsna Verma
cdfb55d15b
Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181628 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 20:58:11 +00:00
Jyotsna Verma
1a35b8e2eb
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 20:27:34 +00:00
Rafael Espindola
6e53180db1
Remove unused argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 18:16:59 +00:00
Rafael Espindola
3a0d00eef9
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 16:53:12 +00:00
Jyotsna Verma
80d81aa8ba
Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181535 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-09 19:16:07 +00:00
Jyotsna Verma
f4f60b10e4
Hexagon: Use relation map for getMatchingCondBranchOpcode() and
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getInvertedPredicatedOpcode() functions instead of switch cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-09 18:25:44 +00:00
Jyotsna Verma
f931f691ee
Hexagon: Fix Small Data support to handle -G 0 correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 19:53:00 +00:00
Jyotsna Verma
ddcf3ee768
Reverting r181331.
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Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 17:12:35 +00:00
Jyotsna Verma
81fda3b4d5
Hexagon: Fix Small Data support to handle -G 0 correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 16:42:15 +00:00
Jyotsna Verma
8cc93593cd
Hexagon: Set accessSize and addrMode on all load/store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 15:06:29 +00:00
Krzysztof Parzyszek
942940a326
Print IR from Hexagon MI passes with -print-before/after-all.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:58:00 +00:00
Krzysztof Parzyszek
b072090f39
Cleanup of the HexagonTargetMachine setup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181250 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 21:25:45 +00:00
Jyotsna Verma
1a7eab3878
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 18:49:23 +00:00
Krzysztof Parzyszek
ed6fe299cf
Make references to HexagonTargetMachine "const".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 18:38:37 +00:00
Krzysztof Parzyszek
cc420a0911
Use consistent function names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 01:30:49 +00:00
Reid Kleckner
aa35a56975
Fix missing include in Hexagon code for Release+Asserts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 00:54:56 +00:00
Jyotsna Verma
d4f8a6b9e9
reverting r180953
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 22:10:59 +00:00
Jyotsna Verma
8a3f50038f
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:21:57 +00:00
Pranav Bhandarkar
02d937d864
Hexagon - Add peephole optimizations for zero extends.
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* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
sequence of a pair of i32->i64 extensions followed by a "bitwise or"
into COMBINE_rr.
* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
* test/CodeGen/Hexagon/union-1.ll: New test.
* test/CodeGen/Hexagon/combine_ir.ll: Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 20:22:51 +00:00
Jyotsna Verma
f945d09d53
Hexagon: Honor __builtin_expect by using branch probabilities.
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* lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
Given a jump opcode return the right pred.new jump opcode with
a taken vs not-taken hint based on branch probabilities provided
by the target independent module.
* lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
* lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
Enhance existing function use branch probabilities like
HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180923 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:39:30 +00:00
Jyotsna Verma
6ea706e40e
Hexagon: Use multiclass for Jump instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01 21:37:34 +00:00
Jyotsna Verma
f9759c9f08
Hexagon: Clear isKill flag on the predicate register in
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PredicateInstruction function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01 21:27:30 +00:00
Jyotsna Verma
42ba77db53
Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 21:17:40 +00:00
Jyotsna Verma
197c833ee1
Hexagon: Define relations for GP-relative instructions.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 21:05:55 +00:00