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5112 Commits

Author SHA1 Message Date
Chris Lattner
ac105c4dca really remove the instruction, don't just comment it out 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91976 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:46:40 +00:00
Chris Lattner
9e3238303c completely eliminate the MOV16r0 'instruction'. The only 
interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91975 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:45:04 +00:00
Sean Callanan
5227cc89f4 More fixes for Visual C++. Replaced several very small 
static inline functions with macros.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91973 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:32:29 +00:00
Chris Lattner
6a38182471 stop pattern matching 16-bit zero's of a register to MOV16r0, 
instead use the appropriate subreggy thing.  This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july).  This means that MOV16r0 can go away
completely in the future soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91972 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:30:26 +00:00
Sean Callanan
542eabcba6 Removed the "inline" keyword from the disassembler decoder, 
because the Visual C++ build does not build .c files as C99


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91935 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 22:51:40 +00:00
Sean Callanan
7fb35a2fd8 Fixes to the X86 disassembler: 
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 21:12:55 +00:00
Evan Cheng
b1f4981333 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 17:47:23 +00:00
Douglas Gregor
3dac3b7d23 Include based on the current path, since we already -I the X86 target's path. Fixes CMake build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 17:25:11 +00:00
Bill Wendling
3ea3c24619 Add more plumbing. This time in the LowerArguments and "get" functions which 
return partial registers. This affected the back-end lowering code some.

Also patch up some places I missed before in the "get" functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 02:10:19 +00:00
Sean Callanan
06b766d1c0 Changed REG_* to MODRM_REG_* to avoid conflicts 
with symbols in AuroraUX's global namespace.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91879 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 02:07:42 +00:00
Daniel Dunbar
baf2e35e18 Fix some may-be-uninitialized var warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91878 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 01:41:37 +00:00
Sean Callanan
0122c9051a Fixed library dependencies between the X86 disassembler and 
X86 codegen that were causing circular symbol dependencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91871 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 01:11:26 +00:00
Chris Lattner
ffc0574a12 print pcrel immediates as signed values instead of unsigned so that we 
get things like this out of the disassembler:

0x100000ecb: callq	-96

instead of:

0x100000ecb: callq	4294967200

rdar://7491123



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91864 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 00:44:05 +00:00
Eric Christopher
f4f43cb501 Fix setting and default setting of code model for jit. Do this 
by allowing backends to override routines that will default
the JIT and Static code generation to an appropriate code model
for the architecture.

Should fix PR 5773.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91824 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 08:15:29 +00:00
Eli Friedman
1f1b0f748d A couple minor README updates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91823 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-21 08:03:16 +00:00
Daniel Dunbar
c814346c9d #if 0 out X86 disassembler for now, it is breaking the build in multiple places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-19 17:11:53 +00:00
Nuno Lopes
392bbd99b6 rename dprintf to dbgpritnf, in order to fix build with glibc (which already defines dprintf in stdio.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91775 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-19 12:07:00 +00:00
Daniel Dunbar
71f842d7c1 Use memset instead of bzero, its more portable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91754 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-19 03:31:50 +00:00
Sean Callanan
8ed9f51663 Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit 
incarnations), integrated into the MC framework.  

The disassembler is table-driven, using a custom TableGen backend to 
generate hierarchical tables optimized for fast decode.  The disassembler 
consumes MemoryObjects and produces arrays of MCInsts, adhering to the 
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).

The disassembler is documented in detail in

- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)

You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets.  Please let me know if you encounter any problems
with it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-19 02:59:52 +00:00
Anton Korobeynikov
e9ec6ad1ba Bump alignment requirements for windows targets to achieve compartibility with vcpp. 
Based on patch by Michael Beck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91745 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-19 02:04:23 +00:00
Evan Cheng
400073d546 On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 07:40:29 +00:00
Evan Cheng
c7928f8f4e Re-apply 91623 now that I actually know what I was trying to do. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91655 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 01:59:21 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Jeffrey Yasskin
08ce53996e Revert r91623 to unbreak the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 22:44:34 +00:00
Evan Cheng
73ebbd8aac Remove an unused option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91623 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 21:23:58 +00:00
Ken Dyck
70d0ef1459 In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of 
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91602 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 15:31:52 +00:00
Evan Cheng
2e489c4f9d Re-enable 91381 with fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:53:11 +00:00
Jeffrey Yasskin
32d7e6ebde Change indirect-globals to use a dedicated allocIndirectGV. This lets us 
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91464 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 22:42:46 +00:00
Evan Cheng
dba6cac0d4 Fix an encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91417 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 06:49:02 +00:00
Kenneth Uildriks
76df3f398c For fastcc on x86, let ECX be used as a return register after EAX and EDX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91410 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 03:27:52 +00:00
Evan Cheng
d7760a4905 Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91405 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 03:07:11 +00:00
Evan Cheng
ad9c0a3d8b Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:53:42 +00:00
Dan Gohman
2e141d744e Fix integer cast code to handle vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 23:40:38 +00:00
Bill Wendling
85de1e5bad Whitespace changes, comment clarification. No functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91274 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 06:51:19 +00:00
Evan Cheng
dd99f3a7dc Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91223 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 20:03:14 +00:00
Evan Cheng
04ab19cb14 Add comment about potential partial register stall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91220 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 18:55:26 +00:00
Evan Cheng
15b0d97068 Fix an obvious bug. No test case since LEA16r is not being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91219 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 18:51:56 +00:00
Dan Gohman
87862e77bb Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 21:31:27 +00:00
Anton Korobeynikov
817a46454a Honour setHasCalls() set from isel. 
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91144 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 19:39:55 +00:00
Evan Cheng
656e51454a Add support to 3-addressify 16-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91104 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 06:01:48 +00:00
Evan Cheng
c363094e04 Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. 
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90984 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 21:00:30 +00:00
Evan Cheng
7bd6478cd6 Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 01:53:58 +00:00
Evan Cheng
64fa4a9584 Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90922 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-09 01:36:00 +00:00
Dan Gohman
d84ea47b89 Don't enable the post-RA scheduler on x86 except at -O3. In its 
current form, it is too expensive in compile time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-07 19:04:31 +00:00
Dan Gohman
864e2efce2 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of 
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-05 00:44:40 +00:00
David Greene
adbc23cae1 Remove an unneeded include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-04 23:55:07 +00:00
David Greene
29dbf50b18 Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90608 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-04 22:38:46 +00:00
Chris Lattner
bf108bdee5 yay for case insensitive file systems (?) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90370 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-03 01:10:05 +00:00
Chris Lattner
7896c9f436 improve portability to avoid conflicting with std::next in c++'0x. 
Patch by Howard Hinnant!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-03 00:50:42 +00:00
Jim Grosbach
e27d205d5d Factor the stack alignment calculations out into a target independent pass. 
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90336 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-02 19:30:24 +00:00