Commit Graph

21557 Commits

Author SHA1 Message Date
Akira Hatanaka
f93b863066 Emit all directives except for ".cprestore" during asm printing rather than emit
them as machine instructions. Directives ".set noat" and ".set at" are now
emitted only at the beginning and end of a function except in the case where
they are emitted to enclose .cpload with an immediate operand that doesn't fit
in 16-bit field or unaligned load/stores.

Also, make the following changes:
- Remove function isUnalignedLoadStore and use a switch-case statement to
  determine whether an instruction is an unaligned load or store.

- Define helper function CreateMCInst which generates an instance of an MCInst
  from an opcode and a list of operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28 00:22:50 +00:00
Akira Hatanaka
d0b5c65b16 Mark flag neverHasSideEffects of pattern-less instructions that do not have
any side effects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28 00:21:37 +00:00
Benjamin Kramer
f2fd23b062 Add a note about a cute little fabs optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 22:42:42 +00:00
Benjamin Kramer
c8591a451a Add two missed instcombines related to compares with nsw arithmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 22:03:19 +00:00
Akira Hatanaka
ced8af1107 Remove trailing white space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 20:35:51 +00:00
Akira Hatanaka
95f95a783f Add member EmitNOAT and its setter and getter functions to class MipsFunctionInfo.
If EmitNOAT is true, directives ".set noat" and ".set at" are emitted at the
beginning and end of a function. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 19:08:42 +00:00
Jakob Stoklund Olesen
805543068e ARMLoadStoreOptimizer invalidates register liveness.
This pass tries to update kill flags, but there are still many bugs.
Passes after the load/store optimizer don't need accurate liveness, so
don't even try.

<rdar://problem/11101911>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 17:33:52 +00:00
Jakob Stoklund Olesen
33fa614b16 Invalidate liveness in Thumb2ITBlockPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 17:06:06 +00:00
Craig Topper
4e02f23de2 Prune some includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 07:54:11 +00:00
Craig Topper
c89c744b69 Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 07:21:54 +00:00
Akira Hatanaka
b4549e1c0e Pass the llvm IR pointer value and offset to the constructor of
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA 
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value. 

The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 03:13:56 +00:00
Akira Hatanaka
13daee3082 Fix bug in LowerConstantPool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153498 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 02:55:31 +00:00
Akira Hatanaka
56e1ed53f5 Add T9 to the list of live-in registers of the entry basic block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153497 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 02:46:25 +00:00
Akira Hatanaka
59182f9425 Retrieve and add the offset of a symbol in applyFixup rather than retrieve and
set it in MipsMCCodeEmitter::getMachineOpValue. Assert in getMachineOpValue if
MachineOperand MO is of an unexpected type. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 02:33:05 +00:00
Akira Hatanaka
d7edf7edd4 Define function MipsGetSymAndOffset which returns a fixup's symbol and the
offset applied to it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153493 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 02:04:18 +00:00
Akira Hatanaka
bca9c25dab Rewrite computation of Value in adjustFixupValue so that the upper 48-bits are
cleared. No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153491 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 01:50:08 +00:00
Akira Hatanaka
7067d4e4de Reserve hardware registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 00:40:56 +00:00
Evan Cheng
e279f5953e ARM has a peephole optimization which looks for a def / use pair. The def
produces a 32-bit immediate which is consumed by the use. It tries to 
fold the immediate by breaking it into two parts and fold them into the
immmediate fields of two uses. e.g
       movw    r2, #40885
       movt    r3, #46540
       add     r0, r0, r3
=>
       add.w   r0, r0, #3019898880
       add.w   r0, r0, #30146560
;
However, this transformation is incorrect if the user produces a flag. e.g.
       movw    r2, #40885
       movt    r3, #46540
       adds    r0, r0, r3
=>
       add.w   r0, r0, #3019898880
       adds.w  r0, r0, #30146560
Note the adds.w may not set the carry flag even if the original sequence
would.

rdar://11116189


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153484 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26 23:31:00 +00:00
Craig Topper
f1d0f7781e Prune some includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26 06:58:25 +00:00
Craig Topper
0e5233a9e5 Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26 00:45:15 +00:00
Craig Topper
acf2077ca4 Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25 23:49:58 +00:00
Craig Topper
805853bc59 Prune some includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153415 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25 18:10:17 +00:00
Hal Finkel
179a4ddd1f Fix small-integer VAARG on SVR4 ABI PPC64.
The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that
are smaller than 64 bits be zero extended to 64 bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-24 03:53:55 +00:00
Justin Holewinski
41085086b2 PTX: Fix predicate logic bug
Code such as:

%vreg100 = setcc %vreg10, -1, SETNE
brcond %vreg10, %tgt

was being incorrectly morphed into

%vreg100 = and %vreg10, 1
brcond %vreg10, %tgt

where the 'and' instruction could be eliminated since
such logic is on 1-bit types in the PTX back-end, leaving
us with just:

brcond %vreg10, %tgt

which essentially gives us inverted branch conditions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-24 01:23:20 +00:00
Jim Grosbach
7a46525056 ARM tidy up ARMConstantIsland.cpp.
No functional change, just tidy up the code and nomenclature a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23 23:07:03 +00:00
Benjamin Kramer
901b85888c Include cstdio in a few place that depended on getting it transitively through StringExtras.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23 11:35:30 +00:00
Benjamin Kramer
e68e77569f Move ftostr into its last user (cppbackend) and simplify it a bit.
New code should use raw_ostream.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153326 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23 11:26:29 +00:00
Eric Christopher
a443e5b1f1 Remove the C backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23 05:50:46 +00:00
Silviu Baranga
6fe310e155 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 14:14:49 +00:00
Silviu Baranga
b7c2ed6664 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 13:24:43 +00:00
Silviu Baranga
a0c48eb8f6 Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 13:14:39 +00:00
Craig Topper
63bd926a41 Remove some unnecessary forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 06:52:14 +00:00
Hal Finkel
f2f6182f6a PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large offsets. Fixes PR12203.
I don't have a small test case yet, but I'll try to construct one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22 05:28:19 +00:00
Kevin Enderby
f0586f08df Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 20:54:32 +00:00
Joerg Sonnenberger
d9e85ef08b Put Is64BitMemOperand into !defined(NDEBUG) for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 14:09:26 +00:00
Benjamin Kramer
47817f30f2 Use a signed value for this enum to avoid spuriuos warnings from gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 13:48:11 +00:00
Joerg Sonnenberger
4fd3d29275 Fix generation of the address size override prefix. Add assertions for
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 05:48:07 +00:00
Craig Topper
9be7c94ccd Add typecast to silence -Wswitch warning introduced by r153153.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153155 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 02:28:53 +00:00
Craig Topper
3d092dbb91 Spacing fixes and using 'unsigned' instead of 'int' to index to select shuffle elements for consistency with other shuffle code in X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 02:14:01 +00:00
Akira Hatanaka
fb54afbcb8 Incremental big endian patch by Jack Carter.
These changes allow us to compile big endian from the command line for 32 bit
Mips targets. This patch will result in code and data actually being produced
in the correct endianess.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21 00:52:01 +00:00
Chad Rosier
1b1fdc0599 [avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to
vextractf128 with 128-bit mem dest.

Combines

	vextractf128 $0, %ymm0, %xmm0
	vmovaps %xmm0, (%rdi)

to

    vextractf128 $0, %ymm0, (%rdi)

rdar://11082570


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 21:43:40 +00:00
Evan Cheng
03a1852538 Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153135 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 21:28:05 +00:00
Matt Beaumont-Gay
98a27acc6b remove unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:52:05 +00:00
Chad Rosier
a3bfdf536e [avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give
precedence over the VINSERTF128 avx1 patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:45:07 +00:00
Bob Wilson
aaa1e2f820 Require a base pointer for stack realignment when SP may vary dynamically.
ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects
but not for stack adjustments around calls.  Use hasReservedCallFrame() to
check for both.  The hasBasePointer function was already correctly checking
both conditions, so the effect of this was that a base pointer would be used
without checking whether the base pointer register could be reserved. I don't
have a small testcase for this.

<rdar://problem/11075906>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:28:25 +00:00
Bob Wilson
055a8127c9 Remove some redundant checks.
ARMFrameLowering::hasReservedCallFrame is already checking for variable
sized objects, so there's no point in checking it twice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 19:28:22 +00:00
Chad Rosier
666da1611a Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 18:38:33 +00:00
Chad Rosier
36a273a76c [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove
whitespace from test case.  No functional change intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 18:24:55 +00:00
Kevin Enderby
9f2e160f7a Fix assembling ARM vst2 instructions with double-spaced registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:41:51 +00:00
Jim Grosbach
07cdd80ccc ARM non-scattered MachO relocations for movw/movt.
Needed when building -mdynamic-no-pic code.

rdar://10459256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:25:45 +00:00