6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-06 05:06:45 +00:00
Code Issues Projects Releases Wiki Activity
78,632 Commits 39 Branches 0 Tags 277 MiB
feb468ab24
Commit Graph

51583 Commits

Author SHA1 Message Date
Craig Topper
cb6bd11bd6 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 09:04:59 +00:00
Craig Topper
34671b812a Merge floating point and integer UNPCK X86ISD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 08:21:25 +00:00
Craig Topper
3d8c2ce3e4 Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:31:16 +00:00
Jim Grosbach
23261af193 ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:03:45 +00:00
Craig Topper
1ff73d7a67 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:59:07 +00:00
Jim Grosbach
df33e0d05e Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:49:29 +00:00
Bruno Cardoso Lopes
ff452f5349 Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes
a00a62acd0 Explicit symbols for gnu mimicing relocations. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145911 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:42 +00:00
Bruno Cardoso Lopes
2bcc789a9d Add register HWR29 numbering. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:36 +00:00
Andrew Trick
8a5d792944 LSR: prune undesirable formulae early. 
It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145906 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:13:31 +00:00
Evan Cheng
89dae971b1 Mix some minor misuse of MachineBasicBlock iterator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 02:49:06 +00:00
Pete Cooper
d3743fc092 Removed isWinToJoinCrossClass from the register coalescer. 
The new register allocator is much more able to split back up ranges too constrained by register classes.

Fixes <rdar://problem/10466609>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145899 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 02:06:50 +00:00
Lang Hames
bae56b4c21 Kill off the LoopSplitter. It's not being used or maintained. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:57:59 +00:00
Bill Wendling
80caf9c273 Add a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:57:48 +00:00
Jim Grosbach
cb86509e7a Tidy up value checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:53:17 +00:00
NAKAMURA Takumi
6482e91149 MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145894 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:48:32 +00:00
Lang Hames
9ad7e07a0f Update PBQP's analysis usage to reflect the requirements of the inline spiller. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145893 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:45:57 +00:00
Chad Rosier
ed42c5f778 [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
3e572ac2fb Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen
8c741b8064 Use logarithmic units for basic block alignment. 
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:26:19 +00:00
Bill Wendling
79df986c60 The compact encoding of the registers are 3-bits each. Make sure we shift the 
value over that much.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145888 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:26:14 +00:00
Jim Grosbach
d9a6e8978d Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen
e80fba0e6c Use an existing function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145883 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:51:12 +00:00
Jim Grosbach
370b78d795 Move target-specific logic out of generic MCAssembler. 
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:47:03 +00:00
Nick Lewycky
7c06741004 Expose a switch for the new gcov format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145880 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:29:13 +00:00
Chad Rosier
dce42b75dc Probably not a good idea to convert a single vector load into a memcpy. We 
don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:19:08 +00:00
Jim Grosbach
f68a26b5d8 Tidy up. Hard tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145878 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:13:09 +00:00
Jim Grosbach
f77d5b14af Switch MCAssembler to method names starting w/ lower-case. 
per http://llvm.org/docs/CodingStandards.html#ll_naming

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:03:48 +00:00
Jim Grosbach
f503ef6800 Simple branch relaxation for Thumb2 Bcc instructions. 
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 23:45:46 +00:00
Nick Lewycky
aa21e417f2 Silence tsan false-positives (tsan can't track things which are only safe due to 
memory fences) in statistics registration, which works the same way that
ManagedStatic registration does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 23:07:05 +00:00
Chad Rosier
a4b6fd5be0 Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145866 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:53:09 +00:00
Chad Rosier
d8bd26ee24 Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio 
where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145865 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:37:00 +00:00
Jim Grosbach
713c70238c Tweak ADDrr fix. Bad check for explicit .w 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:27:04 +00:00
Jim Grosbach
927b9df4c6 Thumb2 prefer ADD register encoding T2 to T3 when possible. 
rdar://10529664


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:16:39 +00:00
Akira Hatanaka
d6bc5237d8 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:26:34 +00:00
Akira Hatanaka
cee46abc16 Split ExtIns into two base classes and have instructions EXT and INS derive from 
them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:14:28 +00:00
Jim Grosbach
da84786bee Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:06:26 +00:00
Akira Hatanaka
2bf08ec854 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:03:03 +00:00
Jim Grosbach
253ef7a779 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:29:59 +00:00
Jim Grosbach
422faab909 Fix previous commit. Oops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145844 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:12:26 +00:00
Jim Grosbach
45755a77ec Tidy up. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:09:44 +00:00
Jim Grosbach
afb500ace1 ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145842 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 19:55:46 +00:00
Hal Finkel
3fd0018af1 enable PPC register scavenging by default (update tests and remove some FIXMEs) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:55:17 +00:00
Hal Finkel
9489487f98 don't include CR bit subregs in callee-saved list 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145818 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:55:12 +00:00
Hal Finkel
2e313caa36 add register pressure for CR regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145816 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:54:17 +00:00
Benjamin Kramer
4da7f90b17 Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks. 
- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:23:27 +00:00
Craig Topper
1dc0fbc168 Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 07:27:14 +00:00
Craig Topper
beabc6cc6d Clean up and optimizations to the X86 shuffle lowering code. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145803 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 06:56:46 +00:00
Nadav Rotem
1608769abe Add support for vectors of pointers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 06:29:09 +00:00
Eric Christopher
309bedd7bc Add inline subprogram names to the name lookup table since they may 
not get there any other way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145789 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-04 06:02:38 +00:00
Bob Wilson
6ce2deacef Fix 80-column issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-04 00:52:23 +00:00
Anton Korobeynikov
0cb2a45cce Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
80b1ae9292 Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 
AnalyzeBranch doesn't change the successor, just the order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 21:24:48 +00:00
Benjamin Kramer
a86bfc1071 Simplify code. No functionality change. 
-3% on ARMDissasembler.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 16:18:22 +00:00
Benjamin Kramer
c00c05f8f5 Clear the new cache. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145771 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 15:19:55 +00:00
Benjamin Kramer
feb9b4bc3b Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache just to remove no blocks from the maps. 
-15% on ARMDisassembler.cpp (Release build).  It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145770 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 15:16:45 +00:00
Sanjoy Das
199ce33b3b Check for stack space more intelligently. 
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit.  This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit.  This should result in lesser calls to __morestack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 09:32:07 +00:00
Sanjoy Das
40f8222e1e Fix a bug in the x86-32 code generated for segmented stacks. 
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp.  This isn't correct since __morestack expects the call
to be followed directly by a ret.

This commit also adjusts the relevant test-case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145765 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 09:21:07 +00:00
Nick Lewycky
3604924799 Creating multiple JITs on X86 in multiple threads causes multiple writes (of 
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145745 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 02:45:50 +00:00
Chad Rosier
9eff1e33f6 [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 02:21:57 +00:00
Pete Cooper
de2e27cc52 Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur 
Turns out long long + unsigned long long is unsigned.  Doh!

Fixes http://llvm.org/bugs/show_bug.cgi?id=11455

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145731 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 00:04:30 +00:00
Chad Rosier
24fbf2bf16 Add support for constant folding the pow intrinsic. 
rdar://10514247

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 00:00:03 +00:00
Jim Grosbach
587f5062b9 ARM NEON VEXT aliases for data type suffices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 23:34:39 +00:00
Jim Grosbach
e40ab244c1 ARM VEXT tighten up operand classes a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:57:57 +00:00
Jim Grosbach
84defb51ca ARM VST1 single lane assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:34:51 +00:00
Nick Lewycky
8a8d479214 Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:16:29 +00:00
Jim Grosbach
872eedbb3a ARM VLD1 single lane assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:01:52 +00:00
Jim Grosbach
204aa64f30 ARM encoder method needs the physical register number, not the enum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 22:01:25 +00:00
Chad Rosier
b74c865841 [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 20:25:18 +00:00
Jim Grosbach
dad2f8e7fb Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:52:30 +00:00
Benjamin Kramer
30fe1ae20d Fix quadratic behavior in InlineFunction by fetching the personality function of the callee once and not for every invoke in the caller. 
The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145690 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:37:31 +00:00
Jim Grosbach
94f2dc90a5 Check for error after InstantiateMultclassDef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 18:33:03 +00:00
Jan Sjödin
ce25d26b40 Add XOP feature flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 15:14:37 +00:00
Craig Topper
f8363305eb Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145681 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 08:18:41 +00:00
Craig Topper
138a5c66b9 Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 07:16:01 +00:00
Hal Finkel
826941a0af remove unneeded FIXME comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 04:58:17 +00:00
Hal Finkel
db809e0eb7 make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145677 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 04:58:07 +00:00
Hal Finkel
64c34e2535 update PPC 940 hazard rec. to function in postRA mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 04:58:02 +00:00
Chad Rosier
aab8e28d5e Fix a few more places where TargetData/TargetLibraryInfo is not being passed. 
Add FIXMEs to places that are non-trivial to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 01:26:24 +00:00
Jim Grosbach
7636bf6530 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 00:35:16 +00:00
Chad Rosier
21646e8bec Abuse of mass replace isn't warranted even when the build is failing. Thanks 
for the suggestion, Eric.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 23:16:03 +00:00
Chad Rosier
ca3043101f Fix build by not assuming TLI is guaranteed. Will have to track down cases where 
TLI isn't being passed to ensure we don't miss opportunities to fold calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 22:38:31 +00:00
Chad Rosier
aebc3aae3f Prevent library calls from being folded if -fno-builtin has been specified. 
rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 22:14:50 +00:00
Dylan Noblesmith
fe0926d773 CodeGen: fix CMake build 
Missing file from r145629.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:49:23 +00:00
Dylan Noblesmith
d95e67dac0 ExecutionEngine: honor optimization level 
It was getting ignored after r144788.

Also fix an accidental implicit cast from the OptLevel enum
to an optional bool argument. MSVC warned on this, but gcc
didn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:49:21 +00:00
Chad Rosier
00737bdb48 Last bit of TargetLibraryInfo propagation. Also fixed a case for TargetData 
where it appeared beneficial to pass.
More of rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:29:16 +00:00
Anshuman Dasgupta
dc81e5da27 Add a deterministic finite automaton based packetizer for VLIW architectures 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:10:21 +00:00
David Blaikie
18c7ec1344 Fix unreachable return & simplify some branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145627 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 20:58:30 +00:00
Sanjoy Das
fc9261279a Dummy commit to check commit access. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 19:15:08 +00:00
Pete Cooper
165695d261 Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 19:13:26 +00:00
Kostya Serebryany
cc1d856d8e [asan] two minor fixes: use UnreachableInst after the neverreturn function call; use report_fatal_error when blacklist file can not be found 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145611 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 18:54:53 +00:00
Chad Rosier
fbd828d8e1 Add missing functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 18:26:19 +00:00
Benjamin Kramer
618f89f22a Autodetect bulldozers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 18:24:17 +00:00
Chad Rosier
32b6c59ad0 Add a few more functions to TargetLibraryInfo. More of rdar://10500969. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 17:54:37 +00:00
Eric Christopher
7d5a61e975 For 64-bit the rest of the general regs are ok for the q constraint. Make 
sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 08:12:41 +00:00
David Blaikie
0becc96b24 Add some missing anchors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 08:00:17 +00:00
Eli Friedman
522fb8cc01 Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145573 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 04:49:21 +00:00
Pete Cooper
65a6b57c33 Added instcombine pattern to spot comparing -val or val against 0. 
(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"

Fixes <rdar://problem/10482509>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145563 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 03:58:40 +00:00
Chad Rosier
618c1dbd29 Propagate TargetLibraryInfo throughout ConstantFolding.cpp and 
InstructionSimplify.cpp.  Other fixups as needed.
Part of rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 03:08:23 +00:00