Tom Stellard 0bbfc9313c R600/SI: Add pattern for rotr ... Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-20 15:02:24 +00:00
..
InstPrinter	R600: Improve texture handling	2013-05-17 16:50:20 +00:00
MCTargetDesc	Fix the build in c++11 mode.	2013-05-17 22:45:52 +00:00
TargetInfo
AMDGPU.h	R600: Improve texture handling	2013-05-17 16:50:20 +00:00
AMDGPU.td
AMDGPUAsmPrinter.cpp	R600: Emit config values in register / value pairs	2013-05-06 17:50:51 +00:00
AMDGPUAsmPrinter.h	R600: Emit used GPRs count	2013-04-17 15:17:25 +00:00
AMDGPUCallingConv.td	R600/SI: Add support for buffer stores v2	2013-04-05 23:31:51 +00:00
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUIndirectAddressing.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td	R600: Swap the legality of rotl and rotr	2013-05-20 15:02:19 +00:00
AMDGPUInstructions.td	R600: Swap the legality of rotl and rotr	2013-05-20 15:02:19 +00:00
AMDGPUIntrinsics.td
AMDGPUISelLowering.cpp	R600: Swap the legality of rotl and rotr	2013-05-20 15:02:19 +00:00
AMDGPUISelLowering.h	R600: Swap the legality of rotl and rotr	2013-05-20 15:02:19 +00:00
AMDGPUMachineFunction.cpp	R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE	2013-04-26 18:32:24 +00:00
AMDGPUMachineFunction.h	R600/SI: Share code recording ShaderTypeAttribute between generations	2013-04-01 21:47:53 +00:00
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUStructurizeCFG.cpp	R600: fix DenseMap with pointer key iteration in the structurizer	2013-03-26 10:24:20 +00:00
AMDGPUSubtarget.cpp	R600: Factorize Fetch size limit inside AMDGPUSubTarget	2013-05-17 16:49:55 +00:00
AMDGPUSubtarget.h	R600: Factorize Fetch size limit inside AMDGPUSubTarget	2013-05-17 16:49:55 +00:00
AMDGPUTargetMachine.cpp	R600: Improve texture handling	2013-05-17 16:50:20 +00:00
AMDGPUTargetMachine.h
AMDIL7XXDevice.cpp
AMDIL7XXDevice.h
AMDIL.h	R600/SI: remove SGPR address space v2	2013-03-07 09:03:59 +00:00
AMDILBase.td	R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions	2013-04-30 00:13:39 +00:00
AMDILCFGStructurizer.cpp	R600: Fix JUMP handling so that MachineInstr verification can occur	2013-03-11 18:15:06 +00:00
AMDILDevice.cpp
AMDILDevice.h
AMDILDeviceInfo.cpp	R600/SI: Add processor type for Hainan asic	2013-05-14 14:42:56 +00:00
AMDILDeviceInfo.h
AMDILDevices.h
AMDILEvergreenDevice.cpp
AMDILEvergreenDevice.h
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td
AMDILISelDAGToDAG.cpp	ArrayRefize getMachineNode(). No functionality change.	2013-04-19 22:22:57 +00:00
AMDILISelLowering.cpp	R600: Swap the legality of rotl and rotr	2013-05-20 15:02:19 +00:00
AMDILNIDevice.cpp
AMDILNIDevice.h
AMDILRegisterInfo.td
AMDILSIDevice.cpp
AMDILSIDevice.h
CMakeLists.txt	R600: Improve texture handling	2013-05-17 16:50:20 +00:00
LLVMBuild.txt
Makefile
Processors.td	R600/SI: Add processor type for Hainan asic	2013-05-14 14:42:56 +00:00
R600ControlFlowFinalizer.cpp	R600: Some factorization	2013-05-17 16:50:02 +00:00
R600Defines.h	R600: Relax some vector constraints on Dot4.	2013-05-17 16:50:32 +00:00
R600EmitClauseMarkers.cpp	R600: Relax some vector constraints on Dot4.	2013-05-17 16:50:32 +00:00
R600ExpandSpecialInstrs.cpp	R600: Relax some vector constraints on Dot4.	2013-05-17 16:50:32 +00:00
R600InstrInfo.cpp	R600: Relax some vector constraints on Dot4.	2013-05-17 16:50:32 +00:00
R600InstrInfo.h	R600: Relax some vector constraints on Dot4.	2013-05-17 16:50:32 +00:00
R600Instructions.td	R600: Swap the legality of rotl and rotr	2013-05-20 15:02:19 +00:00
R600Intrinsics.td	R600: Improve texture handling	2013-05-17 16:50:20 +00:00
R600ISelLowering.cpp	R600: Swap the legality of rotl and rotr	2013-05-20 15:02:19 +00:00
R600ISelLowering.h	Add LLVMContext argument to getSetCCResultType	2013-05-18 00:21:46 +00:00
R600MachineFunctionInfo.cpp	R600/SI: Share code recording ShaderTypeAttribute between generations	2013-04-01 21:47:53 +00:00
R600MachineFunctionInfo.h	R600: Use .AMDGPU.config section to emit stacksize	2013-04-23 17:34:12 +00:00
R600MachineScheduler.cpp	R600: Use bottom up scheduling algorithm	2013-05-17 16:50:56 +00:00
R600MachineScheduler.h	R600: Use bottom up scheduling algorithm	2013-05-17 16:50:56 +00:00
R600Packetizer.cpp	R600: Relax some vector constraints on Dot4.	2013-05-17 16:50:32 +00:00
R600RegisterInfo.cpp	R600: Use bottom up scheduling algorithm	2013-05-17 16:50:56 +00:00
R600RegisterInfo.h	R600: Use bottom up scheduling algorithm	2013-05-17 16:50:56 +00:00
R600RegisterInfo.td	R600: Rename 128 bit registers.	2013-05-17 16:50:09 +00:00
R600Schedule.td	R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips	2013-04-30 00:14:17 +00:00
R600TextureIntrinsicsReplacer.cpp	R600: Improve texture handling	2013-05-17 16:50:20 +00:00
SIAnnotateControlFlow.cpp
SIDefines.h	R600/SI: Emit config values in register value pairs.	2013-04-15 17:51:35 +00:00
SIInsertWaits.cpp	R600/SI: fix inserting waits for all defines	2013-03-18 11:33:45 +00:00
SIInstrFormats.td	R600/SI: Use the same names for VOP3 operands and encoding fields	2013-05-20 15:02:08 +00:00
SIInstrInfo.cpp	R600/SI: dynamical figure out the reg class of MIMG	2013-04-10 08:39:16 +00:00
SIInstrInfo.h	R600/SI: adjust writemask to only the used components	2013-04-10 08:39:08 +00:00
SIInstrInfo.td	R600/SI: Add patterns for 64-bit shift operations	2013-05-20 15:02:12 +00:00
SIInstructions.td	R600/SI: Add pattern for rotr	2013-05-20 15:02:24 +00:00
SIIntrinsics.td	R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode	2013-05-06 23:02:19 +00:00
SIISelLowering.cpp	R600/SI: Make fitsRegClass() operands const	2013-05-20 15:02:01 +00:00
SIISelLowering.h	R600/SI: Make fitsRegClass() operands const	2013-05-20 15:02:01 +00:00
SILowerControlFlow.cpp	R600/SI: replace WQM intrinsic	2013-03-26 14:03:50 +00:00
SIMachineFunctionInfo.cpp	R600/SI: Share code recording ShaderTypeAttribute between generations	2013-04-01 21:47:53 +00:00
SIMachineFunctionInfo.h	R600/SI: Share code recording ShaderTypeAttribute between generations	2013-04-01 21:47:53 +00:00
SIRegisterInfo.cpp	R600/SI: switch back to RegPressure scheduling	2013-03-26 14:04:02 +00:00
SIRegisterInfo.h	R600/SI: switch back to RegPressure scheduling	2013-03-26 14:04:02 +00:00
SIRegisterInfo.td	R600/SI: dynamical figure out the reg class of MIMG	2013-04-10 08:39:16 +00:00
SISchedule.td