Nate Begeman 905a29152f Implement more complete and correct codegen for bitfield inserts, as tested
by the recently committed rlwimi.ll test file.  Also commit initial code
for bitfield extract, although it is turned off until fully debugged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17207 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-24 10:33:30 +00:00
..
2004-10-23 04:59:22 +00:00
2004-10-23 20:29:24 +00:00
2004-10-10 16:26:13 +00:00

TODO:
* implement not-R0 register GPR class
* fix rlwimi generation to be use-and-def
* implement scheduling info
* implement powerpc-64 for darwin
* implement powerpc-64 for aix
* use stfiwx in float->int
* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

Currently failing tests that should pass:
* MultiSource
  |- Applications
  |  `- hbd: miscompilation