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ossc/ossc.sdc

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Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
### CPU clock constraints ###
create_clock -period 27MHz -name clk27 [get_ports clk27]
* Clean up some FPGA code * Wrap sampling phase setting * Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
2016-12-31 12:18:21 +00:00
set_input_delay -clock clk27 0 [get_ports {sda scl SD_CMD SD_DAT* *ALTERA_DATA0}]
set_false_path -from [get_ports {btn* ir_rx HDMI_TX_INT_N HDMI_TX_MODE}]
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
* Clean up some FPGA code * Wrap sampling phase setting * Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
2016-12-31 12:18:21 +00:00
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
### Scanconverter clock constraints ###
simplify timing constraints
2018-03-06 21:53:48 +00:00
create_clock -period 108MHz -name pclk_1x [get_ports PCLK_in]
Set fast output on HDMI_TX pins. Also adjust timing constraits to reflect working state with line3x at 162 MHz.
2020-06-14 09:16:49 +00:00
create_clock -period 54MHz -name pclk_2x_source [get_ports PCLK_in] -add
create_clock -period 54MHz -name pclk_3x_source [get_ports PCLK_in] -add
simplify timing constraints
2018-03-06 21:53:48 +00:00
create_clock -period 33MHz -name pclk_4x_source [get_ports PCLK_in] -add
create_clock -period 33MHz -name pclk_5x_source [get_ports PCLK_in] -add
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
#derive_pll_clocks
optimize clock network * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-05 21:26:50 +00:00
create_generated_clock -name pclk_2x -master_clock pclk_2x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 2 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
create_generated_clock -name pclk_3x -master_clock pclk_3x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 3 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
create_generated_clock -name pclk_4x -master_clock pclk_4x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 4 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
create_generated_clock -name pclk_5x -master_clock pclk_5x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 5 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
create_generated_clock -name pclk_27mhz -master_clock clk27 -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 1 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
simplify timing constraints
2018-03-06 21:53:48 +00:00
additional timing constraint fixes
2018-03-11 20:22:04 +00:00
# retrieve post-mapping clkmux output pin
optimize clock network * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-05 21:26:50 +00:00
set clkmux_output [get_pins scanconverter_inst|clkctrl1|outclk]
simplify timing constraints
2018-03-06 21:53:48 +00:00
additional timing constraint fixes
2018-03-11 20:22:04 +00:00
# specify postmux clocks which clock postprocess pipeline
optimize clock network * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-05 21:26:50 +00:00
create_generated_clock -name pclk_1x_postmux -master_clock pclk_1x -source [get_pins scanconverter_inst|clkctrl1|inclk[0]] -multiply_by 1 $clkmux_output
create_generated_clock -name pclk_2x_postmux -master_clock pclk_2x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
create_generated_clock -name pclk_3x_postmux -master_clock pclk_3x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
create_generated_clock -name pclk_4x_postmux -master_clock pclk_4x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
create_generated_clock -name pclk_5x_postmux -master_clock pclk_5x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
create_generated_clock -name pclk_27mhz_postmux -master_clock pclk_27mhz -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
simplify timing constraints
2018-03-06 21:53:48 +00:00
additional timing constraint fixes
2018-03-11 20:22:04 +00:00
# specify output clocks that drive PCLK output pin
simplify timing constraints
2018-03-06 21:53:48 +00:00
set pclk_out_port [get_ports HDMI_TX_PCLK]
optimize clock network * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-05 21:26:50 +00:00
create_generated_clock -name pclk_1x_out -master_clock pclk_1x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port
create_generated_clock -name pclk_2x_out -master_clock pclk_2x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
create_generated_clock -name pclk_3x_out -master_clock pclk_3x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
create_generated_clock -name pclk_4x_out -master_clock pclk_4x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
create_generated_clock -name pclk_5x_out -master_clock pclk_5x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
create_generated_clock -name pclk_27mhz_out -master_clock pclk_27mhz_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
derive_clock_uncertainty
# input delay constraints
Preliminary Line5x implementation
2017-01-28 01:37:57 +00:00
set TVP_dmin 0
set TVP_dmax 1.5
* Clean up some FPGA code * Wrap sampling phase setting * Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
2016-12-31 12:18:21 +00:00
set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
simplify timing constraints
2018-03-06 21:53:48 +00:00
foreach_in_collection c [get_clocks "pclk_1x pclk_*_source"] {
set_input_delay -clock $c -min $TVP_dmin $critinputs -add_delay
set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay
}
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
Set only HDMI_TX VREF pins to fast output. From the Cyclone IV device handbook: > When you use the VREF pin as a regular input or output, you can expect > a reduced performance of toggle rate and tCO because of higher pin > capacitance. Previously, we had set all HDMI_TX pins to fast output, but doing so produces some worrying timing violations which were masked over by relaxation of the SDC constraints. With fast output enabled, actually fixing the timing constraints would require substantial RTL optimization. Instead, by only setting fast output on the VREF pins, I'm able to avoid the glitching that would occur without any fast output pins when displaying high clock rate line3x output, while also allowing fitter enough flexibility to avoid timing violations. In addition, this commit restores the previously relaxed HDMI_TX timing constraints to those documented in the IT6613 datasheet.
2020-06-20 23:31:55 +00:00
# output delay constraints as documented in the IT6613 datasheet
# -- increased IT_Tsu from 1.0 to 1.5 due to #52
Set fast output on HDMI_TX pins. Also adjust timing constraits to reflect working state with line3x at 162 MHz.
2020-06-14 09:16:49 +00:00
set IT_Tsu 1.5
Set only HDMI_TX VREF pins to fast output. From the Cyclone IV device handbook: > When you use the VREF pin as a regular input or output, you can expect > a reduced performance of toggle rate and tCO because of higher pin > capacitance. Previously, we had set all HDMI_TX pins to fast output, but doing so produces some worrying timing violations which were masked over by relaxation of the SDC constraints. With fast output enabled, actually fixing the timing constraints would require substantial RTL optimization. Instead, by only setting fast output on the VREF pins, I'm able to avoid the glitching that would occur without any fast output pins when displaying high clock rate line3x output, while also allowing fitter enough flexibility to avoid timing violations. In addition, this commit restores the previously relaxed HDMI_TX timing constraints to those documented in the IT6613 datasheet.
2020-06-20 23:31:55 +00:00
set IT_Th -0.5
Fix HDTV mode parameters
2017-05-30 18:16:03 +00:00
set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
simplify timing constraints
2018-03-06 21:53:48 +00:00
foreach_in_collection c [get_clocks pclk_*_out] {
set_output_delay -clock $c -min $IT_Th $critoutputs_hdmi -add
set_output_delay -clock $c -max $IT_Tsu $critoutputs_hdmi -add
}
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
### CPU/scanconverter clock relations ###
# Treat CPU clock asynchronous to pixel clocks
simplify timing constraints
2018-03-06 21:53:48 +00:00
set_clock_groups -asynchronous -group \
optimize clock network * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-05 21:26:50 +00:00
{clk27 pclk_27mhz pclk_27mhz_postmux pclk_27mhz_out} \
simplify timing constraints
2018-03-06 21:53:48 +00:00
{pclk_1x pclk_1x_postmux pclk_1x_out} \
{pclk_2x_source pclk_2x pclk_2x_postmux pclk_2x_out} \
{pclk_3x_source pclk_3x pclk_3x_postmux pclk_3x_out} \
{pclk_4x_source pclk_4x pclk_4x_postmux pclk_4x_out} \
{pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out}
Sync processing rewritten and some issues fixed * add 480i/576i line3x/4x * clean up RTL and SDC * update AVI infoframe properly * add HDMI IT content option
2017-05-18 20:35:43 +00:00
# Ignore paths from registers which are updated only at leading edge of vsync
optimize clock network * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-05 21:26:50 +00:00
set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|SL_* scanconverter_inst|LT_POS_*}]
Sync processing rewritten and some issues fixed * add 480i/576i line3x/4x * clean up RTL and SDC * update AVI infoframe properly * add HDMI IT content option
2017-05-18 20:35:43 +00:00
# Ignore paths from registers which are updated only at leading edge of hsync
optimize clock network * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-05 21:26:50 +00:00
#set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
Ignore paths which use shared clock lines. Quartus calculates fmax (the theoretical maximum clock rate) based on the entirety of the logic between registers. In the case of the pclk_* lines, this includes some invalid paths which cross between the 3x <-> 2x and 5x <-> 4x clock domains. This is because these clocks share output pins from the PLL, but the PLL is configured to output only one of these clocks at a time, and the correct output from the logic is selected via a multiplexer. Therefore these paths cannot co-occur. This has the effect of increasing the calculated fmax of these paths to: pclk_3x: 107.98 MHz -> 132.52 MHz pclk_5x: 162.23 MHz -> 170.33 MHz
2020-06-01 00:17:26 +00:00
# Ignore paths that cross clock domains from 3x to 2x and 5x to 4x, since they share a clock line, but cannot co-occur.
set_false_path -from [get_clocks {pclk_3x*}] -to [get_registers {scanconverter:scanconverter_inst|*_2x*}]
set_false_path -from [get_clocks {pclk_5x*}] -to [get_registers {scanconverter:scanconverter_inst|*_4x*}]
Update latency tester * Enable operation with all sources * Measure strobe length on low-persistence displays
2017-10-28 09:10:54 +00:00
# Ignore paths to latency tester sync regs
set_false_path -to [get_registers {lat_tester:lt0|mode_synced* lat_tester:lt0|VSYNC_in_* lat_tester:lt0|trigger_*}]
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
### JTAG Signal Constraints ###
#constrain the TCK port
#create_clock -name tck -period "10MHz" [get_ports altera_reserved_tck]
#cut all paths to and from tck
set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]
#constrain the TDI port
set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]
#constrain the TMS port
set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]
#constrain the TDO port
#set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo]
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