Apple-1-HW/verilog-apple-one
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63 Commits 3 Branches 0 Tags
586b006e88c7c75b2fcbd4d436479a473879dc73
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8 Commits

Author SHA1 Message Date
Niels Moseley
fe05766894 Fixed address lines of Basic ROM 2018-01-28 20:18:56 +01:00
Alan Garfield
69f1b53e18 added basic rom and fix uart issue on HX 2018-01-28 15:02:51 +11:00
Alan Garfield
0fc84e0b37 added reset logic to uart and CPU 2018-01-28 00:23:09 +11:00
Alan Garfield
abba4eeee6 added reset to cpu registers and made uart ignore first tx 2018-01-27 22:56:28 +11:00
Alan Garfield
bcaf9e6962 Yay got iverilog sim working! 2018-01-27 22:13:52 +11:00
Alan Garfield
149334259d Cleaned up mess, and added HX8K board top file 2018-01-27 13:40:59 +11:00
Niels Moseley
9beb3e5f5e Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
Alan Garfield
7bdccf3d1a move things around. 2018-01-27 00:21:05 +11:00