Olof Kindgren
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2226afe669
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Expose ROM/RAM files as top-level parameters
This allows file names to be overridden at compile-time.
It also gets rid of the ifdef SIM in the verilog components
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2018-02-12 14:04:00 +01:00 |
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Alan Garfield
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a4f13a87fe
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updated ROM paths to handle new board/buildenv structure
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2018-02-12 08:26:57 +11:00 |
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Alan Garfield
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b2ebc23e3a
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added license headers and tidied up
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2018-01-29 22:15:21 +11:00 |
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Alan Garfield
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119d077e1a
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Fixed differences for iceube2 and yosys
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2018-01-29 21:36:32 +11:00 |
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Alan Garfield
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2717184e71
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Added yosys support again, yay for FOSS!
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2018-01-29 17:45:01 +11:00 |
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Niels Moseley
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fe05766894
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Fixed address lines of Basic ROM
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2018-01-28 20:18:56 +01:00 |
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Alan Garfield
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69f1b53e18
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added basic rom and fix uart issue on HX
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2018-01-28 15:02:51 +11:00 |
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