Compare commits
57 Commits
| Author | SHA1 | Date |
|---|---|---|
Florian Reitz
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Florian Reitz
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@ -29,6 +29,7 @@ obj/
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[Rr]elease*/
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_ReSharper*/
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[Tt]est[Rr]esult*
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.vs/
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*.opendb
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**/Debug
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||||
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@ -213,3 +214,13 @@ Hardware/SD_A2\.b\$1
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*.tspec
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||||
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VHDL/_pace\.ucf
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||||
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VHDL/AppleIISd\.tim
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||||
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VHDL/AppleIISd\.jed
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||||
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||||
Firmware/AppleIISd.bin
|
||||
|
||||
Software/Flasher.bin
|
||||
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|
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|||
BIN
AppleIISd.bin
BIN
AppleIISd.bin
Binary file not shown.
|
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@ -1,18 +0,0 @@
|
|||
Qty Value Device Package Parts Description
|
||||
1 A2-50PINSLOT1-3 A2-50PIN-SL1-3 ST1 Apple ][ Peripheral Card Connector
|
||||
1 LEDSQR2X5 LED2X5 LED1 LED
|
||||
1 MA03-1 MA03-1 SV1 PIN HEADER
|
||||
1 MA06-1 MA06-1 SV2 PIN HEADER
|
||||
6 100k R-EU_R0603 R0603 R3, R5, R6, R7, R9, R11 RESISTOR, European symbol
|
||||
9 100n C-EUC0603K C0603K C1, C3, C4, C5, C6, C7, C11, C12, C13 CAPACITOR, European symbol
|
||||
1 104H-TDA0-R 104H-TDA0-R 104H-TDA0-R U$2
|
||||
3 10n C-EUC0603K C0603K C8, C9, C10 CAPACITOR, European symbol
|
||||
1 1u CPOL-EU153CLV-0405 153CLV-0405 C2 POLARIZED CAPACITOR, European symbol
|
||||
1 200 R-EU_R0603 R0603 R1 RESISTOR, European symbol
|
||||
1 2716 / 2732 2716 DIL24 IC3 MEMORY
|
||||
1 330 R-EU_R0603 R0603 R2 RESISTOR, European symbol
|
||||
1 470 R-EU_R0603 R0603 R4 RESISTOR, European symbol
|
||||
1 68k R-EU_R0603 R0603 R8 RESISTOR, European symbol
|
||||
1 74LS245N 74LS245N DIL20 IC1 Octal BUS TRANSCEIVER, 3-state
|
||||
1 LM317 LM317TL 317TL IC2 VOLTAGE REGULATOR
|
||||
1 XC9572XL XC9572_S44 S44 IC4
|
||||
129
AppleIISd.hex
129
AppleIISd.hex
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|
@ -1,129 +0,0 @@
|
|||
:10000000A220A200A203A20078A960853F203F00A1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
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||||
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||||
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||||
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||||
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|
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
|
@ -1,17 +0,0 @@
|
|||
{signal: [
|
||||
['Apple',
|
||||
{name: '7M', wave: 'n........', period: 2 },
|
||||
{name: 'Phi0', wave: 'hl......h......l..'},
|
||||
{name: 'Q3', wave: 'lh...l..h...l..h..'},
|
||||
{name: 'ADD', wave: 'x.....=.........x.', data: "IO-Address", phase: 0.5},
|
||||
{name: '/DEV_SEL',wave: 'h.......0......1..'},
|
||||
{},
|
||||
{name: 'R/W', wave: 'x.....=.........x.', phase: 0.5},
|
||||
{name: 'DATA', wave: 'x.....z..x.=....z.', phase: 0.5},
|
||||
],
|
||||
{},
|
||||
['Card',
|
||||
{name: 'Address', wave: 'x........=.......x'},
|
||||
{name: 'DATA', wave: 'x........z.=....z.', data: 'FromPeripheral', phase: 0.5},
|
||||
],
|
||||
]}
|
||||
BIN
AppleIISd.pdf
BIN
AppleIISd.pdf
Binary file not shown.
|
|
@ -3,7 +3,9 @@ Microsoft Visual Studio Solution File, Format Version 12.00
|
|||
# Visual Studio 14
|
||||
VisualStudioVersion = 14.0.25420.1
|
||||
MinimumVisualStudioVersion = 10.0.40219.1
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "AppleIISd", "AppleIISd.vcxproj", "{9EA7EC3D-1771-420F-932F-231A35ED1200}"
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "AppleIISd", "Firmware\AppleIISd.vcxproj", "{9EA7EC3D-1771-420F-932F-231A35ED1200}"
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Flasher", "Software\Flasher.vcxproj", "{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
|
|
@ -15,6 +17,10 @@ Global
|
|||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Debug|x86.Build.0 = Debug|Win32
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Release|x86.ActiveCfg = Release|Win32
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Release|x86.Build.0 = Release|Win32
|
||||
{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}.Debug|x86.ActiveCfg = Debug|Win32
|
||||
{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}.Debug|x86.Build.0 = Debug|Win32
|
||||
{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}.Release|x86.ActiveCfg = Release|Win32
|
||||
{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}.Release|x86.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,14 @@
|
|||
Qty Value Device Package Parts Description
|
||||
1 LEDSQR2X5 LED2X5 LED1 LED
|
||||
1 MA03-1 MA03-1 SV1 PIN HEADER
|
||||
1 MA06-1 MA06-1 SV2 PIN HEADER
|
||||
1 100k GE08R SIL9 RN1 SIL RESISTOR
|
||||
8 100n C-EUC0603K C0603K C1, C2, C4, C5, C6, C7, C8, C9 CAPACITOR, European symbol
|
||||
1 104H-TDA0-R 104H-TDA0-R 104H-TDA0-R U$2 SD Card Socket
|
||||
3 10n C-EUC0603K C0603K C10, C11, C12 CAPACITOR, European symbol
|
||||
2 10u/16V CPOL-EUA/3216-18R A/3216-18R C3, C13 POLARIZED CAPACITOR, European symbol
|
||||
1 28C64ASO 28C64ASO SO28W IC3 CMOS EEPROM
|
||||
1 470 R-EU_R0603 R0603 R4 RESISTOR, European symbol
|
||||
1 74LS245N 74LS245N DIL20 IC1 Octal BUS TRANSCEIVER, 3-state
|
||||
1 LM1117DTX-3.3 LM1117DTX-3.3 TO252 IC2
|
||||
1 XC9572XL XC9572_S44VQFP SQFP-S-10X10-44 IC4
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
:10000000A220A200A203A20078A960853F203F00A1
|
||||
:10001000BABD0001588DF807290F853FA80A0A0AC2
|
||||
:100020000A853EAA2CFFCFA000B907C9F00D0980B0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:1000F000FA7A2860182048CB80C900000000977564
|
||||
:100100009E81C0A9019D83C0A00AA9FF9D80C03C1B
|
||||
:1001100081C010FB88D0F5BD83C029FE9D83C0A996
|
||||
:100120002F8540A9C98541205FC92073C9C901D065
|
||||
:1001300065A93B8540A9C98541205FC9208AC9C9F5
|
||||
:1001400001D056A43FB9F805C9AAD04AA9478540AD
|
||||
:10015000A9C98541205FC92073C9A9538540A9C990
|
||||
:100160008541205FC92073C9C901F0E0C900D026CC
|
||||
:10017000A94D8540A9C98541205FC9208AC9C90008
|
||||
:10018000D014A43FB978042940F048BD83C00910B9
|
||||
:100190009D83C04CE5C84CFAC8A9478540A9C985CC
|
||||
:1001A00041205FC9A9598540A9C98541205FC9205F
|
||||
:1001B00073C9C901F0E3C900D0034CD3C8A9358580
|
||||
:1001C00040A9C98541205FC92073C9C901F0F6C99A
|
||||
:1001D00000D027A9418540A9C98541205FC9207366
|
||||
:1001E000C9C900D015BD83C009809D83C0BD81C031
|
||||
:1001F00009049D81C018A000900338A027BD83C0CA
|
||||
:1002000009019D83C09860204170706C655D5B53EF
|
||||
:10021000642076312E322E3220286329323032305B
|
||||
:1002200020466C6F7269616E20526569747A004075
|
||||
:1002300000000000954100000000F948000001AAFC
|
||||
:10024000875000000200FF7700000000FF7A0000E6
|
||||
:100250000000FF6940000000776900000000FF5ABD
|
||||
:10026000A000B1409D80C03C81C010FBC8C006907A
|
||||
:10027000F17A60A9FF9D80C03C81C010FBBD80C0A9
|
||||
:1002800030F148A9FF9D80C068602073C9485AA01A
|
||||
:10029000044C99C9A9FF9D80C03C81C010FBBD8062
|
||||
:1002A000C04888D0EFA43F6899F805689978056838
|
||||
:1002B00099F804689978047AA9FF9D80C06860DA8B
|
||||
:1002C0005AA63FA43EA5469DF805A5479D78059EE4
|
||||
:1002D000F8049E78049845432970F005A9029DF81A
|
||||
:1002E0000424431007BDF8041A9DF804A9103983AB
|
||||
:1002F000C0D011A0091EF8053E78053EF8043E78EE
|
||||
:100300000488D0F17AFA605AA43F9D80C0B978047D
|
||||
:100310009D80C0B9F8049D80C0B978059D80C0B9A2
|
||||
:10032000F8059D80C0A9FF9D80C02073C97A6048F0
|
||||
:10033000A9403C83C018F00138686048A9203C837C
|
||||
:10034000C018F001386860A542F00CC901F00BC973
|
||||
:1003500002F00AA90138604C60CA4C6ECA4CD7CA78
|
||||
:10036000A900203BCA9002A92BA2FFA0FF6020BFDA
|
||||
:10037000C9BD83C029FE9D83C0A9512007CAC900F9
|
||||
:10038000D050A9FF9D80C0BD80C0C9FED0F4BD8102
|
||||
:10039000C009109D81C0A9FF9D80C0A000BD80C084
|
||||
:1003A0009144C8D0F8E645BD80C09144C8D0F8C695
|
||||
:1003B00045BD80C0BD80C0BD80C0BD81C029EF9D4E
|
||||
:1003C00081C018A9000848BD83C009019D83C06889
|
||||
:1003D000286038A92780EE203BCAB06720BFC9BD7E
|
||||
:1003E00083C029FE9D83C0A9582007CAC900D04EEA
|
||||
:1003F000A9FF9D80C0A9FE9D80C0A000B1449D8042
|
||||
:10040000C0C8D0F8E645B1449D80C0C8D0F8C64504
|
||||
:10041000A9FF9D80C09D80C09D80C0BD80C0291F58
|
||||
:10042000C905D01A18A9000848A9FF9D80C0BD8041
|
||||
:10043000C0F0F6BD83C009019D83C068286038A95B
|
||||
:100440002780E438A92B80DFA004B9480048881031
|
||||
:10045000F9BABD0D0185481869039D0D01BD0E0156
|
||||
:10046000854969009D0E01A001B1488542C8B14887
|
||||
:10047000AAC8B14885498648A901A642E00AB01A2F
|
||||
:10048000B248DDDECCD027A001B148A43F99780660
|
||||
:100490008A0AAA20B2CBB002A900AAA00068994893
|
||||
:1004A00000C8C00590F78AA002A200C90160A90493
|
||||
:1004B00080E87CE8CC2043CCA43FB97806D018A5CE
|
||||
:1004C0004CF004A9213860A904924AA007B9FBCCDA
|
||||
:1004D000914A88D0F81860A64CF016CAF008CACA2B
|
||||
:1004E000F00FA9213860A901924AA8A900914A18E1
|
||||
:1004F00060A9E8A63E202FCAB0020910203BCA908E
|
||||
:10050000020904924AA001A9FF914AC8914AC8A9C8
|
||||
:1005100000914AA54CF00CA004B9FFCC914AC8C088
|
||||
:100520001990F618602043CCA64CF00FCAF00CCA04
|
||||
:10053000F006CAF00ACAF003A92138A9001860A978
|
||||
:100540001F3860A002B148854AC8B148854BC8B180
|
||||
:1005500048854C60206ECC900160A63EA43F4C6E56
|
||||
:10056000CA206ECC900160A63EA43F4CD7CAB97891
|
||||
:1005700006F044C901F00EC902F00EC903F010C91B
|
||||
:1005800004F0118032A53E8010A53E0980800AA5A6
|
||||
:100590003E3A8005A53E3A09808543A002B14885D0
|
||||
:1005A00044C8B1488545C8B1488546C8B148854763
|
||||
:1005B000C8B148D0061860A9113860A92D3860B9B3
|
||||
:1005C0007806F004A9001860A9113860B9780618F7
|
||||
:1005D000F003A9113860A9013860A9273860030326
|
||||
:1005E0000301030101010404B5CB54CC61CCBFCCA1
|
||||
:1005F00025CCCCCCD6CCD6CCDACCDACC4000000B97
|
||||
:10060000120000104150504C455D5B5344202020A7
|
||||
:100610002020202002000B1200000000000000003B
|
||||
:1006200000000000000000000000000000000000CA
|
||||
:1006300000000000000000000000000000000000BA
|
||||
:1006400000000000000000000000000000000000AA
|
||||
:10065000000000000000000000000000000000009A
|
||||
:10066000000000000000000000000000000000008A
|
||||
:10067000000000000000000000000000000000007A
|
||||
:10068000000000000000000000000000000000006A
|
||||
:10069000000000000000000000000000000000005A
|
||||
:1006A000000000000000000000000000000000004A
|
||||
:1006B000000000000000000000000000000000003A
|
||||
:1006C000000000000000000000000000000000002A
|
||||
:1006D000000000000000000000000000000000001A
|
||||
:1006E000000000000000000000000000000000000A
|
||||
:1006F00000000000000000000000000000000000FA
|
||||
:1007000000000000000000000000000000000000E9
|
||||
:1007100000000000000000000000000000000000D9
|
||||
:1007200000000000000000000000000000000000C9
|
||||
:1007300000000000000000000000000000000000B9
|
||||
:1007400000000000000000000000000000000000A9
|
||||
:100750000000000000000000000000000000000099
|
||||
:100760000000000000000000000000000000000089
|
||||
:100770000000000000000000000000000000000079
|
||||
:100780000000000000000000000000000000000069
|
||||
:100790000000000000000000000000000000000059
|
||||
:1007A0000000000000000000000000000000000049
|
||||
:1007B0000000000000000000000000000000000039
|
||||
:1007C0000000000000000000000000000000000029
|
||||
:1007D0000000000000000000000000000000000019
|
||||
:1007E0000000000000000000000000000000000009
|
||||
:1007F00000000000000000000000000000000000F9
|
||||
:00000001FF
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,18 @@
|
|||
{signal: [
|
||||
['Apple',
|
||||
{name: '7M', wave: 'n........', period: 2 },
|
||||
{name: 'Phi0', wave: 'hl......h......l..', node: '.a......b......c'},
|
||||
{name: 'Q3', wave: 'lh...l..h...l..h..'},
|
||||
{name: 'ADD', wave: '=.x=............x.', node: '...d............e', phase: 0.5},
|
||||
{name: '/DEV_SEL',wave: 'h.......0......1..'},
|
||||
{},
|
||||
{name: 'R/W', wave: 'x..=.........x....', phase: 0.5},
|
||||
{name: 'DATA', wave: 'x........=.......z', node: '.........f.......g', data: 'FromCPU', phase: 0.5},
|
||||
{name: 'DATA', wave: 'x..........=....z.', node: '...........h....i', data: 'ToCPU', phase: 0.5},
|
||||
],
|
||||
|
||||
],
|
||||
edge: [
|
||||
'a<->b 490 ns', 'a-|>d max 100ns', 'b-|>f max 30ns', 'c-|>e min 15ns', 'h|->c min 140ns', 'c-|>g min 30ns', 'c|->i min 10ns'
|
||||
]
|
||||
}
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 37 KiB |
|
|
@ -0,0 +1,21 @@
|
|||
{signal: [
|
||||
['E2 Read',
|
||||
{name: 'ADD', wave: 'x.=......x..', node: '..a......b'},
|
||||
{name: '/CE', wave: '1..0.....1..', node: '...c'},
|
||||
{name: '/OE', wave: '1...0....1..', node: '....d'},
|
||||
{name: 'DATA', wave: 'z......=...z', node: '.......e...f'},
|
||||
],
|
||||
{},
|
||||
['E2 Write',
|
||||
{name: 'ADD', wave: 'x.=..x........=', node: '..g..h'},
|
||||
{name: '/CE', wave: '1.0......1....0', node: '.........i'},
|
||||
{name: '/OE', wave: '0.1......0.....'},
|
||||
{name: '/WE', wave: '1..0....1.....0', node: '...j....k.....l'},
|
||||
{name: 'DATA', wave: 'z....=.....z...', node: '.....m.....n'},
|
||||
],
|
||||
],
|
||||
edge: [
|
||||
'a-|>e max 150ns', 'b-|>f max 50ns', 'c-|>e max 150ns', 'd|->e 10-70ns',
|
||||
'g-|>j min 10ns', 'k|->i min 0ns', 'j-|>h min 50ns', 'j->k min 100ns', 'k|->m min 50ns', 'k-|>n min 10ns'
|
||||
]
|
||||
}
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 37 KiB |
Binary file not shown.
Binary file not shown.
|
|
@ -11,9 +11,11 @@
|
|||
</ProjectConfiguration>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="..\README.md" />
|
||||
<None Include="AppleIISd.bin.map" />
|
||||
<None Include="makefile" />
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="obj\AppleIISd.lst" />
|
||||
<None Include="README.md" />
|
||||
<None Include="src\AppleIISd.cfg" />
|
||||
<None Include="src\AppleIISd.inc" />
|
||||
<None Include="src\AppleIISd.s" />
|
||||
|
|
@ -8,7 +8,6 @@
|
|||
<None Include="src\AppleIISd.s">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="README.md" />
|
||||
<None Include="obj\AppleIISd.lst" />
|
||||
<None Include="src\Helper.s">
|
||||
<Filter>src</Filter>
|
||||
|
|
@ -22,6 +21,9 @@
|
|||
<None Include="src\Smartport.s">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="..\README.md" />
|
||||
<None Include="AppleIISd.bin.map" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<Filter Include="src">
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
make clean
|
||||
make OPTIONS=mapfile,listing
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -d ..\Binary\Flasher.dsk appleiisd.bin
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -p ..\Binary\Flasher.dsk appleiisd.bin $00 < AppleIISd.bin
|
||||
copy AppleIISd.bin ..\Binary
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/bash
|
||||
|
||||
make clean
|
||||
make OPTIONS=mapfile,listing
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -d ../Binary/Flasher.dsk appleiisd.bin
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -p ../Binary/Flasher.dsk appleiisd.bin $00 < AppleIISd.bin
|
||||
cp AppleIISd.bin ../Binary/
|
||||
|
|
@ -1,10 +1,10 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2
|
||||
; Version 1.2.3
|
||||
; Defines
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2018
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
|
|
@ -44,11 +44,9 @@ DRVNUM := $0678
|
|||
CURSLOT := $07F8 ; $Cs
|
||||
|
||||
; Rom equates
|
||||
KNOWNRTS := $FF58
|
||||
OAPPLE := $C061 ; open apple key
|
||||
DATA := $C080
|
||||
CTRL := DATA+1
|
||||
DIV := DATA+2
|
||||
SS := DATA+3
|
||||
|
||||
; Constants
|
||||
|
|
@ -59,7 +57,7 @@ SS0 = $01 ; SS register
|
|||
SDHC = $10
|
||||
WP = $20
|
||||
CD = $40
|
||||
INITED = $80
|
||||
CARD_INIT = $80
|
||||
|
||||
SMDRIVERVER = $120B ; Version 1.2 Beta
|
||||
|
||||
|
|
@ -1,22 +1,25 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2
|
||||
; Version 1.2.3
|
||||
; Main source
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2018
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export INIT
|
||||
|
||||
.import PRODOS
|
||||
.import SMARTPORT
|
||||
.import GETR1
|
||||
.import GETR3
|
||||
.import SDCMD
|
||||
.import CARDDET
|
||||
.import INITED
|
||||
.import READ
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
|
|
@ -54,25 +57,23 @@
|
|||
LDX #$00
|
||||
LDX #$03
|
||||
LDX #$00 ; is Smartport controller
|
||||
;LDX #$3C ; is a disk controller
|
||||
|
||||
SEI ; find slot
|
||||
LDA #$60 ; opcode for RTS
|
||||
STA SLOT
|
||||
JSR SLOT
|
||||
BIT $CFFF
|
||||
JSR KNOWNRTS
|
||||
TSX
|
||||
LDA $0100,X
|
||||
CLI
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
TAY ; Y holds now SLOT
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
STA SLOT16 ; $s0
|
||||
TAX ; X holds now SLOT16
|
||||
BIT $CFFF
|
||||
|
||||
LDY #0 ; display copyright message
|
||||
@DRAW: LDA TEXT,Y
|
||||
|
|
@ -85,7 +86,7 @@
|
|||
LDA #197
|
||||
JSR $FCA8 ; wait for 100 ms
|
||||
|
||||
@OAPPLE: BIT OAPPLE ; check for OA key
|
||||
@OAPPLE: LDA OAPPLE ; check for OA key
|
||||
BPL @INIT ; and skip boot if pressed
|
||||
|
||||
@NEXTSLOT: LDA CURSLOT ; skip boot when no card
|
||||
|
|
@ -95,7 +96,6 @@
|
|||
JMP (CMDLO)
|
||||
|
||||
@INIT: JSR INIT
|
||||
CMP #NO_ERR
|
||||
BNE @NEXTSLOT ; init not successful
|
||||
|
||||
;*******************************
|
||||
|
|
@ -110,6 +110,8 @@
|
|||
STZ BUFFER ; buffer lo
|
||||
STZ BLOCKNUM+1 ; block hi
|
||||
STZ BLOCKNUM ; block lo
|
||||
LDA SLOT16
|
||||
STA DSNUMBER ; set to current slot
|
||||
JSR READ
|
||||
BCS @NEXTSLOT ; load not successful
|
||||
|
||||
|
|
@ -145,9 +147,8 @@ DRIVER: CLC ; ProDOS entry
|
|||
|
||||
; Has this to be done every time this gets called or only on boot???
|
||||
SEI
|
||||
LDA #$60 ; opcode for RTS
|
||||
STA SLOT
|
||||
JSR SLOT
|
||||
BIT $CFFF
|
||||
JSR KNOWNRTS
|
||||
TSX
|
||||
LDA $0100,X
|
||||
CLI
|
||||
|
|
@ -161,16 +162,9 @@ DRIVER: CLC ; ProDOS entry
|
|||
ASL A
|
||||
STA SLOT16 ; $s0
|
||||
TAX ; X holds now SLOT16
|
||||
BIT $CFFF
|
||||
|
||||
JSR CARDDET
|
||||
BCC @INITED
|
||||
LDA #ERR_OFFLINE; no card inserted
|
||||
BRA @END
|
||||
|
||||
@INITED: LDA #INITED ; check for init
|
||||
BIT SS,X
|
||||
BNE @DISP
|
||||
JSR INITED ; check for init
|
||||
BCC @DISP
|
||||
JSR INIT
|
||||
BCS @END ; Init failed
|
||||
|
||||
|
|
@ -228,18 +222,14 @@ DRIVER: CLC ; ProDOS entry
|
|||
;*******************************
|
||||
|
||||
.segment "EXTROM"
|
||||
INIT: LDA #$03 ; set SPI mode 3
|
||||
STA CTRL,X
|
||||
LDA SS,X
|
||||
ORA #SS0 ; set CS high
|
||||
INIT: STZ CTRL,X ; reset SPI controller
|
||||
LDA #SS0 ; set CS high
|
||||
STA SS,X
|
||||
LDA #7 ; set 400 kHz
|
||||
STA DIV,X
|
||||
LDY #10
|
||||
LDA #DUMMY
|
||||
|
||||
@LOOP: STA DATA,X
|
||||
@WAIT: BIT CTRL,X
|
||||
@LOOP: LDA #DUMMY
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X ; wait for TC (bit 7) to get high
|
||||
BPL @WAIT
|
||||
DEY
|
||||
BNE @LOOP ; do 10 times
|
||||
|
|
@ -348,7 +338,7 @@ INIT: LDA #$03 ; set SPI mode 3
|
|||
BNE @IOERROR ; error!
|
||||
|
||||
@END: LDA SS,X
|
||||
ORA #INITED ; initialized
|
||||
ORA #CARD_INIT ; initialized
|
||||
STA SS,X
|
||||
LDA CTRL,X
|
||||
ORA #ECE ; enable 7MHz
|
||||
|
|
@ -362,13 +352,13 @@ INIT: LDA #$03 ; set SPI mode 3
|
|||
@END1: LDA SS,X ; set CS high
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
LDA #0 ; set div to 2
|
||||
STA DIV,X
|
||||
TYA ; retval in A
|
||||
RTS
|
||||
KNOWNRTS: RTS
|
||||
|
||||
|
||||
TEXT: .asciiz " Apple][Sd v1.2 (c)2018 Florian Reitz"
|
||||
TEXT: .asciiz " Apple][Sd v1.2.2 (c)2021 Florian Reitz"
|
||||
.assert(*-TEXT)=40, error, "TEXT must be 40 bytes long"
|
||||
|
||||
|
||||
CMD0: .byt $40, $00, $00
|
||||
.byt $00, $00, $95
|
||||
|
|
@ -1,23 +1,25 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2
|
||||
; Version 1.2.3
|
||||
; Helper functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2018
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export COMMAND
|
||||
.export SDCMD
|
||||
.export GETBLOCK
|
||||
.export CARDDET
|
||||
.export WRPROT
|
||||
.export GETR1
|
||||
.export GETR3
|
||||
.export GETBLOCK
|
||||
.export COMMAND
|
||||
.export CARDDET
|
||||
.export WRPROT
|
||||
.export INITED
|
||||
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
.segment "EXTROM"
|
||||
|
|
@ -34,7 +36,7 @@ SDCMD: PHY
|
|||
LDY #0
|
||||
@LOOP: LDA (CMDLO),Y
|
||||
STA DATA,X
|
||||
@WAIT: BIT CTRL,X ; TC is in N
|
||||
@WAIT: LDA CTRL,X ; TC is in N
|
||||
BPL @WAIT
|
||||
INY
|
||||
CPY #6
|
||||
|
|
@ -52,7 +54,7 @@ SDCMD: PHY
|
|||
|
||||
GETR1: LDA #DUMMY
|
||||
STA DATA,X
|
||||
@WAIT: BIT CTRL,X
|
||||
@WAIT: LDA CTRL,X
|
||||
BPL @WAIT
|
||||
LDA DATA,X ; get response
|
||||
BMI GETR1 ; wait for MSB=0
|
||||
|
|
@ -77,7 +79,7 @@ GETR3: JSR GETR1 ; get R1 first
|
|||
JMP @WAIT ; first byte is already there
|
||||
@LOOP: LDA #DUMMY ; send dummy
|
||||
STA DATA,X
|
||||
@WAIT: BIT CTRL,X
|
||||
@WAIT: LDA CTRL,X
|
||||
BPL @WAIT
|
||||
LDA DATA,X
|
||||
PHA
|
||||
|
|
@ -126,7 +128,7 @@ GETBLOCK: PHX ; save X
|
|||
LDA #2 ; it is a phantom slot
|
||||
STA R31,X
|
||||
|
||||
@DRIVE: BIT DSNUMBER ; drive number
|
||||
@DRIVE: LDA DSNUMBER ; drive number
|
||||
BPL @SDHC ; D1
|
||||
LDA R31,X ; D2
|
||||
INC A
|
||||
|
|
@ -212,3 +214,23 @@ WRPROT: PHA
|
|||
SEC
|
||||
@DONE: PLA
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Check if card is initialized
|
||||
; X must contain SLOT16
|
||||
;
|
||||
; C Clear - card initialized
|
||||
; Set - card not initialized
|
||||
;
|
||||
;*******************************
|
||||
|
||||
INITED: PHA
|
||||
LDA #CARD_INIT ; 0: card not initialized
|
||||
BIT SS,X ; 1: card initialized
|
||||
CLC
|
||||
BNE @DONE
|
||||
SEC
|
||||
@DONE: PLA
|
||||
RTS
|
||||
|
|
@ -1,10 +1,10 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2
|
||||
; Version 1.2.3
|
||||
; ProDOS functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2018
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
|
|
@ -19,6 +19,9 @@
|
|||
.import COMMAND
|
||||
.import SDCMD
|
||||
.import GETBLOCK
|
||||
.import CARDDET
|
||||
.import INITED
|
||||
.import INIT
|
||||
.import WRPROT
|
||||
.import GETR1
|
||||
.import GETR3
|
||||
|
|
@ -67,6 +70,7 @@ PRODOS: LDA DCMD ; get command
|
|||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $28 - No card inserted
|
||||
; $2B - Card write protected
|
||||
; X - Blocks avail (low byte)
|
||||
; Y - Blocks avail (high byte)
|
||||
|
|
@ -74,7 +78,12 @@ PRODOS: LDA DCMD ; get command
|
|||
;*******************************
|
||||
|
||||
STATUS: LDA #NO_ERR ; Thanks for this one, Antoine!
|
||||
JSR WRPROT
|
||||
JSR CARDDET
|
||||
BCC @WRPROT
|
||||
LDA #ERR_NODRIVE; no card inserted
|
||||
BNE @DONE
|
||||
|
||||
@WRPROT: JSR WRPROT
|
||||
BCC @DONE
|
||||
LDA #ERR_NOWRITE; card write protected
|
||||
|
||||
|
|
@ -94,10 +103,20 @@ STATUS: LDA #NO_ERR ; Thanks for this one, Antoine!
|
|||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $27 - Bad block number
|
||||
; $28 - No card inserted
|
||||
;
|
||||
;*******************************
|
||||
|
||||
READ: JSR GETBLOCK ; calc block address
|
||||
READ: JSR CARDDET ; check for card
|
||||
BCS @NDERROR ; no card
|
||||
|
||||
JSR INITED ; check for initialization
|
||||
BCC @GETBLOCK
|
||||
|
||||
JSR INIT ; initialize card
|
||||
BCS @NDERROR ; init failed
|
||||
|
||||
@GETBLOCK: JSR GETBLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #<~SS0
|
||||
|
|
@ -105,7 +124,7 @@ READ: JSR GETBLOCK ; calc block address
|
|||
LDA #$51 ; send CMD17
|
||||
JSR COMMAND ; send command
|
||||
CMP #0
|
||||
BNE @ERROR ; check for error
|
||||
BNE @IOERROR ; check for error
|
||||
|
||||
@GETTOK: LDA #DUMMY ; get data token
|
||||
STA DATA,X
|
||||
|
|
@ -150,10 +169,14 @@ READ: JSR GETBLOCK ; calc block address
|
|||
PLP
|
||||
RTS
|
||||
|
||||
@ERROR: SEC ; an error occured
|
||||
@IOERROR: SEC ; an error occured
|
||||
LDA #ERR_IOERR
|
||||
BRA @DONE
|
||||
|
||||
@NDERROR: SEC ; an error occured
|
||||
LDA #ERR_NODRIVE
|
||||
BRA @DONE
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
|
|
@ -210,7 +233,7 @@ WRITE: JSR WRPROT
|
|||
CMP #$05
|
||||
BNE @IOERROR ; check for write error
|
||||
CLC ; no error
|
||||
LDA NO_ERR
|
||||
LDA #NO_ERR
|
||||
|
||||
@DONE: PHP
|
||||
PHA
|
||||
|
|
@ -1,10 +1,10 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2
|
||||
; Version 1.2.3
|
||||
; Smartport functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2018
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
|
|
@ -95,8 +95,10 @@ SMARTPORT: LDY #SMZPSIZE-1 ; save zeropage area for Smarport
|
|||
BCC @RESTZP
|
||||
|
||||
TXA
|
||||
;warum feste anzahl an bytes f<>r return wert?
|
||||
LDY #2 ; highbyte of # bytes transferred
|
||||
LDX #0 ; low byte of # bytes transferred
|
||||
;warum wird mit #1 verglichen?
|
||||
CMP #1 ; C=1 if A != NO_ERR
|
||||
RTS
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,280 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.1">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="2" name="Route2" color="1" fill="3" visible="no" active="yes"/>
|
||||
<layer number="3" name="Route3" color="4" fill="3" visible="no" active="yes"/>
|
||||
<layer number="14" name="Route14" color="1" fill="6" visible="no" active="yes"/>
|
||||
<layer number="15" name="Route15" color="4" fill="6" visible="no" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="200" name="200bmp" color="1" fill="10" visible="no" active="no"/>
|
||||
<layer number="250" name="Descript" color="3" fill="1" visible="no" active="no"/>
|
||||
<layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/>
|
||||
</layers>
|
||||
<library>
|
||||
<packages>
|
||||
<package name="TC2050-IDC">
|
||||
<smd name="2" x="-2.54" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="1" x="-2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="4" x="-1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="3" x="-1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="6" x="0" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="5" x="0" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="7" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="8" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="10" x="2.54" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="9" x="2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<rectangle x1="-2.54" y1="-0.635" x2="2.54" y2="0.635" layer="41"/>
|
||||
<hole x="-3.81" y="0" drill="0.9906"/>
|
||||
<hole x="3.81" y="1.016" drill="0.9906"/>
|
||||
<hole x="3.81" y="-1.016" drill="0.9906"/>
|
||||
<hole x="-3.81" y="2.54" drill="2.3749"/>
|
||||
<hole x="-3.81" y="-2.54" drill="2.3749"/>
|
||||
<hole x="1.905" y="2.54" drill="2.3749"/>
|
||||
<hole x="1.905" y="-2.54" drill="2.3749"/>
|
||||
<rectangle x1="-4.5847" y1="-5.14985" x2="-3.0353" y2="-2.54" layer="40"/>
|
||||
<rectangle x1="1.1303" y1="-5.14985" x2="2.6797" y2="-2.54" layer="40"/>
|
||||
<rectangle x1="-4.5847" y1="2.54" x2="-3.0353" y2="5.14985" layer="40"/>
|
||||
<rectangle x1="1.1303" y1="2.54" x2="2.6797" y2="5.14985" layer="40"/>
|
||||
<text x="-5.715" y="-2.54" size="1.27" layer="27" rot="R90">>VALUE</text>
|
||||
<text x="6.35" y="-2.54" size="1.27" layer="25" rot="R90">>NAME</text>
|
||||
</package>
|
||||
<package name="TC2050-IDC-NL">
|
||||
<smd name="2" x="-2.54" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="1" x="-2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="4" x="-1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="3" x="-1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="6" x="0" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="5" x="0" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="7" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="8" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="10" x="2.54" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="9" x="2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<rectangle x1="-2.54" y1="-0.635" x2="2.54" y2="0.635" layer="41"/>
|
||||
<hole x="-3.81" y="0" drill="0.9906"/>
|
||||
<hole x="3.81" y="1.016" drill="0.9906"/>
|
||||
<hole x="3.81" y="-1.016" drill="0.9906"/>
|
||||
<text x="-4.445" y="-3.175" size="1.27" layer="27">>VALUE</text>
|
||||
<text x="-4.445" y="1.905" size="1.27" layer="25">>NAME</text>
|
||||
</package>
|
||||
<package name="TC2030-IDC">
|
||||
<smd name="2" x="-1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="1" x="-1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="4" x="0" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="3" x="0" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="6" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="5" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<rectangle x1="-1.27" y1="-0.635" x2="1.27" y2="0.635" layer="41"/>
|
||||
<hole x="-2.54" y="0" drill="0.9906"/>
|
||||
<hole x="2.54" y="1.016" drill="0.9906"/>
|
||||
<hole x="2.54" y="-1.016" drill="0.9906"/>
|
||||
<hole x="-2.54" y="2.54" drill="2.3749"/>
|
||||
<hole x="-2.54" y="-2.54" drill="2.3749"/>
|
||||
<hole x="0.635" y="2.54" drill="2.3749"/>
|
||||
<hole x="0.635" y="-2.54" drill="2.3749"/>
|
||||
<rectangle x1="-3.3147" y1="-5.14985" x2="-1.7653" y2="-2.54" layer="40"/>
|
||||
<rectangle x1="-0.1397" y1="-5.14985" x2="1.4097" y2="-2.54" layer="40"/>
|
||||
<rectangle x1="-3.3147" y1="2.54" x2="-1.7653" y2="5.14985" layer="40"/>
|
||||
<rectangle x1="-0.1397" y1="2.54" x2="1.4097" y2="5.14985" layer="40"/>
|
||||
<text x="-4.445" y="-2.54" size="1.27" layer="27" rot="R90">>VALUE</text>
|
||||
<text x="5.08" y="-2.54" size="1.27" layer="25" rot="R90">>NAME</text>
|
||||
</package>
|
||||
<package name="TC2030-IDC-NL">
|
||||
<smd name="2" x="-1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="1" x="-1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="4" x="0" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="3" x="0" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="6" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<smd name="5" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/>
|
||||
<rectangle x1="-1.27" y1="-0.635" x2="1.27" y2="0.635" layer="41"/>
|
||||
<hole x="-2.54" y="0" drill="0.9906"/>
|
||||
<hole x="2.54" y="1.016" drill="0.9906"/>
|
||||
<hole x="2.54" y="-1.016" drill="0.9906"/>
|
||||
<text x="-3.175" y="1.905" size="1.27" layer="27">>VALUE</text>
|
||||
<text x="-3.175" y="-3.175" size="1.27" layer="25">>NAME</text>
|
||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="TC2030-IDC">
|
||||
<wire x1="3.81" y1="-5.08" x2="-3.81" y2="-5.08" width="0.4064" layer="94"/>
|
||||
<wire x1="-3.81" y1="5.08" x2="-3.81" y2="-5.08" width="0.4064" layer="94"/>
|
||||
<wire x1="3.81" y1="-5.08" x2="3.81" y2="5.08" width="0.4064" layer="94"/>
|
||||
<wire x1="-3.81" y1="5.08" x2="3.81" y2="5.08" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="2.54" x2="2.54" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-2.54" x2="2.54" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="2.54" x2="-1.27" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="0" x2="-1.27" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="-2.54" x2="-1.27" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<text x="-3.81" y="-7.62" size="1.778" layer="96">>VALUE</text>
|
||||
<text x="-3.81" y="5.842" size="1.778" layer="95">>NAME</text>
|
||||
<pin name="1" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="3" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="5" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="2" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="4" x="-7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="6" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
</symbol>
|
||||
<symbol name="TC2050-IDC">
|
||||
<wire x1="3.81" y1="-7.62" x2="-3.81" y2="-7.62" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-2.54" x2="2.54" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="-5.08" x2="2.54" y2="-5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="0" x2="-1.27" y2="0" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="-2.54" x2="-1.27" y2="-2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="-5.08" x2="-1.27" y2="-5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="-3.81" y1="7.62" x2="-3.81" y2="-7.62" width="0.4064" layer="94"/>
|
||||
<wire x1="3.81" y1="-7.62" x2="3.81" y2="7.62" width="0.4064" layer="94"/>
|
||||
<wire x1="-3.81" y1="7.62" x2="3.81" y2="7.62" width="0.4064" layer="94"/>
|
||||
<wire x1="1.27" y1="5.08" x2="2.54" y2="5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="1.27" y1="2.54" x2="2.54" y2="2.54" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="5.08" x2="-1.27" y2="5.08" width="0.6096" layer="94"/>
|
||||
<wire x1="-2.54" y1="2.54" x2="-1.27" y2="2.54" width="0.6096" layer="94"/>
|
||||
<text x="-3.81" y="-10.16" size="1.778" layer="96">>VALUE</text>
|
||||
<text x="-3.81" y="8.382" size="1.778" layer="95">>NAME</text>
|
||||
<pin name="1" x="7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="3" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="5" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="2" x="-7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="4" x="-7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="6" x="-7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="7" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="9" x="7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
|
||||
<pin name="8" x="-7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
<pin name="10" x="-7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="TC2050-IDC" prefix="TC">
|
||||
<description>Tag-Connect In Circuit Programming & Debug Cable 10 Pin
|
||||
http://www.tag-connect.com</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="TC2050-IDC" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="TC2050-IDC">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="-NL" package="TC2050-IDC-NL">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="TC2030-IDC" prefix="TC">
|
||||
<description>Tag-Connect In Circuit Programming & Debug Cable 6 Pin
|
||||
http://www.tag-connect.com</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="TC2030-IDC" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="TC2030-IDC">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="-NL" package="TC2030-IDC-NL">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="8.2.2">
|
||||
<eagle version="7.2.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<grid distance="25" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
|
|
@ -161,56 +161,56 @@ Dimensions taken from Tech Note #28</description>
|
|||
<wire x1="-25.4" y1="2.54" x2="-25.4" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-105.41" y1="-3.81" x2="-16.51" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-0.127" y2="7.778" width="0.2032" layer="49"/>
|
||||
<smd name="26" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="26" x="-12.065" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<text x="-5.715" y="3.175" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-94.5134" y="2.9718" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
|
||||
|
|
@ -478,7 +478,7 @@ Dimensions taken from Tech Note #28</description>
|
|||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="A2-50PIN" prefix="ST" uservalue="yes">
|
||||
<deviceset name="A2-50PIN">
|
||||
<description><B>Apple ][ Peripheral Card Connector</B>
|
||||
<br />
|
||||
This is the, default, 50-pin connector for slot #1 to #7
|
||||
|
|
@ -494,23 +494,23 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
|
||||
<gate name="_D6" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
|
||||
<gate name="_D7" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
|
||||
<gate name="_DEVSELECT\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_00" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_!DEVSELECT" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_PHI0" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_USER1" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
|
||||
<gate name="_01" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_PHI1" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_Q3" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
|
||||
<gate name="_7M" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
|
||||
<gate name="_NC@2" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
|
||||
<gate name="_-5V" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
|
||||
<gate name="_-12V" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
|
||||
<gate name="_INH\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_RES\" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_IRQ\" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_NMI\" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_!INH" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_!RES" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_!IRQ" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_!NMI" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_IN" symbol="ATPIN" x="-5.08" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_IN" symbol="ATPIN" x="-5.08" y="20.32" addlevel="always"/>
|
||||
<gate name="_GND" symbol="ATPIN" x="-5.08" y="22.86" addlevel="always"/>
|
||||
<gate name="_IOSELECT\" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_!IOSELECT" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_A00" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
|
||||
<gate name="_A01" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
|
||||
<gate name="_A02" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
|
||||
|
|
@ -527,11 +527,11 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<gate name="_A13" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
|
||||
<gate name="_A14" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
|
||||
<gate name="_A15" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
|
||||
<gate name="_RW" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_R!W" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_NC@1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
|
||||
<gate name="_IOSTR\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_!IOSTR" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_RDY" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
|
||||
<gate name="_DMA\" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
<gate name="_!DMA" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_OUT" symbol="ATPIN" x="27.94" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_OUT" symbol="ATPIN" x="27.94" y="20.32" addlevel="always"/>
|
||||
<gate name="_+5V" symbol="ATPIN" x="27.94" y="22.86" addlevel="always"/>
|
||||
|
|
@ -539,12 +539,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<devices>
|
||||
<device name="SLOT1-3" package="A2-50PIN-SL1-3">
|
||||
<connects>
|
||||
<connect gate="_!DEVSELECT" pin="P" pad="41"/>
|
||||
<connect gate="_!DMA" pin="P" pad="22"/>
|
||||
<connect gate="_!INH" pin="P" pad="32"/>
|
||||
<connect gate="_!IOSELECT" pin="P" pad="01"/>
|
||||
<connect gate="_!IOSTR" pin="P" pad="20"/>
|
||||
<connect gate="_!IRQ" pin="P" pad="30"/>
|
||||
<connect gate="_!NMI" pin="P" pad="29"/>
|
||||
<connect gate="_!RES" pin="P" pad="31"/>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
|
|
@ -570,24 +576,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_PHI0" pin="P" pad="40"/>
|
||||
<connect gate="_PHI1" pin="P" pad="38"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_R!W" pin="P" pad="18"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
|
|
@ -596,12 +596,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
</device>
|
||||
<device name="SLOT4-7" package="A2-50PIN-SL4-7">
|
||||
<connects>
|
||||
<connect gate="_!DEVSELECT" pin="P" pad="41"/>
|
||||
<connect gate="_!DMA" pin="P" pad="22"/>
|
||||
<connect gate="_!INH" pin="P" pad="32"/>
|
||||
<connect gate="_!IOSELECT" pin="P" pad="01"/>
|
||||
<connect gate="_!IOSTR" pin="P" pad="20"/>
|
||||
<connect gate="_!IRQ" pin="P" pad="30"/>
|
||||
<connect gate="_!NMI" pin="P" pad="29"/>
|
||||
<connect gate="_!RES" pin="P" pad="31"/>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
|
|
@ -627,24 +633,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_PHI0" pin="P" pad="40"/>
|
||||
<connect gate="_PHI1" pin="P" pad="38"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_R!W" pin="P" pad="18"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -0,0 +1,688 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="8.2.2">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="50" name="dxf" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="53" name="tGND_GNDA" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="54" name="bGND_GNDA" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="56" name="wert" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<pad name="38" x="6.35" y="3.81" drill="0.8128" shape="octagon"/>
|
||||
<pad name="39" x="8.89" y="6.35" drill="0.8128" shape="octagon"/>
|
||||
<pad name="40" x="6.35" y="8.89" drill="0.8128" shape="octagon"/>
|
||||
<pad name="41" x="6.35" y="6.35" drill="0.8128" shape="octagon"/>
|
||||
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|
||||
<pad name="43" x="3.81" y="6.35" drill="0.8128" shape="octagon"/>
|
||||
<pad name="44" x="1.27" y="8.89" drill="0.8128" shape="octagon"/>
|
||||
<text x="-2.54" y="11.938" size="1.27" layer="27" ratio="10">>VALUE</text>
|
||||
<text x="-10.16" y="11.938" size="1.27" layer="25" ratio="10">>NAME</text>
|
||||
<text x="8.255" y="-10.795" size="1.27" layer="21" ratio="10">44</text>
|
||||
</package>
|
||||
<package name="SQFP-S-10X10-44">
|
||||
<description><b>QFP44</b><p>
|
||||
shrink quad flat pack, square</description>
|
||||
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||||
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||||
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|
||||
<wire x1="7.4" y1="-7.4" x2="-7.4" y2="-7.4" width="0.1998" layer="39"/>
|
||||
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|
||||
<wire x1="4.91" y1="-4.91" x2="4.91" y2="4.91" width="0.2032" layer="51"/>
|
||||
<wire x1="4.91" y1="4.91" x2="-4.91" y2="4.91" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.91" y1="4.91" x2="-4.91" y2="-4.91" width="0.2032" layer="51"/>
|
||||
<wire x1="-4.72" y1="4.71" x2="4.71" y2="4.71" width="0.2032" layer="21"/>
|
||||
<wire x1="4.71" y1="4.71" x2="4.71" y2="-4.71" width="0.2032" layer="21"/>
|
||||
<wire x1="4.71" y1="-4.71" x2="-4.72" y2="-4.71" width="0.2032" layer="21"/>
|
||||
<wire x1="-4.72" y1="-4.71" x2="-4.72" y2="4.71" width="0.2032" layer="21"/>
|
||||
<circle x="-3.7501" y="-3.7501" radius="0.5002" width="0.254" layer="21"/>
|
||||
<smd name="1" x="-4" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="2" x="-3.2" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="3" x="-2.4" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="4" x="-1.6" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="5" x="-0.8" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="6" x="0" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="7" x="0.8" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="8" x="1.6" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="9" x="2.4" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="10" x="3.2" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="11" x="4" y="-6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="12" x="6" y="-4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="13" x="6" y="-3.2" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="14" x="6" y="-2.4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="15" x="6" y="-1.6" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="16" x="6" y="-0.8" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="17" x="6" y="0" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="18" x="6" y="0.8" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="19" x="6" y="1.6" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="20" x="6" y="2.4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="21" x="6" y="3.2" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="22" x="6" y="4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="23" x="4" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="24" x="3.2" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="25" x="2.4" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="26" x="1.6" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="27" x="0.8" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="28" x="0" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="29" x="-0.8" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="30" x="-1.6" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="31" x="-2.4" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="32" x="-3.2" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="33" x="-4" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
<smd name="34" x="-6" y="4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="35" x="-6" y="3.2" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="36" x="-6" y="2.4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="37" x="-6" y="1.6" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="38" x="-6" y="0.8" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="39" x="-6" y="0" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="40" x="-6" y="-0.8" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="41" x="-6" y="-1.6" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="42" x="-6" y="-2.4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="43" x="-6" y="-3.2" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="44" x="-6" y="-4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<text x="-3.81" y="-2.175" size="1.27" layer="25">>NAME</text>
|
||||
<text x="-3.81" y="1.905" size="1.27" layer="27">>VALUE</text>
|
||||
<rectangle x1="-4.22" y1="-6.7201" x2="-3.78" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="-3.4201" y1="-6.7201" x2="-2.9799" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="-2.62" y1="-6.7201" x2="-2.1801" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="-1.8199" y1="-6.7201" x2="-1.38" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="-1.0201" y1="-6.7201" x2="-0.5799" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="-0.22" y1="-6.7201" x2="0.22" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="0.5799" y1="-6.7201" x2="1.0201" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="1.38" y1="-6.7201" x2="1.8199" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="2.1801" y1="-6.7201" x2="2.62" y2="-4.95" layer="51"/>
|
||||
<rectangle x1="2.9799" y1="-6.7201" x2="3.4201" y2="-4.95" layer="51"/>
|
||||
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|
||||
<rectangle x1="4.95" y1="-4.22" x2="6.7201" y2="-3.78" layer="51"/>
|
||||
<rectangle x1="4.95" y1="-3.4201" x2="6.7201" y2="-2.9799" layer="51"/>
|
||||
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|
||||
<rectangle x1="4.95" y1="-1.8199" x2="6.7201" y2="-1.38" layer="51"/>
|
||||
<rectangle x1="4.95" y1="-1.0201" x2="6.7201" y2="-0.5799" layer="51"/>
|
||||
<rectangle x1="4.95" y1="-0.22" x2="6.7201" y2="0.22" layer="51"/>
|
||||
<rectangle x1="4.95" y1="0.5799" x2="6.7201" y2="1.0201" layer="51"/>
|
||||
<rectangle x1="4.95" y1="1.38" x2="6.7201" y2="1.8199" layer="51"/>
|
||||
<rectangle x1="4.95" y1="2.1801" x2="6.7201" y2="2.62" layer="51"/>
|
||||
<rectangle x1="4.95" y1="2.9799" x2="6.7201" y2="3.4201" layer="51"/>
|
||||
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|
||||
<rectangle x1="3.78" y1="4.95" x2="4.22" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="2.9799" y1="4.95" x2="3.4201" y2="6.7201" layer="51"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<rectangle x1="-3.4201" y1="4.95" x2="-2.9799" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-4.22" y1="4.95" x2="-3.78" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="3.78" x2="-4.95" y2="4.22" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="2.9799" x2="-4.95" y2="3.4201" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="2.1801" x2="-4.95" y2="2.62" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="1.38" x2="-4.95" y2="1.8199" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="0.5799" x2="-4.95" y2="1.0201" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-0.22" x2="-4.95" y2="0.22" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-1.0201" x2="-4.95" y2="-0.5799" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-1.8199" x2="-4.95" y2="-1.38" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-2.62" x2="-4.95" y2="-2.1801" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-3.4201" x2="-4.95" y2="-2.9799" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-4.22" x2="-4.95" y2="-3.78" layer="51"/>
|
||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="SUPPLY">
|
||||
<pin name="GND@0" x="-5.08" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
<pin name="GND@1" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
<pin name="GND@2" x="5.08" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
<pin name="VCCINT@0" x="-5.08" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
|
||||
<pin name="VCCINT@1" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
|
||||
<pin name="VCCIO" x="5.08" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
|
||||
<text x="-0.635" y="-0.635" size="1.778" layer="95">>NAME</text>
|
||||
<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
|
||||
<text x="1.905" y="2.54" size="1.27" layer="95" rot="R90">VCCINT</text>
|
||||
<text x="-3.175" y="2.54" size="1.27" layer="95" rot="R90">VCCINT</text>
|
||||
<text x="6.985" y="2.54" size="1.27" layer="95" rot="R90">VCCIO</text>
|
||||
<text x="-3.175" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
|
||||
<text x="6.985" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
|
||||
</symbol>
|
||||
<symbol name="XC9572_PC44">
|
||||
<wire x1="-25.4" y1="-25.4" x2="25.4" y2="-25.4" width="0.254" layer="94"/>
|
||||
<wire x1="25.4" y1="-25.4" x2="25.4" y2="25.4" width="0.254" layer="94"/>
|
||||
<wire x1="25.4" y1="25.4" x2="-25.4" y2="25.4" width="0.254" layer="94"/>
|
||||
<wire x1="-25.4" y1="25.4" x2="-25.4" y2="-25.4" width="0.254" layer="94"/>
|
||||
<pin name="FB01/02" x="-30.48" y="12.7" length="middle"/>
|
||||
<pin name="FB01/05" x="-30.48" y="10.16" length="middle"/>
|
||||
<pin name="FB01/06" x="-30.48" y="7.62" length="middle"/>
|
||||
<pin name="FB01/08" x="-30.48" y="5.08" length="middle"/>
|
||||
<pin name="FB01/09" x="-30.48" y="2.54" length="middle"/>
|
||||
<pin name="FB01/11" x="-30.48" y="0" length="middle"/>
|
||||
<pin name="FB01/14" x="-30.48" y="-2.54" length="middle"/>
|
||||
<pin name="FB01/15" x="-30.48" y="-5.08" length="middle"/>
|
||||
<pin name="FB01/17" x="-30.48" y="-7.62" length="middle"/>
|
||||
<pin name="FB02/02" x="10.16" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/05" x="7.62" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/06" x="5.08" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/08" x="2.54" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/09" x="0" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/11" x="-2.54" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/14" x="-5.08" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/15" x="-7.62" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/17" x="-10.16" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB03/02" x="-10.16" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/05" x="-7.62" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/08" x="-5.08" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/09" x="-2.54" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/11" x="0" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/14" x="2.54" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/15" x="5.08" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/16" x="7.62" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/17" x="10.16" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB04/02" x="30.48" y="-2.54" length="middle" rot="R180"/>
|
||||
<pin name="FB04/05" x="30.48" y="0" length="middle" rot="R180"/>
|
||||
<pin name="FB04/08" x="30.48" y="2.54" length="middle" rot="R180"/>
|
||||
<pin name="FB04/11" x="30.48" y="5.08" length="middle" rot="R180"/>
|
||||
<pin name="FB04/14" x="30.48" y="7.62" length="middle" rot="R180"/>
|
||||
<pin name="FB04/15" x="30.48" y="10.16" length="middle" rot="R180"/>
|
||||
<pin name="FB04/17" x="30.48" y="12.7" length="middle" rot="R180"/>
|
||||
<pin name="TCK" x="30.48" y="-10.16" length="middle" direction="in" rot="R180"/>
|
||||
<pin name="TDI" x="30.48" y="-15.24" length="middle" direction="in" rot="R180"/>
|
||||
<pin name="TDO" x="30.48" y="-12.7" length="middle" direction="out" rot="R180"/>
|
||||
<pin name="TMS" x="30.48" y="-17.78" length="middle" direction="in" rot="R180"/>
|
||||
<text x="-5.08" y="1.27" size="1.778" layer="95">>NAME</text>
|
||||
<text x="-5.08" y="-2.54" size="1.778" layer="96">>VALUE</text>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="XC9572_S44">
|
||||
<gates>
|
||||
<gate name="G$1" symbol="XC9572_PC44" x="0" y="0"/>
|
||||
<gate name="SUPPLY" symbol="SUPPLY" x="58.42" y="-2.54" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="PLCC" package="S44">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="FB01/02" pad="1"/>
|
||||
<connect gate="G$1" pin="FB01/05" pad="2"/>
|
||||
<connect gate="G$1" pin="FB01/06" pad="3"/>
|
||||
<connect gate="G$1" pin="FB01/08" pad="4"/>
|
||||
<connect gate="G$1" pin="FB01/09" pad="5"/>
|
||||
<connect gate="G$1" pin="FB01/11" pad="6"/>
|
||||
<connect gate="G$1" pin="FB01/14" pad="7"/>
|
||||
<connect gate="G$1" pin="FB01/15" pad="8"/>
|
||||
<connect gate="G$1" pin="FB01/17" pad="9"/>
|
||||
<connect gate="G$1" pin="FB02/02" pad="35"/>
|
||||
<connect gate="G$1" pin="FB02/05" pad="36"/>
|
||||
<connect gate="G$1" pin="FB02/06" pad="37"/>
|
||||
<connect gate="G$1" pin="FB02/08" pad="38"/>
|
||||
<connect gate="G$1" pin="FB02/09" pad="39"/>
|
||||
<connect gate="G$1" pin="FB02/11" pad="40"/>
|
||||
<connect gate="G$1" pin="FB02/14" pad="42"/>
|
||||
<connect gate="G$1" pin="FB02/15" pad="43"/>
|
||||
<connect gate="G$1" pin="FB02/17" pad="44"/>
|
||||
<connect gate="G$1" pin="FB03/02" pad="11"/>
|
||||
<connect gate="G$1" pin="FB03/05" pad="12"/>
|
||||
<connect gate="G$1" pin="FB03/08" pad="13"/>
|
||||
<connect gate="G$1" pin="FB03/09" pad="14"/>
|
||||
<connect gate="G$1" pin="FB03/11" pad="18"/>
|
||||
<connect gate="G$1" pin="FB03/14" pad="19"/>
|
||||
<connect gate="G$1" pin="FB03/15" pad="20"/>
|
||||
<connect gate="G$1" pin="FB03/16" pad="24"/>
|
||||
<connect gate="G$1" pin="FB03/17" pad="22"/>
|
||||
<connect gate="G$1" pin="FB04/02" pad="25"/>
|
||||
<connect gate="G$1" pin="FB04/05" pad="26"/>
|
||||
<connect gate="G$1" pin="FB04/08" pad="27"/>
|
||||
<connect gate="G$1" pin="FB04/11" pad="28"/>
|
||||
<connect gate="G$1" pin="FB04/14" pad="29"/>
|
||||
<connect gate="G$1" pin="FB04/15" pad="33"/>
|
||||
<connect gate="G$1" pin="FB04/17" pad="34"/>
|
||||
<connect gate="G$1" pin="TCK" pad="17"/>
|
||||
<connect gate="G$1" pin="TDI" pad="15"/>
|
||||
<connect gate="G$1" pin="TDO" pad="30"/>
|
||||
<connect gate="G$1" pin="TMS" pad="16"/>
|
||||
<connect gate="SUPPLY" pin="GND@0" pad="10"/>
|
||||
<connect gate="SUPPLY" pin="GND@1" pad="23"/>
|
||||
<connect gate="SUPPLY" pin="GND@2" pad="31"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@0" pad="21"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@1" pad="41"/>
|
||||
<connect gate="SUPPLY" pin="VCCIO" pad="32"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="VQFP" package="SQFP-S-10X10-44">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="FB01/02" pad="39"/>
|
||||
<connect gate="G$1" pin="FB01/05" pad="40"/>
|
||||
<connect gate="G$1" pin="FB01/06" pad="41"/>
|
||||
<connect gate="G$1" pin="FB01/08" pad="42"/>
|
||||
<connect gate="G$1" pin="FB01/09" pad="43"/>
|
||||
<connect gate="G$1" pin="FB01/11" pad="44"/>
|
||||
<connect gate="G$1" pin="FB01/14" pad="1"/>
|
||||
<connect gate="G$1" pin="FB01/15" pad="2"/>
|
||||
<connect gate="G$1" pin="FB01/17" pad="3"/>
|
||||
<connect gate="G$1" pin="FB02/02" pad="29"/>
|
||||
<connect gate="G$1" pin="FB02/05" pad="30"/>
|
||||
<connect gate="G$1" pin="FB02/06" pad="31"/>
|
||||
<connect gate="G$1" pin="FB02/08" pad="32"/>
|
||||
<connect gate="G$1" pin="FB02/09" pad="33"/>
|
||||
<connect gate="G$1" pin="FB02/11" pad="34"/>
|
||||
<connect gate="G$1" pin="FB02/14" pad="36"/>
|
||||
<connect gate="G$1" pin="FB02/15" pad="37"/>
|
||||
<connect gate="G$1" pin="FB02/17" pad="38"/>
|
||||
<connect gate="G$1" pin="FB03/02" pad="5"/>
|
||||
<connect gate="G$1" pin="FB03/05" pad="6"/>
|
||||
<connect gate="G$1" pin="FB03/08" pad="7"/>
|
||||
<connect gate="G$1" pin="FB03/09" pad="8"/>
|
||||
<connect gate="G$1" pin="FB03/11" pad="12"/>
|
||||
<connect gate="G$1" pin="FB03/14" pad="13"/>
|
||||
<connect gate="G$1" pin="FB03/15" pad="14"/>
|
||||
<connect gate="G$1" pin="FB03/16" pad="18"/>
|
||||
<connect gate="G$1" pin="FB03/17" pad="16"/>
|
||||
<connect gate="G$1" pin="FB04/02" pad="19"/>
|
||||
<connect gate="G$1" pin="FB04/05" pad="20"/>
|
||||
<connect gate="G$1" pin="FB04/08" pad="21"/>
|
||||
<connect gate="G$1" pin="FB04/11" pad="22"/>
|
||||
<connect gate="G$1" pin="FB04/14" pad="23"/>
|
||||
<connect gate="G$1" pin="FB04/15" pad="27"/>
|
||||
<connect gate="G$1" pin="FB04/17" pad="28"/>
|
||||
<connect gate="G$1" pin="TCK" pad="11"/>
|
||||
<connect gate="G$1" pin="TDI" pad="9"/>
|
||||
<connect gate="G$1" pin="TDO" pad="24"/>
|
||||
<connect gate="G$1" pin="TMS" pad="10"/>
|
||||
<connect gate="SUPPLY" pin="GND@0" pad="4"/>
|
||||
<connect gate="SUPPLY" pin="GND@1" pad="17"/>
|
||||
<connect gate="SUPPLY" pin="GND@2" pad="25"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@0" pad="15"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@1" pad="35"/>
|
||||
<connect gate="SUPPLY" pin="VCCIO" pad="26"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 572 KiB |
BIN
ProFile.zip
BIN
ProFile.zip
Binary file not shown.
56
README.md
56
README.md
|
|
@ -5,12 +5,13 @@ The **AppleIISd** is a SD card based replaced for the ProFile harddrive. In cont
|
|||
|
||||
A Xilinx CPLD is used as a SPI controller and translates, together with the ROM driver, SD card data to/from the Apple IIe. The VHDL source is based on [SPI65/B](http://www.6502.org/users/andre/spi65b) by André Fachat.
|
||||
|
||||
The assembler sources are written for CC65. The [schematics](AppleIISd.pdf) are available as PDF.
|
||||
The assembler sources are written for CC65. The [schematics](Binary/AppleIISd.pdf) are available as PDF.
|
||||
|
||||
## Features
|
||||
* works with ProDOS and GS/OS
|
||||
* up to 128MB storage space (4x 65535 blocks)
|
||||
* ProDOS and Smartport driver in ROM
|
||||
* Firmware update from ProDOS
|
||||
* Auto boot
|
||||
* Access LED
|
||||
* Card detect and write protect sensing
|
||||
|
|
@ -25,7 +26,19 @@ The AppleIISd requires an enhanced IIe or IIgs computer. The ROM code uses some
|
|||
* Apple IIe enhanced, 128k, Prodos 1.9
|
||||
* Apple IIe enhanced, 64k, Prodos 1.9
|
||||
|
||||
When a 2732 type ROM is used, the binary image has to be programmed at offset 0x800, because A11 is always high for compatibility with 2716 type ROMs.
|
||||
## Binary distribution
|
||||
The following files in [Binary/](Binary) have been provided to eliminate the need to compile assembler or VHDL sources.
|
||||
|
||||
| File | Purpose |
|
||||
| ---- | ------- |
|
||||
| AppleIISd_xx44.jed | CPLD bitfiles for PC44 and VQ44 formfactors |
|
||||
| AppleIISd.bin | 2k Firmware binary for EPROM |
|
||||
| AppleIISd.hex | Same as above in INTEL-HEX format |
|
||||
| AppleIISd.bom.txt | BOM for the board |
|
||||
| AppleIISd.pdf | Schematic and layout |
|
||||
| Flasher.bin | Flasher program ProDOS binary |
|
||||
| Flasher.dsk | Complete ProDOS disk image with Flasher.bin and AppleIISd.bin |
|
||||
| Gerber_Vx.x.zip | Gerber files for different hw revisions |
|
||||
|
||||
## Smartport drive remapping
|
||||
The AppleIISd features Smartport drivers in ROM to provide more than two drives in both GS/OS and ProDOS.
|
||||
|
|
@ -85,14 +98,47 @@ LDA $C0C0
|
|||
```
|
||||
|
||||
|
||||
## Registers
|
||||
The control registers of the *AppleIISd* are mapped to the usual I/O space at **$C0n0 - $C0n3**, where n is slot+8. All registers and bits are read/write, except where noted.
|
||||
|
||||
| Address | Function | Default value |
|
||||
| ------- | --------------- | ------------- |
|
||||
| $C0n0 | DATA | - |
|
||||
| $C0n1 | **0:** PGMEN<br>**1:** -<br>**2:** ECE<br>**3:** -<br>**4:** FRX<br>**5:** BSY (R)<br>**6:** -<br>**7:** TC (R) | 0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br> |
|
||||
| $C0n2 | unused | $00 |
|
||||
| $C0n3 | **0:** /SS<br>**1:** -<br>**2:** -<br>**3:** -<br>**4:** SDHC<br>**5:** WP (R)<br>**6:** CD (R)<br>**7:** INIT | 1<br>0<br>0<br>0<br>0<br>-<br>-<br>0 |
|
||||
|
||||
**DATA** SPI data register - Is used for both input and output. When the register is written to, the controller will output the byte on the SPI bus. When it is read from, it reflects the data that was received over the SPI bus.
|
||||
|
||||
**PGMEN** Program Enable - Enable programing of the internal firmware eeprom. Should be reset immediately after writing to the device.
|
||||
|
||||
**ECE** External Clock Enable - This bit enables the the external clock input to the SPI controller. In the *AppleIISd*, this effectively switches the SPI clock between 500kHz (ECE = 0) and 3.5MHz (ECE = 1).
|
||||
|
||||
**FRX** Fast Receive mode - When set to 1, fast receive mode triggers shifting upon reading or writing the SPI Data register. When set to 0, shifting is only triggered by writing the SPI data register.
|
||||
|
||||
**BSY** Busy - This bit is 1 as long as data is shifted out on the SPI bus. *BSY* is read-only.
|
||||
|
||||
**TC** Transfer Complete - This flag is set when the last bit has been shifted out onto the SPI bus and is cleared when *SPI data* is read.
|
||||
|
||||
**/SS** Slave select - Write 0 to this bit to select the SD card.
|
||||
|
||||
**SDHC** This bit is used by the initialization routine in firmware to signalize when a SDHC card was found. Do not write to manually.
|
||||
|
||||
**WP** Write Protect - This read-only bit is 0 when writing to the card is enabled by the switch on the card.
|
||||
|
||||
**CD** Card Detect - This read-only bit is 0 when a card is inserted.
|
||||
|
||||
**INIT** Initialized - This bit is set to 1 when the SD card has been initialized by the firmware. Do not write manually.
|
||||
|
||||
## TODOs
|
||||
* Much more testing
|
||||
* SRAM option (may never work, though)
|
||||
* Enable more than 4 volumes under GS/OS
|
||||
* Use 28 pin socket to support other EPROMS than 2716 and 2732
|
||||
* Support for 6502 CPUs
|
||||
* Support for CP/M
|
||||
|
||||
## Known Bugs
|
||||
* Does not work with some Z80 cards present
|
||||
* Programs not startable from partitions 3 and 4 under ProDOS
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,100 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project DefaultTargets="Build" ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup Label="ProjectConfigurations">
|
||||
<ProjectConfiguration Include="Debug|Win32">
|
||||
<Configuration>Debug</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
<ProjectConfiguration Include="Release|Win32">
|
||||
<Configuration>Release</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="Flasher.bin.map" />
|
||||
<None Include="makefile" />
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="obj\Flasher.lst" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="src\Flasher.c" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="src\AppleIISd.h" />
|
||||
</ItemGroup>
|
||||
<PropertyGroup Label="Globals">
|
||||
<ProjectGuid>{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}</ProjectGuid>
|
||||
<Keyword>MakeFileProj</Keyword>
|
||||
<ProjectName>Flasher</ProjectName>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
|
||||
<ConfigurationType>Makefile</ConfigurationType>
|
||||
<UseDebugLibraries>true</UseDebugLibraries>
|
||||
<PlatformToolset>v140</PlatformToolset>
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
|
||||
<ConfigurationType>Makefile</ConfigurationType>
|
||||
<UseDebugLibraries>false</UseDebugLibraries>
|
||||
<PlatformToolset>v140</PlatformToolset>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
|
||||
<ImportGroup Label="ExtensionSettings">
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<PropertyGroup Label="UserMacros" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<NMakeOutput>
|
||||
</NMakeOutput>
|
||||
<NMakePreprocessorDefinitions>__APPLE2__;__APPLE2ENH__;__fastcall__=__fastcall;_MSC_VER=0;__attribute__</NMakePreprocessorDefinitions>
|
||||
<ExecutablePath>$(PATH);C:\cc65\bin</ExecutablePath>
|
||||
<IncludePath>C:\cc65\include</IncludePath>
|
||||
<LibraryPath>C:\cc65\lib</LibraryPath>
|
||||
<LibraryWPath />
|
||||
<ExcludePath />
|
||||
<NMakeBuildCommandLine>$(MAKE_HOME)\make OPTIONS=mapfile,listing</NMakeBuildCommandLine>
|
||||
<SourcePath>$(ProjectDir)\src</SourcePath>
|
||||
<NMakeReBuildCommandLine>$(MAKE_HOME)\make clean
|
||||
$(MAKE_HOME)\make OPTIONS=mapfile,listing</NMakeReBuildCommandLine>
|
||||
<OutDir>$(SolutionDir)\</OutDir>
|
||||
<NMakeCleanCommandLine>$(MAKE_HOME)\make clean</NMakeCleanCommandLine>
|
||||
<ReferencePath />
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<NMakeOutput>
|
||||
</NMakeOutput>
|
||||
<NMakePreprocessorDefinitions>
|
||||
</NMakePreprocessorDefinitions>
|
||||
<NMakeBuildCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"</NMakeBuildCommandLine>
|
||||
<NMakeReBuildCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make clean -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
$(MAKE_HOME)\make -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"
|
||||
</NMakeReBuildCommandLine>
|
||||
<NMakeCleanCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make clean -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"</NMakeCleanCommandLine>
|
||||
<ExecutablePath>$(PATH);C:\cc65\bin</ExecutablePath>
|
||||
<IncludePath>$(VC_IncludePath);C:\cc65\include</IncludePath>
|
||||
<ReferencePath />
|
||||
<LibraryPath>C:\cc65\lib</LibraryPath>
|
||||
<ExcludePath />
|
||||
<LibraryWPath />
|
||||
<OutDir>$(SolutionDir)$\</OutDir>
|
||||
</PropertyGroup>
|
||||
<ItemDefinitionGroup>
|
||||
</ItemDefinitionGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
|
||||
<ImportGroup Label="ExtensionTargets">
|
||||
</ImportGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup>
|
||||
<None Include="makefile" />
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="Flasher.bin.map" />
|
||||
<None Include="obj\Flasher.lst" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="src\Flasher.c" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="src\AppleIISd.h" />
|
||||
</ItemGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
# Configuration for ProDOS 8 system programs (allowing for 3KB in LC)
|
||||
|
||||
SYMBOLS {
|
||||
__EXEHDR__: type = import;
|
||||
__FILETYPE__: type = weak, value = $00FF; # ProDOS file type
|
||||
__STACKSIZE__: type = weak, value = $0800; # 2k stack
|
||||
__LCADDR__: type = weak, value = $D400; # Behind quit code
|
||||
__LCSIZE__: type = weak, value = $0C00; # Rest of bank two
|
||||
}
|
||||
MEMORY {
|
||||
ZP: file = "", define = yes, start = $0080, size = $001A;
|
||||
HEADER: file = %O, start = $2000 - $003A, size = $003A;
|
||||
MAIN: file = %O, define = yes, start = $2000, size = $BF00 - $2000;
|
||||
BSS: file = "", start = __ONCE_RUN__, size = $BF00 - __STACKSIZE__ - __ONCE_RUN__;
|
||||
LC: file = "", define = yes, start = __LCADDR__, size = __LCSIZE__;
|
||||
}
|
||||
SEGMENTS {
|
||||
ZEROPAGE: load = ZP, type = zp;
|
||||
EXEHDR: load = HEADER, type = ro, optional = yes;
|
||||
STARTUP: load = MAIN, type = ro;
|
||||
LOWCODE: load = MAIN, type = ro, optional = yes;
|
||||
CODE: load = MAIN, type = ro;
|
||||
RODATA: load = MAIN, type = ro;
|
||||
DATA: load = MAIN, type = rw;
|
||||
INIT: load = MAIN, type = rw;
|
||||
ONCE: load = MAIN, type = ro, define = yes;
|
||||
LC: load = MAIN, run = LC, type = ro, optional = yes;
|
||||
BSS: load = BSS, type = bss, define = yes;
|
||||
}
|
||||
FEATURES {
|
||||
CONDES: type = constructor,
|
||||
label = __CONSTRUCTOR_TABLE__,
|
||||
count = __CONSTRUCTOR_COUNT__,
|
||||
segment = ONCE;
|
||||
CONDES: type = destructor,
|
||||
label = __DESTRUCTOR_TABLE__,
|
||||
count = __DESTRUCTOR_COUNT__,
|
||||
segment = RODATA;
|
||||
CONDES: type = interruptor,
|
||||
label = __INTERRUPTOR_TABLE__,
|
||||
count = __INTERRUPTOR_COUNT__,
|
||||
segment = RODATA,
|
||||
import = __CALLIRQ__;
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
make clean
|
||||
make
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -d ..\Binary\Flasher.dsk flasher
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -as ..\Binary\Flasher.dsk flasher < Flasher.bin
|
||||
copy Flasher.bin ..\Binary
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/bash
|
||||
|
||||
make clean
|
||||
make
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -d ../Binary/Flasher.dsk flasher
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -as ../Binary/Flasher.dsk flasher < Flasher.bin
|
||||
cp Flasher.bin ../Binary/
|
||||
|
|
@ -0,0 +1,346 @@
|
|||
###############################################################################
|
||||
### Generic Makefile for cc65 projects - full version with abstract options ###
|
||||
### V1.3.0(w) 2010 - 2013 Oliver Schmidt & Patryk "Silver Dream !" ?ogiewa ###
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
### In order to override defaults - values can be assigned to the variables ###
|
||||
###############################################################################
|
||||
|
||||
# Space or comma separated list of cc65 supported target platforms to build for.
|
||||
# Default: c64 (lowercase!)
|
||||
TARGETS := apple2enh
|
||||
|
||||
# Name of the final, single-file executable.
|
||||
# Default: name of the current dir with target name appended
|
||||
PROGRAM := Flasher
|
||||
|
||||
# Path(s) to additional libraries required for linking the program
|
||||
# Use only if you don't want to place copies of the libraries in SRCDIR
|
||||
# Default: none
|
||||
LIBS :=
|
||||
|
||||
# Custom linker configuration file
|
||||
# Use only if you don't want to place it in SRCDIR
|
||||
# Default: none
|
||||
CONFIG := apple2enh-system.cfg
|
||||
|
||||
# Additional C compiler flags and options.
|
||||
# Default: none
|
||||
CFLAGS =
|
||||
|
||||
# Additional assembler flags and options.
|
||||
# Default: none
|
||||
ASFLAGS =
|
||||
|
||||
# Additional linker flags and options.
|
||||
# Default: none
|
||||
LDFLAGS =
|
||||
|
||||
# Path to the directory containing C and ASM sources.
|
||||
# Default: src
|
||||
SRCDIR :=
|
||||
|
||||
# Path to the directory where object files are to be stored (inside respective target subdirectories).
|
||||
# Default: obj
|
||||
OBJDIR :=
|
||||
|
||||
# Command used to run the emulator.
|
||||
# Default: depending on target platform. For default (c64) target: x64 -kernal kernal -VICIIdsize -autoload
|
||||
EMUCMD :=
|
||||
|
||||
# Optional commands used before starting the emulation process, and after finishing it.
|
||||
# Default: none
|
||||
# Examples
|
||||
#PREEMUCMD := osascript -e "tell application \"System Events\" to set isRunning to (name of processes) contains \"X11.bin\"" -e "if isRunning is true then tell application \"X11\" to activate"
|
||||
#PREEMUCMD := osascript -e "tell application \"X11\" to activate"
|
||||
#POSTEMUCMD := osascript -e "tell application \"System Events\" to tell process \"X11\" to set visible to false"
|
||||
#POSTEMUCMD := osascript -e "tell application \"Terminal\" to activate"
|
||||
PREEMUCMD :=
|
||||
POSTEMUCMD :=
|
||||
|
||||
# On Windows machines VICE emulators may not be available in the PATH by default.
|
||||
# In such case, please set the variable below to point to directory containing
|
||||
# VICE emulators.
|
||||
#VICE_HOME := "C:\Program Files\WinVICE-2.2-x86\"
|
||||
VICE_HOME :=
|
||||
|
||||
# Options state file name. You should not need to change this, but for those
|
||||
# rare cases when you feel you really need to name it differently - here you are
|
||||
STATEFILE := Makefile.options
|
||||
|
||||
###################################################################################
|
||||
#### DO NOT EDIT BELOW THIS LINE, UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! ####
|
||||
###################################################################################
|
||||
|
||||
###################################################################################
|
||||
### Mapping abstract options to the actual compiler, assembler and linker flags ###
|
||||
### Predefined compiler, assembler and linker flags, used with abstract options ###
|
||||
### valid for 2.14.x. Consult the documentation of your cc65 version before use ###
|
||||
###################################################################################
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SPEED
|
||||
define _optspeed_
|
||||
CFLAGS += -Oris
|
||||
endef
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SIZE
|
||||
define _optsize_
|
||||
CFLAGS += -Or
|
||||
endef
|
||||
|
||||
# Compiler and assembler flags for generating listings
|
||||
define _listing_
|
||||
CFLAGS += --listing $$(@:.o=.lst) -T
|
||||
ASFLAGS += --listing $$(@:.o=.lst)
|
||||
REMOVES += $(addsuffix .lst,$(basename $(OBJECTS)))
|
||||
endef
|
||||
|
||||
# Linker flags for generating map file
|
||||
define _mapfile_
|
||||
LDFLAGS += --mapfile $$@.map
|
||||
REMOVES += $(PROGRAM).map
|
||||
endef
|
||||
|
||||
# Linker flags for generating VICE label file
|
||||
define _labelfile_
|
||||
LDFLAGS += -Ln $$@.lbl
|
||||
REMOVES += $(PROGRAM).lbl
|
||||
endef
|
||||
|
||||
# Linker flags for generating a debug file
|
||||
define _debugfile_
|
||||
LDFLAGS += -Wl --dbgfile,$$@.dbg
|
||||
REMOVES += $(PROGRAM).dbg
|
||||
endef
|
||||
|
||||
###############################################################################
|
||||
### Defaults to be used if nothing defined in the editable sections above ###
|
||||
###############################################################################
|
||||
|
||||
# Presume the C64 target like the cl65 compile & link utility does.
|
||||
# Set TARGETS to override.
|
||||
ifeq ($(TARGETS),)
|
||||
TARGETS := c64
|
||||
endif
|
||||
|
||||
# Presume we're in a project directory so name the program like the current
|
||||
# directory. Set PROGRAM to override.
|
||||
ifeq ($(PROGRAM),)
|
||||
PROGRAM := $(notdir $(CURDIR))
|
||||
endif
|
||||
|
||||
# Presume the C and asm source files to be located in the subdirectory 'src'.
|
||||
# Set SRCDIR to override.
|
||||
ifeq ($(SRCDIR),)
|
||||
SRCDIR := src
|
||||
endif
|
||||
|
||||
# Presume the object and dependency files to be located in the subdirectory
|
||||
# 'obj' (which will be created). Set OBJDIR to override.
|
||||
ifeq ($(OBJDIR),)
|
||||
OBJDIR := obj
|
||||
endif
|
||||
TARGETOBJDIR := $(OBJDIR)
|
||||
|
||||
# On Windows it is mandatory to have CC65_HOME set. So do not unnecessarily
|
||||
# rely on cl65 being added to the PATH in this scenario.
|
||||
ifdef CC65_HOME
|
||||
CC := $(CC65_HOME)/bin/cl65
|
||||
else
|
||||
CC := cl65
|
||||
endif
|
||||
|
||||
# Default emulator commands and options for particular targets.
|
||||
# Set EMUCMD to override.
|
||||
c64_EMUCMD := $(VICE_HOME)x64 -kernal kernal -VICIIdsize -autoload
|
||||
c128_EMUCMD := $(VICE_HOME)x128 -kernal kernal -VICIIdsize -autoload
|
||||
vic20_EMUCMD := $(VICE_HOME)xvic -kernal kernal -VICdsize -autoload
|
||||
pet_EMUCMD := $(VICE_HOME)xpet -Crtcdsize -autoload
|
||||
plus4_EMUCMD := $(VICE_HOME)xplus4 -TEDdsize -autoload
|
||||
# So far there is no x16 emulator in VICE (why??) so we have to use xplus4 with -memsize option
|
||||
c16_EMUCMD := $(VICE_HOME)xplus4 -ramsize 16 -TEDdsize -autoload
|
||||
cbm510_EMUCMD := $(VICE_HOME)xcbm2 -model 510 -VICIIdsize -autoload
|
||||
cbm610_EMUCMD := $(VICE_HOME)xcbm2 -model 610 -Crtcdsize -autoload
|
||||
atari_EMUCMD := atari800 -windowed -xl -pal -nopatchall -run
|
||||
|
||||
ifeq ($(EMUCMD),)
|
||||
EMUCMD = $($(CC65TARGET)_EMUCMD)
|
||||
endif
|
||||
|
||||
###############################################################################
|
||||
### The magic begins ###
|
||||
###############################################################################
|
||||
|
||||
# The "Native Win32" GNU Make contains quite some workarounds to get along with
|
||||
# cmd.exe as shell. However it does not provide means to determine that it does
|
||||
# actually activate those workarounds. Especially $(SHELL) does NOT contain the
|
||||
# value 'cmd.exe'. So the usual way to determine if cmd.exe is being used is to
|
||||
# execute the command 'echo' without any parameters. Only cmd.exe will return a
|
||||
# non-empty string - saying 'ECHO is on/off'.
|
||||
#
|
||||
# Many "Native Win32" programs accept '/' as directory delimiter just fine. How-
|
||||
# ever the internal commands of cmd.exe generally require '\' to be used.
|
||||
#
|
||||
# cmd.exe has an internal command 'mkdir' that doesn't understand nor require a
|
||||
# '-p' to create parent directories as needed.
|
||||
#
|
||||
# cmd.exe has an internal command 'del' that reports a syntax error if executed
|
||||
# without any file so make sure to call it only if there's an actual argument.
|
||||
ifeq ($(shell echo),)
|
||||
MKDIR = mkdir -p $1
|
||||
RMDIR = rmdir $1
|
||||
RMFILES = $(RM) $1
|
||||
else
|
||||
MKDIR = mkdir $(subst /,\,$1)
|
||||
RMDIR = rmdir $(subst /,\,$1)
|
||||
RMFILES = $(if $1,del /f $(subst /,\,$1))
|
||||
endif
|
||||
COMMA := ,
|
||||
SPACE := $(N/A) $(N/A)
|
||||
define NEWLINE
|
||||
|
||||
|
||||
endef
|
||||
# Note: Do not remove any of the two empty lines above !
|
||||
|
||||
TARGETLIST := $(subst $(COMMA),$(SPACE),$(TARGETS))
|
||||
|
||||
ifeq ($(words $(TARGETLIST)),1)
|
||||
|
||||
# Set PROGRAM to something like 'myprog.c64'.
|
||||
override PROGRAM := $(PROGRAM).bin
|
||||
|
||||
# Set SOURCES to something like 'src/foo.c src/bar.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES := $(wildcard $(SRCDIR)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.a65)
|
||||
|
||||
# Add to SOURCES something like 'src/c64/me.c src/c64/too.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.a65)
|
||||
|
||||
# Set OBJECTS to something like 'obj/c64/foo.o obj/c64/bar.o'.
|
||||
OBJECTS := $(addsuffix .o,$(basename $(addprefix $(TARGETOBJDIR)/,$(notdir $(SOURCES)))))
|
||||
|
||||
# Set DEPENDS to something like 'obj/c64/foo.d obj/c64/bar.d'.
|
||||
DEPENDS := $(OBJECTS:.o=.d)
|
||||
|
||||
# Add to LIBS something like 'src/foo.lib src/c64/bar.lib'.
|
||||
LIBS += $(wildcard $(SRCDIR)/*.lib)
|
||||
LIBS += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.lib)
|
||||
|
||||
# Add to CONFIG something like 'src/c64/bar.cfg src/foo.cfg'.
|
||||
CONFIG += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.cfg)
|
||||
CONFIG += $(wildcard $(SRCDIR)/*.cfg)
|
||||
|
||||
# Select CONFIG file to use. Target specific configs have higher priority.
|
||||
ifneq ($(word 2,$(CONFIG)),)
|
||||
CONFIG := $(firstword $(CONFIG))
|
||||
$(info Using config file $(CONFIG) for linking)
|
||||
endif
|
||||
|
||||
.SUFFIXES:
|
||||
.PHONY: all test clean zap love
|
||||
|
||||
all: $(PROGRAM)
|
||||
|
||||
-include $(DEPENDS)
|
||||
-include $(STATEFILE)
|
||||
|
||||
# If OPTIONS are given on the command line then save them to STATEFILE
|
||||
# if (and only if) they have actually changed. But if OPTIONS are not
|
||||
# given on the command line then load them from STATEFILE. Have object
|
||||
# files depend on STATEFILE only if it actually exists.
|
||||
ifeq ($(origin OPTIONS),command line)
|
||||
ifneq ($(OPTIONS),$(_OPTIONS_))
|
||||
ifeq ($(OPTIONS),)
|
||||
$(info Removing OPTIONS)
|
||||
$(shell $(RM) $(STATEFILE))
|
||||
$(eval $(STATEFILE):)
|
||||
else
|
||||
$(info Saving OPTIONS=$(OPTIONS))
|
||||
$(shell echo _OPTIONS_=$(OPTIONS) > $(STATEFILE))
|
||||
endif
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
else
|
||||
ifeq ($(origin _OPTIONS_),file)
|
||||
$(info Using saved OPTIONS=$(_OPTIONS_))
|
||||
OPTIONS = $(_OPTIONS_)
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
endif
|
||||
|
||||
# Transform the abstract OPTIONS to the actual cc65 options.
|
||||
$(foreach o,$(subst $(COMMA),$(SPACE),$(OPTIONS)),$(eval $(_$o_)))
|
||||
|
||||
# Strip potential variant suffix from the actual cc65 target.
|
||||
CC65TARGET := $(firstword $(subst .,$(SPACE),$(TARGETLIST)))
|
||||
|
||||
# The remaining targets.
|
||||
$(TARGETOBJDIR):
|
||||
$(call MKDIR,$@)
|
||||
|
||||
vpath %.c $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.c | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(CFLAGS) -o $@ $<
|
||||
|
||||
vpath %.s $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.s | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.asm $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.asm | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.a65 $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.a65 | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
$(PROGRAM): $(CONFIG) $(OBJECTS) $(LIBS)
|
||||
$(CC) -t $(CC65TARGET) $(LDFLAGS) -o $@ $(patsubst %.cfg,-C %.cfg,$^)
|
||||
|
||||
test: $(PROGRAM)
|
||||
$(PREEMUCMD)
|
||||
$(EMUCMD) $<
|
||||
$(POSTEMUCMD)
|
||||
|
||||
clean:
|
||||
$(call RMFILES,$(OBJECTS))
|
||||
$(call RMFILES,$(DEPENDS))
|
||||
$(call RMFILES,$(REMOVES))
|
||||
$(call RMFILES,$(PROGRAM))
|
||||
|
||||
else # $(words $(TARGETLIST)),1
|
||||
|
||||
all test clean:
|
||||
$(foreach t,$(TARGETLIST),$(MAKE) TARGETS=$t $@$(NEWLINE))
|
||||
|
||||
endif # $(words $(TARGETLIST)),1
|
||||
|
||||
OBJDIRLIST := $(wildcard $(OBJDIR)/*)
|
||||
|
||||
zap:
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMFILES,$o/*.o $o/*.d $o/*.lst)$(NEWLINE))
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMDIR,$o)$(NEWLINE))
|
||||
-$(call RMDIR,$(OBJDIR))
|
||||
-$(call RMFILES,$(basename $(PROGRAM)).* $(STATEFILE))
|
||||
|
||||
love:
|
||||
@echo "Not war, eh?"
|
||||
|
||||
###################################################################
|
||||
### Place your additional targets in the additional Makefiles ###
|
||||
### in the same directory - their names have to end with ".mk"! ###
|
||||
###################################################################
|
||||
-include *.mk
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
#ifndef APPLE_II_SD_H
|
||||
#define APPLE_II_SD_H
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned short uint16;
|
||||
typedef unsigned long uint32;
|
||||
typedef unsigned char boolean;
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#define SLOT_IO_START (volatile uint8*)0xC080
|
||||
#define SLOT_ROM_START (volatile uint8*)0xC000
|
||||
#define EXT_ROM_START (volatile uint8*)0xC800
|
||||
|
||||
#define CFFF (volatile uint8*)0xCFFF
|
||||
|
||||
typedef volatile struct
|
||||
{
|
||||
// data register
|
||||
// +0
|
||||
uint8 data;
|
||||
|
||||
// status register
|
||||
// +1
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned pgmen : 1;
|
||||
unsigned : 1;
|
||||
unsigned ece : 1;
|
||||
unsigned : 1;
|
||||
unsigned frx : 1;
|
||||
const unsigned bsy : 1;
|
||||
unsigned : 1;
|
||||
const unsigned tc : 1;
|
||||
};
|
||||
|
||||
uint8 status;
|
||||
} status;
|
||||
|
||||
// clock divisor register, unused
|
||||
// +2
|
||||
uint8 clkDiv;
|
||||
|
||||
// slave select and card state register
|
||||
// +3
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned slaveSel : 1;
|
||||
unsigned : 3;
|
||||
unsigned sdhc : 1;
|
||||
const unsigned wp : 1;
|
||||
const unsigned card : 1;
|
||||
unsigned inited : 1;
|
||||
};
|
||||
|
||||
uint8 ss_card;
|
||||
} ss_card;
|
||||
} APPLE_II_SD_T;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
#include "AppleIISd.h"
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdio.h>
|
||||
#include <errno.h>
|
||||
#include <conio.h>
|
||||
#include <string.h>
|
||||
#include <apple2enh.h>
|
||||
|
||||
// Binary can't be larger than 2k
|
||||
#define BUFFER_SIZE 2048
|
||||
#define BIN_FILE_NAME "AppleIISd.bin"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
STATE_0, // pipe
|
||||
STATE_1, // slash
|
||||
STATE_2, // hyphen
|
||||
STATE_3, // backslash
|
||||
|
||||
STATE_LAST // don't use
|
||||
} STATE_CURSOR_T;
|
||||
|
||||
const char state_char[STATE_LAST] = { '|', '/', '-', '\\' };
|
||||
static uint8 buffer[BUFFER_SIZE];
|
||||
|
||||
static void writeChip(const uint8* pSource, volatile uint8* pDest, uint16 length);
|
||||
static boolean verifyChip(const uint8* pSource, volatile uint8* pDest, uint16 length);
|
||||
static void printStatus(uint8 percentage);
|
||||
|
||||
int main()
|
||||
{
|
||||
int retval = 1;
|
||||
FILE* pFile;
|
||||
char slotNum;
|
||||
boolean erase = FALSE;
|
||||
uint16 fileSize = 0;
|
||||
|
||||
APPLE_II_SD_T* pAIISD;
|
||||
volatile uint8* pSlotRom = SLOT_ROM_START;
|
||||
volatile uint8 dummy;
|
||||
|
||||
videomode(VIDEOMODE_40COL);
|
||||
clrscr();
|
||||
cprintf("AppleIISd firmware flasher V1.2\r\n");
|
||||
cprintf("(c) 2019-2020 Florian Reitz\r\n\r\n");
|
||||
|
||||
// ask for slot
|
||||
cursor(1); // enable blinking cursor
|
||||
cprintf("Slot number (1-7): ");
|
||||
cscanf("%c", &slotNum);
|
||||
slotNum -= 0x30;
|
||||
cursor(0); // disable blinking cursor
|
||||
|
||||
if(slotNum == 0)
|
||||
{
|
||||
// erase device
|
||||
erase = TRUE;
|
||||
// ask for slot
|
||||
cursor(1); // enable blinking cursor
|
||||
cprintf("Erase device in slot number (1-7): ");
|
||||
cscanf("%c", &slotNum);
|
||||
slotNum -= 0x30;
|
||||
cursor(0); // disable blinking cursor
|
||||
}
|
||||
|
||||
// check if slot is valid
|
||||
if((slotNum < 1) || (slotNum > 7))
|
||||
{
|
||||
cprintf("\r\nInvalid slot number!");
|
||||
cgetc();
|
||||
return 1; // failure
|
||||
}
|
||||
|
||||
pAIISD = (APPLE_II_SD_T*)(SLOT_IO_START + (slotNum << 4));
|
||||
pSlotRom += slotNum << 8;
|
||||
|
||||
if(erase)
|
||||
{
|
||||
fileSize = BUFFER_SIZE;
|
||||
memset(buffer, 0, sizeof(buffer));
|
||||
}
|
||||
else
|
||||
{
|
||||
// open file
|
||||
pFile = fopen(BIN_FILE_NAME, "rb");
|
||||
if(pFile)
|
||||
{
|
||||
// read buffer
|
||||
fileSize = fread(buffer, 1, sizeof(buffer), pFile);
|
||||
fclose(pFile);
|
||||
pFile = NULL;
|
||||
|
||||
if(fileSize != BUFFER_SIZE)
|
||||
{
|
||||
cprintf("\r\nWrong file size: %d\r\n", fileSize);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
cprintf("\r\nCan't open %s file\r\n", BIN_FILE_NAME);
|
||||
fileSize = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if(fileSize == BUFFER_SIZE)
|
||||
{
|
||||
// enable write
|
||||
pAIISD->status.pgmen = 1;
|
||||
|
||||
// write to SLOTROM
|
||||
cprintf("\r\n\r\nFlashing SLOTROM: ");
|
||||
writeChip(buffer, pSlotRom, 256);
|
||||
|
||||
cprintf("\r\nVerifying SLOTROM: ");
|
||||
if(verifyChip(buffer, pSlotRom, 256))
|
||||
{
|
||||
// write to EXT_ROM
|
||||
cprintf("\r\n\r\nFlashing EXTROM: ");
|
||||
|
||||
// clear CFFF and dummy read to enable correct EXT_ROM
|
||||
dummy = *CFFF;
|
||||
dummy = *pSlotRom;
|
||||
|
||||
writeChip(buffer + 256, EXT_ROM_START, fileSize - 256);
|
||||
cprintf("\r\nVerifying EXTROM: ");
|
||||
|
||||
dummy = *CFFF;
|
||||
dummy = *pSlotRom;
|
||||
|
||||
if(verifyChip(buffer + 256, EXT_ROM_START, fileSize - 256))
|
||||
{
|
||||
cprintf("\r\n\r\nFlashing finished!\n");
|
||||
retval = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// disable write
|
||||
pAIISD->status.pgmen = 0;
|
||||
}
|
||||
|
||||
cgetc();
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void writeChip(const uint8* pSource, volatile uint8* pDest, uint16 length)
|
||||
{
|
||||
uint32 i;
|
||||
volatile uint8 readData;
|
||||
|
||||
for(i=0; i<length; i++)
|
||||
{
|
||||
pDest[i] = pSource[i];
|
||||
printStatus((i * 100u / length) + 1);
|
||||
|
||||
// wait for write cycle
|
||||
do
|
||||
{
|
||||
readData = pDest[i];
|
||||
}
|
||||
while((readData & 0x80) != (pSource[i] & 0x80));
|
||||
}
|
||||
}
|
||||
|
||||
static boolean verifyChip(const uint8* pSource, volatile uint8* pDest, uint16 length)
|
||||
{
|
||||
uint32 i;
|
||||
|
||||
for(i=0; i<length; i++)
|
||||
{
|
||||
printStatus((i * 100u / length) + 1);
|
||||
|
||||
if(pDest[i] != pSource[i])
|
||||
{
|
||||
// verification not successful
|
||||
cprintf("\r\n\r\n!!! Verification failed at %p !!!\r\n", &pDest[i]);
|
||||
cprintf("Was 0x%02hhX, should be 0x%02hhX\r\n", pDest[i], pSource[i]);
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void printStatus(uint8 percentage)
|
||||
{
|
||||
static STATE_CURSOR_T state = STATE_0;
|
||||
uint8 wait = 0;
|
||||
uint8 x = wherex();
|
||||
char cState = (percentage < 100) ? state_char[state] : ' ';
|
||||
|
||||
cprintf("% 3hhu%% %c", percentage, cState);
|
||||
gotox(x);
|
||||
|
||||
state++;
|
||||
if(state == STATE_LAST)
|
||||
{
|
||||
state = STATE_0;
|
||||
}
|
||||
}
|
||||
|
|
@ -31,18 +31,19 @@ use IEEE.STD_LOGIC_1164.ALL;
|
|||
|
||||
entity AddressDecoder is
|
||||
Port ( A : in std_logic_vector (11 downto 8);
|
||||
B : out std_logic_vector (10 downto 8); -- to EPROM
|
||||
B : out std_logic_vector (10 downto 8); -- to EEPROM
|
||||
CLK : in std_logic;
|
||||
PHI0 : in std_logic;
|
||||
RNW : in std_logic;
|
||||
NDEV_SEL : in std_logic; -- $C0n0 - $C0nF
|
||||
NIO_SEL : in std_logic; -- $Cs00 - $CsFF
|
||||
NIO_STB : in std_logic; -- $C800 - $CFFF
|
||||
NDEV_SEL : in std_logic; -- $C0n0 - $C0nF, CPLD registers
|
||||
NIO_SEL : in std_logic; -- $Cs00 - $CsFF, EEPROM bank 0
|
||||
NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
|
||||
NRESET : in std_logic;
|
||||
DATA_EN : out std_logic; -- to CPLD
|
||||
DATA_EN : out std_logic; -- to CPLD
|
||||
PGM_EN : in std_logic; -- from CPLD;
|
||||
NG : out std_logic; -- to bus transceiver
|
||||
NOE : out std_logic;
|
||||
LED : out std_logic); -- to EPROM
|
||||
NOE : out std_logic; -- to EEPROM
|
||||
NWE : out std_logic); -- to EEPROM
|
||||
end AddressDecoder;
|
||||
|
||||
architecture Behavioral of AddressDecoder is
|
||||
|
|
@ -51,7 +52,7 @@ architecture Behavioral of AddressDecoder is
|
|||
signal ndev_sel_int : std_logic;
|
||||
signal nio_sel_int : std_logic;
|
||||
signal nio_stb_int : std_logic;
|
||||
signal ncs : std_logic; -- $C800 - $CFFF enabled
|
||||
signal ncs : std_logic; -- $C800 - $CFFE enabled
|
||||
signal a_int : std_logic_vector (11 downto 8);
|
||||
|
||||
begin
|
||||
|
|
@ -65,7 +66,6 @@ begin
|
|||
-- $C0xx to $C7xx is mapped to EEPROM bank 0
|
||||
-- $C8xx to $CExx is mapped to banks 1 to 7
|
||||
|
||||
LED <= ncs;
|
||||
B(8) <= (a_int(11) and not a_int(8))
|
||||
or (a_int(11) and a_int(10) and a_int(9));
|
||||
B(9) <= (a_int(11) and not a_int(9) and a_int(8))
|
||||
|
|
@ -79,8 +79,14 @@ begin
|
|||
or (ndev_sel_int and nio_sel_int and ncs)
|
||||
or not PHI0;
|
||||
NOE <= not RNW
|
||||
or not NDEV_SEL
|
||||
or (not NIO_STB and ncs);
|
||||
or (not NIO_SEL and not NIO_STB)
|
||||
or (NIO_SEL and NIO_STB)
|
||||
or (NIO_SEL and ncs);
|
||||
NWE <= RNW
|
||||
or (not NIO_SEL and not NIO_STB)
|
||||
or (NIO_SEL and NIO_STB)
|
||||
or (NIO_SEL and ncs)
|
||||
or not PGM_EN;
|
||||
|
||||
cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
|
||||
|
||||
|
|
@ -107,6 +113,4 @@ begin
|
|||
a_int <= A;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
|
|
|||
|
|
@ -50,10 +50,11 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
|
|||
NIO_SEL : IN std_logic;
|
||||
NIO_STB : IN std_logic;
|
||||
NRESET : IN std_logic;
|
||||
DATA_EN : OUT std_logic;
|
||||
DATA_EN : OUT std_logic;
|
||||
PGM_EN : IN std_logic;
|
||||
NG : OUT std_logic;
|
||||
NOE : OUT std_logic;
|
||||
LED : OUT std_logic
|
||||
NWE : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
|
@ -66,21 +67,22 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
|
|||
signal NIO_STB : std_logic := '1';
|
||||
signal NRESET : std_logic := '1';
|
||||
signal CLK : std_logic := '0';
|
||||
signal PHI0 : std_logic := '1';
|
||||
signal PHI0 : std_logic := '1';
|
||||
signal PGM_EN : std_logic := '1';
|
||||
|
||||
--Outputs
|
||||
--Outputs
|
||||
signal B : std_logic_vector(10 downto 8);
|
||||
signal DATA_EN : std_logic;
|
||||
signal NG : std_logic;
|
||||
signal NOE : std_logic;
|
||||
signal LED : std_logic;
|
||||
signal NWE : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 142 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: AddressDecoder PORT MAP (
|
||||
A => A,
|
||||
B => B,
|
||||
|
|
@ -91,19 +93,20 @@ BEGIN
|
|||
NIO_SEL => NIO_SEL,
|
||||
NIO_STB => NIO_STB,
|
||||
NRESET => NRESET,
|
||||
DATA_EN => DATA_EN,
|
||||
DATA_EN => DATA_EN,
|
||||
PGM_EN => PGM_EN,
|
||||
NG => NG,
|
||||
NOE => NOE,
|
||||
LED => LED
|
||||
NWE => NWE
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
PHI0_process :process(CLK)
|
||||
|
|
@ -120,7 +123,7 @@ BEGIN
|
|||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
begin
|
||||
-- hold reset state.
|
||||
wait for CLK_period * 10;
|
||||
NRESET <= '0';
|
||||
|
|
@ -128,60 +131,209 @@ BEGIN
|
|||
NRESET <= '1';
|
||||
wait for CLK_period * 10;
|
||||
|
||||
-- insert stimulus here
|
||||
-- C0nX access
|
||||
-- NG must be '0"
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "0000"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
|
||||
-- C0nX access, write
|
||||
-- NG must be '0"
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
A <= "0000"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access
|
||||
-- CnXX access, select
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access, write, select
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access, write, select, no PGM_EN
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
PGM_EN <= '0';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
PGM_EN <= '1';
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx write access, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C9xx access, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "1001"; -- must become "010"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="010") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C9xx access write, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CPLD access
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "0101"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CFFF access
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "1111"; -- must become "111"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="111") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access, unselected
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access write, unselected
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
MODULE AddressDecoder_old
|
||||
|
|
@ -1,275 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<drawing version="7">
|
||||
<attr value="xc9500xl" name="DeviceFamilyName">
|
||||
<trait delete="all:0" />
|
||||
<trait editname="all:0" />
|
||||
<trait edittrait="all:0" />
|
||||
</attr>
|
||||
<netlist>
|
||||
<signal name="A10" />
|
||||
<signal name="A9" />
|
||||
<signal name="A8" />
|
||||
<signal name="XLXN_10" />
|
||||
<signal name="CLK" />
|
||||
<signal name="XLXN_14" />
|
||||
<signal name="B10" />
|
||||
<signal name="B9" />
|
||||
<signal name="B8" />
|
||||
<signal name="NIO_SEL" />
|
||||
<signal name="NIO_STB" />
|
||||
<signal name="XLXN_38" />
|
||||
<signal name="XLXN_46" />
|
||||
<signal name="XLXN_47" />
|
||||
<signal name="NDEV_SEL" />
|
||||
<signal name="NOE" />
|
||||
<signal name="XLXN_53" />
|
||||
<signal name="RNW" />
|
||||
<signal name="XLXN_55" />
|
||||
<port polarity="Input" name="A10" />
|
||||
<port polarity="Input" name="A9" />
|
||||
<port polarity="Input" name="A8" />
|
||||
<port polarity="Input" name="CLK" />
|
||||
<port polarity="Output" name="B10" />
|
||||
<port polarity="Output" name="B9" />
|
||||
<port polarity="Output" name="B8" />
|
||||
<port polarity="Input" name="NIO_SEL" />
|
||||
<port polarity="Input" name="NIO_STB" />
|
||||
<port polarity="Input" name="NDEV_SEL" />
|
||||
<port polarity="Output" name="NOE" />
|
||||
<port polarity="Input" name="RNW" />
|
||||
<blockdef name="fdrs">
|
||||
<timestamp>2001-3-9T11:23:0</timestamp>
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="64" y1="-256" y2="-256" x1="0" />
|
||||
<line x2="320" y1="-256" y2="-256" x1="384" />
|
||||
<line x2="64" y1="-32" y2="-32" x1="0" />
|
||||
<line x2="64" y1="-352" y2="-352" x1="0" />
|
||||
<rect width="256" x="64" y="-320" height="256" />
|
||||
<line x2="192" y1="-64" y2="-32" x1="192" />
|
||||
<line x2="64" y1="-32" y2="-32" x1="192" />
|
||||
<line x2="80" y1="-112" y2="-128" x1="64" />
|
||||
<line x2="64" y1="-128" y2="-144" x1="80" />
|
||||
<line x2="192" y1="-320" y2="-352" x1="192" />
|
||||
<line x2="64" y1="-352" y2="-352" x1="192" />
|
||||
</blockdef>
|
||||
<blockdef name="inv">
|
||||
<timestamp>2001-3-9T11:23:50</timestamp>
|
||||
<line x2="64" y1="-32" y2="-32" x1="0" />
|
||||
<line x2="160" y1="-32" y2="-32" x1="224" />
|
||||
<line x2="128" y1="-64" y2="-32" x1="64" />
|
||||
<line x2="64" y1="-32" y2="0" x1="128" />
|
||||
<line x2="64" y1="0" y2="-64" x1="64" />
|
||||
<circle r="16" cx="144" cy="-32" />
|
||||
</blockdef>
|
||||
<blockdef name="vcc">
|
||||
<timestamp>2001-3-9T11:23:11</timestamp>
|
||||
<line x2="32" y1="-64" y2="-64" x1="96" />
|
||||
<line x2="64" y1="0" y2="-32" x1="64" />
|
||||
<line x2="64" y1="-32" y2="-64" x1="64" />
|
||||
</blockdef>
|
||||
<blockdef name="and2">
|
||||
<timestamp>2001-5-11T10:41:37</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="192" y1="-96" y2="-96" x1="256" />
|
||||
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
|
||||
<line x2="64" y1="-48" y2="-48" x1="144" />
|
||||
<line x2="144" y1="-144" y2="-144" x1="64" />
|
||||
<line x2="64" y1="-48" y2="-144" x1="64" />
|
||||
</blockdef>
|
||||
<blockdef name="and4">
|
||||
<timestamp>2001-5-11T10:43:14</timestamp>
|
||||
<line x2="64" y1="-112" y2="-112" x1="144" />
|
||||
<arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
|
||||
<line x2="144" y1="-208" y2="-208" x1="64" />
|
||||
<line x2="64" y1="-64" y2="-256" x1="64" />
|
||||
<line x2="192" y1="-160" y2="-160" x1="256" />
|
||||
<line x2="64" y1="-256" y2="-256" x1="0" />
|
||||
<line x2="64" y1="-192" y2="-192" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
</blockdef>
|
||||
<blockdef name="nand2">
|
||||
<timestamp>2001-3-9T11:23:50</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="216" y1="-96" y2="-96" x1="256" />
|
||||
<circle r="12" cx="204" cy="-96" />
|
||||
<line x2="64" y1="-48" y2="-144" x1="64" />
|
||||
<line x2="144" y1="-144" y2="-144" x1="64" />
|
||||
<line x2="64" y1="-48" y2="-48" x1="144" />
|
||||
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
|
||||
</blockdef>
|
||||
<blockdef name="or2">
|
||||
<timestamp>2000-1-1T10:10:10</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="192" y1="-96" y2="-96" x1="256" />
|
||||
<arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
|
||||
<arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
|
||||
<line x2="48" y1="-144" y2="-144" x1="112" />
|
||||
<arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
|
||||
<line x2="48" y1="-48" y2="-48" x1="112" />
|
||||
</blockdef>
|
||||
<block symbolname="fdrs" name="XLXI_16">
|
||||
<blockpin signalname="CLK" name="C" />
|
||||
<blockpin signalname="XLXN_14" name="D" />
|
||||
<blockpin signalname="XLXN_10" name="R" />
|
||||
<blockpin signalname="XLXN_46" name="S" />
|
||||
<blockpin signalname="XLXN_47" name="Q" />
|
||||
</block>
|
||||
<block symbolname="vcc" name="XLXI_17">
|
||||
<blockpin signalname="XLXN_14" name="P" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_18">
|
||||
<blockpin signalname="A10" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B10" name="O" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_19">
|
||||
<blockpin signalname="A9" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B9" name="O" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_20">
|
||||
<blockpin signalname="A8" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B8" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_22">
|
||||
<blockpin signalname="NIO_SEL" name="I" />
|
||||
<blockpin signalname="XLXN_46" name="O" />
|
||||
</block>
|
||||
<block symbolname="and4" name="XLXI_30">
|
||||
<blockpin signalname="A8" name="I0" />
|
||||
<blockpin signalname="A9" name="I1" />
|
||||
<blockpin signalname="A10" name="I2" />
|
||||
<blockpin signalname="XLXN_38" name="I3" />
|
||||
<blockpin signalname="XLXN_10" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_31">
|
||||
<blockpin signalname="NIO_STB" name="I" />
|
||||
<blockpin signalname="XLXN_38" name="O" />
|
||||
</block>
|
||||
<block symbolname="nand2" name="XLXI_32">
|
||||
<blockpin signalname="XLXN_47" name="I0" />
|
||||
<blockpin signalname="NDEV_SEL" name="I1" />
|
||||
<blockpin signalname="XLXN_55" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_33">
|
||||
<blockpin signalname="RNW" name="I" />
|
||||
<blockpin signalname="XLXN_53" name="O" />
|
||||
</block>
|
||||
<block symbolname="or2" name="XLXI_34">
|
||||
<blockpin signalname="XLXN_55" name="I0" />
|
||||
<blockpin signalname="XLXN_53" name="I1" />
|
||||
<blockpin signalname="NOE" name="O" />
|
||||
</block>
|
||||
</netlist>
|
||||
<sheet sheetnum="1" width="3520" height="2720">
|
||||
<branch name="A10">
|
||||
<wire x2="592" y1="704" y2="704" x1="320" />
|
||||
<wire x2="704" y1="704" y2="704" x1="592" />
|
||||
<wire x2="592" y1="704" y2="992" x1="592" />
|
||||
<wire x2="1088" y1="992" y2="992" x1="592" />
|
||||
</branch>
|
||||
<branch name="A9">
|
||||
<wire x2="528" y1="768" y2="768" x1="320" />
|
||||
<wire x2="704" y1="768" y2="768" x1="528" />
|
||||
<wire x2="528" y1="768" y2="1136" x1="528" />
|
||||
<wire x2="1088" y1="1136" y2="1136" x1="528" />
|
||||
</branch>
|
||||
<branch name="A8">
|
||||
<wire x2="464" y1="832" y2="832" x1="320" />
|
||||
<wire x2="704" y1="832" y2="832" x1="464" />
|
||||
<wire x2="464" y1="832" y2="1280" x1="464" />
|
||||
<wire x2="1088" y1="1280" y2="1280" x1="464" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="704" name="A10" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="768" name="A9" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="832" name="A8" orien="R180" />
|
||||
<branch name="CLK">
|
||||
<wire x2="912" y1="576" y2="576" x1="320" />
|
||||
<wire x2="912" y1="576" y2="640" x1="912" />
|
||||
<wire x2="992" y1="640" y2="640" x1="912" />
|
||||
</branch>
|
||||
<branch name="B10">
|
||||
<wire x2="1664" y1="960" y2="960" x1="1344" />
|
||||
</branch>
|
||||
<branch name="B9">
|
||||
<wire x2="1664" y1="1104" y2="1104" x1="1344" />
|
||||
</branch>
|
||||
<branch name="B8">
|
||||
<wire x2="1664" y1="1248" y2="1248" x1="1344" />
|
||||
</branch>
|
||||
<branch name="NIO_SEL">
|
||||
<wire x2="352" y1="368" y2="368" x1="320" />
|
||||
</branch>
|
||||
<branch name="NIO_STB">
|
||||
<wire x2="336" y1="640" y2="640" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="368" name="NIO_SEL" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="640" name="NIO_STB" orien="R180" />
|
||||
<instance x="336" y="672" name="XLXI_31" orien="R0" />
|
||||
<branch name="XLXN_38">
|
||||
<wire x2="672" y1="640" y2="640" x1="560" />
|
||||
<wire x2="704" y1="640" y2="640" x1="672" />
|
||||
<wire x2="672" y1="640" y2="928" x1="672" />
|
||||
<wire x2="1088" y1="928" y2="928" x1="672" />
|
||||
<wire x2="672" y1="928" y2="1072" x1="672" />
|
||||
<wire x2="1088" y1="1072" y2="1072" x1="672" />
|
||||
<wire x2="672" y1="1072" y2="1216" x1="672" />
|
||||
<wire x2="1088" y1="1216" y2="1216" x1="672" />
|
||||
</branch>
|
||||
<instance x="704" y="896" name="XLXI_30" orien="R0" />
|
||||
<branch name="XLXN_10">
|
||||
<wire x2="992" y1="736" y2="736" x1="960" />
|
||||
</branch>
|
||||
<branch name="XLXN_14">
|
||||
<wire x2="848" y1="496" y2="512" x1="848" />
|
||||
<wire x2="992" y1="512" y2="512" x1="848" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="576" name="CLK" orien="R180" />
|
||||
<instance x="784" y="496" name="XLXI_17" orien="R0" />
|
||||
<instance x="352" y="400" name="XLXI_22" orien="R0" />
|
||||
<branch name="XLXN_46">
|
||||
<wire x2="992" y1="368" y2="368" x1="576" />
|
||||
<wire x2="992" y1="368" y2="416" x1="992" />
|
||||
</branch>
|
||||
<instance x="992" y="768" name="XLXI_16" orien="R0" />
|
||||
<instance x="1088" y="1056" name="XLXI_18" orien="R0" />
|
||||
<instance x="1088" y="1200" name="XLXI_19" orien="R0" />
|
||||
<instance x="1088" y="1344" name="XLXI_20" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="960" name="B10" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="1104" name="B9" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="1248" name="B8" orien="R0" />
|
||||
<instance x="1424" y="432" name="XLXI_32" orien="R0" />
|
||||
<branch name="XLXN_47">
|
||||
<wire x2="1392" y1="512" y2="512" x1="1376" />
|
||||
<wire x2="1424" y1="368" y2="368" x1="1392" />
|
||||
<wire x2="1392" y1="368" y2="512" x1="1392" />
|
||||
</branch>
|
||||
<branch name="NDEV_SEL">
|
||||
<wire x2="1424" y1="304" y2="304" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="304" name="NDEV_SEL" orien="R180" />
|
||||
<instance x="352" y="272" name="XLXI_33" orien="R0" />
|
||||
<branch name="NOE">
|
||||
<wire x2="2016" y1="272" y2="272" x1="2000" />
|
||||
</branch>
|
||||
<branch name="XLXN_53">
|
||||
<wire x2="1744" y1="240" y2="240" x1="576" />
|
||||
</branch>
|
||||
<branch name="RNW">
|
||||
<wire x2="352" y1="240" y2="240" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="240" name="RNW" orien="R180" />
|
||||
<instance x="1744" y="368" name="XLXI_34" orien="R0" />
|
||||
<branch name="XLXN_55">
|
||||
<wire x2="1696" y1="336" y2="336" x1="1680" />
|
||||
<wire x2="1744" y1="304" y2="304" x1="1696" />
|
||||
<wire x2="1696" y1="304" y2="336" x1="1696" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="2016" y="272" name="NOE" orien="R0" />
|
||||
</sheet>
|
||||
</drawing>
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 23:42:22 10/10/2017
|
||||
-- Design Name:
|
||||
-- Module Name: C:/Git/AppleIISd/VHDL/AddressDecoder_Test.vhd
|
||||
-- Project Name: AppleIISd
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: AddressDecoder
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY AddressDecoder_old_Test IS
|
||||
END AddressDecoder_old_Test;
|
||||
|
||||
ARCHITECTURE behavior OF AddressDecoder_old_Test IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT AddressDecoder_old
|
||||
PORT(
|
||||
A8 : IN std_logic;
|
||||
A9 : IN std_logic;
|
||||
A10 : IN std_logic;
|
||||
B8 : OUT std_logic;
|
||||
B9 : OUT std_logic;
|
||||
B10 : OUT std_logic;
|
||||
RNW : IN std_logic;
|
||||
CLK : IN std_logic;
|
||||
NDEV_SEL : IN std_logic;
|
||||
NIO_SEL : IN std_logic;
|
||||
NIO_STB : IN std_logic;
|
||||
NOE : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal A : std_logic_vector(10 downto 8) := "101";
|
||||
signal RNW : std_logic := '1';
|
||||
signal NDEV_SEL : std_logic := '1';
|
||||
signal NIO_SEL : std_logic := '1';
|
||||
signal NIO_STB : std_logic := '1';
|
||||
signal NRESET : std_logic := '1';
|
||||
signal CLK : std_logic := '0';
|
||||
signal PHI0 : std_logic := '1';
|
||||
|
||||
--Outputs
|
||||
signal B : std_logic_vector(10 downto 8);
|
||||
signal DATA_EN : std_logic;
|
||||
signal NG : std_logic;
|
||||
signal NOE : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 142 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: AddressDecoder_old PORT MAP (
|
||||
A8 => A(8),
|
||||
A9 => A(9),
|
||||
A10 => A(10),
|
||||
B8 => B(8),
|
||||
B9 => B(9),
|
||||
B10 => B(10),
|
||||
RNW => RNW,
|
||||
CLK => CLK,
|
||||
NDEV_SEL => NDEV_SEL,
|
||||
NIO_SEL => NIO_SEL,
|
||||
NIO_STB => NIO_STB,
|
||||
NOE => NOE
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
PHI0_process :process(CLK)
|
||||
variable counter : integer range 0 to 7;
|
||||
begin
|
||||
if rising_edge(CLK) or falling_edge(CLK) then
|
||||
counter := counter + 1;
|
||||
if counter = 7 then
|
||||
PHI0 <= not PHI0;
|
||||
counter := 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state.
|
||||
wait for CLK_period * 10;
|
||||
NRESET <= '0';
|
||||
wait for CLK_period * 20;
|
||||
NRESET <= '1';
|
||||
wait for CLK_period * 10;
|
||||
|
||||
-- insert stimulus here
|
||||
-- CPLD access
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- CnXX access
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- C8xx access, selected
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- CPLD access
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- CFFF access
|
||||
A <= "111";
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
A <= "000";
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- C8xx access, unselected
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
Binary file not shown.
|
|
@ -1,44 +0,0 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
NET "DATA<2>" BUFG = DATA_GATE ;
|
||||
NET "DATA<3>" BUFG = DATA_GATE ;
|
||||
NET "DATA<4>" BUFG = DATA_GATE ;
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADD_HIGH<11>" LOC = "P44" ;
|
||||
NET "ADD_HIGH<10>" LOC = "P38" ;
|
||||
NET "ADD_HIGH<8>" LOC = "P36" ;
|
||||
NET "ADD_HIGH<9>" LOC = "P37" ;
|
||||
NET "ADD_LOW<0>" LOC = "P19" ;
|
||||
NET "ADD_LOW<1>" LOC = "P18" ;
|
||||
NET "B<10>" LOC = "P22" ;
|
||||
NET "B<8>" LOC = "P26" ;
|
||||
NET "B<9>" LOC = "P27" ;
|
||||
NET "CARD" LOC = "P33" ;
|
||||
NET "DATA<0>" LOC = "P3" ;
|
||||
NET "DATA<1>" LOC = "P4" ;
|
||||
NET "DATA<2>" LOC = "P5" ;
|
||||
NET "DATA<3>" LOC = "P6" ;
|
||||
NET "DATA<4>" LOC = "P7" ;
|
||||
NET "DATA<5>" LOC = "P9" ;
|
||||
NET "DATA<6>" LOC = "P11" ;
|
||||
NET "DATA<7>" LOC = "P13" ;
|
||||
NET "CLK" LOC = "P43" ;
|
||||
NET "LED" LOC = "P29" ;
|
||||
NET "NDEV_SEL" LOC = "P24" ;
|
||||
NET "NG" LOC = "P12" ;
|
||||
NET "NIO_SEL" LOC = "P14" ;
|
||||
NET "NIO_STB" LOC = "P42" ;
|
||||
NET "NOE" LOC = "P25" ;
|
||||
NET "PHI0" LOC = "P8" ;
|
||||
NET "NRESET" LOC = "P20" ;
|
||||
NET "RNW" LOC = "P1" ;
|
||||
NET "MISO" LOC = "P40" ;
|
||||
NET "MOSI" LOC = "P35" ;
|
||||
NET "NSEL" LOC = "P28" ;
|
||||
NET "SCLK" LOC = "P34" ;
|
||||
NET "WP" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -43,6 +43,7 @@ Port (
|
|||
NIO_SEL : in std_logic;
|
||||
NIO_STB : in std_logic;
|
||||
NOE : out std_logic;
|
||||
NWE : out std_logic;
|
||||
PHI0 : in std_logic;
|
||||
NRESET : in std_logic;
|
||||
RNW : in std_logic;
|
||||
|
|
@ -69,6 +70,7 @@ architecture Behavioral of AppleIISd is
|
|||
signal addr_low_int : std_logic_vector (1 downto 0);
|
||||
|
||||
signal data_en : std_logic;
|
||||
signal pgm_en : std_logic;
|
||||
|
||||
component SpiController is
|
||||
Port (
|
||||
|
|
@ -86,11 +88,12 @@ Port (
|
|||
nsel : out std_logic;
|
||||
wp : in std_logic;
|
||||
card : in std_logic;
|
||||
led : out std_logic
|
||||
led : out std_logic;
|
||||
pgm_en : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component AddressDecoder
|
||||
component AddressDecoder
|
||||
Port (
|
||||
A : in std_logic_vector (11 downto 8);
|
||||
B : out std_logic_vector (10 downto 8);
|
||||
|
|
@ -102,11 +105,13 @@ Port (
|
|||
NIO_STB : in std_logic;
|
||||
NRESET : in std_logic;
|
||||
DATA_EN : out std_logic;
|
||||
PGM_EN : in std_logic;
|
||||
NG : out std_logic;
|
||||
NOE : out std_logic;
|
||||
LED : out std_logic
|
||||
);
|
||||
end component;
|
||||
NWE : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
begin
|
||||
spi: SpiController port map(
|
||||
|
|
@ -124,7 +129,8 @@ begin
|
|||
nsel => NSEL,
|
||||
wp => WP,
|
||||
card => CARD,
|
||||
led => LED
|
||||
led => LED,
|
||||
pgm_en => pgm_en
|
||||
);
|
||||
|
||||
addDec: AddressDecoder port map(
|
||||
|
|
@ -138,9 +144,10 @@ begin
|
|||
NIO_STB => NIO_STB,
|
||||
NRESET => NRESET,
|
||||
DATA_EN => data_en,
|
||||
PGM_EN => pgm_en,
|
||||
NOE => NOE,
|
||||
NWE => NWE,
|
||||
NG => NG
|
||||
--LED => LED
|
||||
);
|
||||
|
||||
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADD_HIGH<10>" LOC = "P38" ;
|
||||
NET "ADD_HIGH<11>" LOC = "P44" ;
|
||||
NET "ADD_HIGH<8>" LOC = "P36" ;
|
||||
NET "ADD_HIGH<9>" LOC = "P37" ;
|
||||
NET "ADD_LOW<0>" LOC = "P19" ;
|
||||
NET "ADD_LOW<1>" LOC = "P18" ;
|
||||
NET "B<10>" LOC = "P22" ;
|
||||
NET "B<8>" LOC = "P26" ;
|
||||
NET "B<9>" LOC = "P27" ;
|
||||
NET "CARD" LOC = "P33" ;
|
||||
NET "CLK" LOC = "P43" ;
|
||||
NET "DATA<0>" LOC = "P3" ;
|
||||
NET "DATA<1>" LOC = "P4" ;
|
||||
NET "DATA<2>" LOC = "P5" | BUFG = DATA_GATE ;
|
||||
NET "DATA<3>" LOC = "P6" | BUFG = DATA_GATE ;
|
||||
NET "DATA<4>" LOC = "P7" | BUFG = DATA_GATE ;
|
||||
NET "DATA<5>" LOC = "P9" ;
|
||||
NET "DATA<6>" LOC = "P11" ;
|
||||
NET "DATA<7>" LOC = "P13" ;
|
||||
NET "LED" LOC = "P29" ;
|
||||
NET "MISO" LOC = "P40" ;
|
||||
NET "MOSI" LOC = "P35" ;
|
||||
NET "NDEV_SEL" LOC = "P24" ;
|
||||
NET "NG" LOC = "P12" ;
|
||||
NET "NIO_SEL" LOC = "P14" ;
|
||||
NET "NIO_STB" LOC = "P42" ;
|
||||
NET "NOE" LOC = "P25" ;
|
||||
NET "NRESET" LOC = "P20" ;
|
||||
NET "NSEL" LOC = "P28" ;
|
||||
NET "NWE" LOC = "P2" ;
|
||||
NET "PHI0" LOC = "P8" ;
|
||||
NET "RNW" LOC = "P1" ;
|
||||
NET "SCLK" LOC = "P34" ;
|
||||
NET "WP" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -16,35 +16,28 @@
|
|||
|
||||
<files>
|
||||
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
|
||||
<file xil_pn:name="AppleIISd_PC44.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_old_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="52"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
|
|
@ -159,8 +152,8 @@
|
|||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -170,7 +163,7 @@
|
|||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
|
|
@ -184,9 +177,9 @@
|
|||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -205,7 +198,7 @@
|
|||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADD_HIGH<10>" LOC = "P32" ;
|
||||
NET "ADD_HIGH<11>" LOC = "P38" ;
|
||||
NET "ADD_HIGH<8>" LOC = "P30" ;
|
||||
NET "ADD_HIGH<9>" LOC = "P31" ;
|
||||
NET "ADD_LOW<0>" LOC = "P13" ;
|
||||
NET "ADD_LOW<1>" LOC = "P12" ;
|
||||
NET "B<10>" LOC = "P16" ;
|
||||
NET "B<8>" LOC = "P20" ;
|
||||
NET "B<9>" LOC = "P21" ;
|
||||
NET "CARD" LOC = "P27" ;
|
||||
NET "CLK" LOC = "P37" ;
|
||||
NET "DATA<0>" LOC = "P41" ;
|
||||
NET "DATA<1>" LOC = "P42" ;
|
||||
NET "DATA<2>" LOC = "P43" ;
|
||||
NET "DATA<3>" LOC = "P44" ;
|
||||
NET "DATA<4>" LOC = "P1" ;
|
||||
NET "DATA<5>" LOC = "P3" ;
|
||||
NET "DATA<6>" LOC = "P5" ;
|
||||
NET "DATA<7>" LOC = "P7" ;
|
||||
NET "LED" LOC = "P23" ;
|
||||
NET "MISO" LOC = "P34" ;
|
||||
NET "MOSI" LOC = "P29" ;
|
||||
NET "NDEV_SEL" LOC = "P18" ;
|
||||
NET "NG" LOC = "P6" ;
|
||||
NET "NIO_SEL" LOC = "P8" ;
|
||||
NET "NIO_STB" LOC = "P36" ;
|
||||
NET "NOE" LOC = "P19" ;
|
||||
NET "NRESET" LOC = "P14" ;
|
||||
NET "NSEL" LOC = "P22" ;
|
||||
NET "NWE" LOC = "P40" ;
|
||||
NET "PHI0" LOC = "P2" ;
|
||||
NET "RNW" LOC = "P39" ;
|
||||
NET "SCLK" LOC = "P28" ;
|
||||
NET "WP" LOC = "P33" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_VQ44.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
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|
||||
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|
||||
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|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
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|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="_" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AppleIISd|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="AppleIISd.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="AppleIISd_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
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|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="50 us" xil_pn:valueState="non-default"/>
|
||||
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|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="iMPACT Project File" xil_pn:value="AppleIISd_VQ44.ipf" xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-09-03T14:20:38" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FD3A1F2B88484D658A65860211499755" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -24,12 +24,10 @@ Port (
|
|||
sclk : out STD_LOGIC;
|
||||
nsel : out STD_LOGIC;
|
||||
wp : in STD_LOGIC;
|
||||
card : in STD_LOGIC;
|
||||
card : in STD_LOGIC;
|
||||
pgm_en : out STD_LOGIC;
|
||||
led : out STD_LOGIC
|
||||
);
|
||||
|
||||
constant DIV_WIDTH : integer := 3;
|
||||
|
||||
end SpiController;
|
||||
|
||||
architecture Behavioral of SpiController is
|
||||
|
|
@ -39,7 +37,8 @@ architecture Behavioral of SpiController is
|
|||
signal spidatain: std_logic_vector (7 downto 0);
|
||||
signal spidataout: std_logic_vector (7 downto 0);
|
||||
signal sdhc: std_logic; -- is SDHC card
|
||||
signal inited: std_logic; -- card initialized
|
||||
signal inited: std_logic; -- card initialized
|
||||
signal pgmen: std_logic; -- enable EEPROM programming
|
||||
|
||||
-- spi register flags
|
||||
signal tc: std_logic; -- transmission complete; cleared on spi data read
|
||||
|
|
@ -47,7 +46,6 @@ architecture Behavioral of SpiController is
|
|||
signal frx: std_logic; -- fast receive mode
|
||||
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
|
||||
|
||||
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
|
||||
signal slavesel: std_logic := '1'; -- slave select output (0=selected)
|
||||
signal int_miso: std_logic;
|
||||
--------------------------
|
||||
|
|
@ -61,12 +59,9 @@ architecture Behavioral of SpiController is
|
|||
|
||||
-- spi clock
|
||||
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
|
||||
-- TODO divcnt is not used at all??
|
||||
--signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
|
||||
signal shiftclk : std_logic;
|
||||
|
||||
begin
|
||||
--led <= not (inited);
|
||||
led <= not (bsy or not slavesel);
|
||||
bsy <= start_shifting or shifting2;
|
||||
|
||||
|
|
@ -171,29 +166,16 @@ begin
|
|||
clksrc <= phi0 when (ece = '0') else clk;
|
||||
|
||||
-- is a pulse signal to allow for divisor==0
|
||||
--shiftclk <= clksrc when divcnt = "000000" else '0';
|
||||
shiftclk <= clksrc when bsy = '1' else '0';
|
||||
|
||||
-- clkgen: process(nreset, divisor, clksrc)
|
||||
-- begin
|
||||
-- if (nreset = '0') then
|
||||
-- divcnt <= divisor;
|
||||
-- elsif (falling_edge(clksrc)) then
|
||||
-- if (shiftclk = '1') then
|
||||
-- divcnt <= divisor;
|
||||
-- else
|
||||
-- divcnt <= divcnt - 1;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
--------------------------
|
||||
-- interface section
|
||||
-- inputs
|
||||
int_miso <= (miso and not slavesel);
|
||||
|
||||
-- outputs
|
||||
nsel <= slavesel;
|
||||
nsel <= slavesel;
|
||||
pgm_en <= pgmen;
|
||||
|
||||
tc_proc: process (ndev_sel, shiftdone)
|
||||
begin
|
||||
|
|
@ -207,24 +189,22 @@ begin
|
|||
--------------------------
|
||||
-- cpu register section
|
||||
-- cpu read
|
||||
cpu_read: process(addr, spidatain, tc, bsy, frx,
|
||||
ece, divisor, slavesel, wp, card, sdhc, inited)
|
||||
cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen,
|
||||
ece, slavesel, wp, card, sdhc, inited)
|
||||
begin
|
||||
case addr is
|
||||
when "00" => -- read SPI data in
|
||||
data_out <= spidatain;
|
||||
when "01" => -- read status register
|
||||
data_out(0) <= '0';
|
||||
data_out(0) <= pgmen;
|
||||
data_out(1) <= '0';
|
||||
data_out(2) <= ece;
|
||||
data_out(3) <= '0';
|
||||
data_out(4) <= frx;
|
||||
data_out(5) <= bsy;
|
||||
data_out(6) <= '0';
|
||||
data_out(7) <= tc;
|
||||
when "10" => -- read sclk divisor
|
||||
data_out(DIV_WIDTH-1 downto 0) <= divisor;
|
||||
data_out(7 downto 3) <= (others => '0');
|
||||
data_out(7) <= tc;
|
||||
-- no register 2
|
||||
when "11" => -- read slave select / slave interrupt state
|
||||
data_out(0) <= slavesel;
|
||||
data_out(3 downto 1) <= (others => '0');
|
||||
|
|
@ -244,10 +224,10 @@ begin
|
|||
ece <= '0';
|
||||
frx <= '0';
|
||||
slavesel <= '1';
|
||||
divisor <= (others => '0');
|
||||
spidataout <= (others => '1');
|
||||
sdhc <= '0';
|
||||
inited <= '0';
|
||||
inited <= '0';
|
||||
pgmen <= '0';
|
||||
elsif (card = '1') then
|
||||
sdhc <= '0';
|
||||
inited <= '0';
|
||||
|
|
@ -255,13 +235,13 @@ begin
|
|||
case addr is
|
||||
when "00" => -- write SPI data out (see other process above)
|
||||
spidataout <= data_in;
|
||||
when "01" => -- write status register
|
||||
when "01" => -- write status register
|
||||
pgmen <= data_in(0);
|
||||
ece <= data_in(2);
|
||||
frx <= data_in(4);
|
||||
-- no bit 5 - 7
|
||||
when "10" => -- write divisor
|
||||
divisor <= data_in(DIV_WIDTH-1 downto 0);
|
||||
when "11" => -- write slave select / slave interrupt enable
|
||||
-- no bit 5 - 7
|
||||
-- no register 2
|
||||
when "11" => -- write slave select
|
||||
slavesel <= data_in(0);
|
||||
-- no bit 1 - 3
|
||||
sdhc <= data_in(4);
|
||||
|
|
@ -273,4 +253,3 @@ begin
|
|||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,42 +0,0 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "a10" LOC = "P38" ;
|
||||
NET "a8" LOC = "P36" ;
|
||||
NET "a9" LOC = "P37" ;
|
||||
NET "addr<0>" LOC = "P19" ;
|
||||
NET "addr<1>" LOC = "P18" ;
|
||||
NET "b10" LOC = "P22" ;
|
||||
NET "b8" LOC = "P26" ;
|
||||
NET "b9" LOC = "P27" ;
|
||||
NET "card" LOC = "P33" ;
|
||||
NET "data<0>" LOC = "P3" ;
|
||||
NET "data<1>" LOC = "P5" ;
|
||||
NET "data<2>" LOC = "P4" ;
|
||||
NET "data<3>" LOC = "P6" ;
|
||||
NET "data<4>" LOC = "P7" ;
|
||||
NET "data<5>" LOC = "P9" ;
|
||||
NET "data<6>" LOC = "P11" ;
|
||||
NET "data<7>" LOC = "P13" ;
|
||||
NET "extclk" LOC = "P42" ;
|
||||
NET "led" LOC = "P29" ;
|
||||
NET "ndev_sel" LOC = "P24" ;
|
||||
NET "ng" LOC = "P12" ;
|
||||
NET "nio_sel" LOC = "P14" ;
|
||||
NET "nio_stb" LOC = "P40" ;
|
||||
NET "nirq" LOC = "P2" ;
|
||||
NET "noe" LOC = "P25" ;
|
||||
NET "nphi2" LOC = "P44" ;
|
||||
NET "nreset" LOC = "P20" ;
|
||||
NET "nrw" LOC = "P1" ;
|
||||
NET "spi_miso" LOC = "P43" ;
|
||||
NET "spi_mosi" LOC = "P35" ;
|
||||
NET "spi_Nsel" LOC = "P28" ;
|
||||
NET "spi_sclk" LOC = "P34" ;
|
||||
NET "wp" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
Loading…
Reference in New Issue