Apple-2-HW/GR8RAM
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81 Commits 4 Branches 0 Tags 76 MiB
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Commit Graph

27 Commits

Author SHA1 Message Date
Zane Kaminski
debc1f02fe Release candidate? 2021-09-14 03:57:20 -04:00
Zane Kaminski
5437b524cc Register Apple address bus on PHI0 rising edge 2021-04-21 20:06:56 -04:00
Zane Kaminski
2ca22d3d54 Latch config DIP switches at boot 
Also rearranged GR8RAM.v
 2021-04-20 04:23:57 -04:00
Zane Kaminski
2f607d6d7c Works better? 2021-04-20 04:10:26 -04:00
Zane Kaminski
f09d92f480 Sorta works 2021-04-19 02:57:51 -04:00
Zane Kaminski
ed0821b322 Added CKE back 2021-04-18 20:24:58 -04:00
Zane Kaminski
bfd262def7 Sorta works 2021-04-18 06:01:08 -04:00
Zane Kaminski
4fd3d2ff3f Make apple boot 
Apple boots but SDRAM not working. Register R/W/increment works
 2021-04-18 03:54:45 -04:00
Zane Kaminski
d8a5dc069d idk 2021-04-11 15:39:19 -04:00
Zane Kaminski
fc2e875ac2 Works? 2021-04-03 03:44:42 -04:00
Zane Kaminski
763861e444 ugh 2021-03-19 16:38:48 -04:00
Zane Kaminski
e4bfc93b1f before remove UFM 2021-03-19 14:23:33 -04:00
Zane Kaminski
4defba0f50 better 2021-03-19 06:45:31 -04:00
Zane Kaminski
72851cefc5 ugh 2021-03-19 02:56:20 -04:00
Zane Kaminski
fdbc92725a Remove old CPLD stuff 2021-03-15 13:40:41 -04:00
Zane Kaminski
88a4169ab6 Fixed previous problem, working again 2020-02-16 00:11:12 -05:00
Zane Kaminski
3e06d30382 Fixed bugs in new PLD stuff 2019-10-20 22:41:24 -04:00
Zane Kaminski
79dd794f45 New PLD revision 
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
 2019-10-18 15:07:38 -04:00
Zane Kaminski
21f18c14db Recompiled just to be sure 2019-10-13 21:18:41 -04:00
Zane Kaminski
cf16763591 24-bit counter, CAS fixed 2019-10-11 20:34:51 -04:00
Zane Kaminski
2382fdfda6 Made AddrH high bit variable with mode input 2019-09-07 21:16:23 -04:00
Zane Kaminski
b0a001aa58 Clarified assignments 2019-09-06 17:26:42 -04:00
Zane Kaminski
47a4c012d7 Pipelined addition 2019-09-04 21:45:56 -04:00
Zane Kaminski
106df31f52 Trying again with RamFactor firmware 2019-09-02 20:56:37 -04:00
Zane Kaminski
a73cbf10ef Clarifications and bugfixes, will try again 2019-09-02 01:42:07 -04:00
Zane Kaminski
5b230c0966 1MB CPLD design seems to work, fails Apple BIST 2019-09-01 21:18:44 -04:00
Zane Kaminski
e78807ce85 CPLD firmware compiles 2019-08-31 22:55:04 -04:00