Finished SRAM design schematic

For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.

.gitignore

@@ -6,6 +6,7 @@
 *.bak
 *.bck
 *.kicad_pcb-bak
+*.sch-bak
 *~
 _autosave-*
 *.tmp
@@ -21,8 +22,4 @@ fp-info-cache
 *.dsn
 *.ses
 
-# Exported BOM files
-*.xml
-*.csv
-
 *.DS_Store

Documentation/Flash Map

@@ -0,0 +1,38 @@
+GR8RAM flash memory map
+
+....		-----------------------------
+7FFF		|							|
+....		|     firmware 3 (8 kB)     |
+6000		|							|
+			-----------------------------
+5FFF		|							|
+....		|     firmware 2 (8 kB)     |
+4000		|							|
+			-----------------------------
+3FFF		|							|
+....		|     firmware 1 (8 kB)     |
+2000		|							|
+			-----------------------------
+1FFF		|							|
+....		|     firmware 0 (8 kB)     |
+0000		|							|
+			-----------------------------
+
+Firmware area map (N=$0000, $2000, $4000, $6000)
+			-----------------------------
+N+1FFF		|							|
+....		|    IOSTRB bank 1 (2 kB)   |
+N+1800		|							|
+			-----------------------------
+N+17FF		|							|
+....		|    IOSEL bank 1 (2 kB)    |
+N+1000		|							|
+			-----------------------------
+N+0FFF		|							|
+....		|    IOSTRB bank 0 (2 kB)   |
+N+0800		|							|
+			-----------------------------
+N+07FF		|							|
+....		|    IOSEL bank 0 (2 kB)    |
+N+0000		|							|
+			-----------------------------

Documentation/Initialization Sequence

@@ -0,0 +1,139 @@
+Init sequence
+
+Init State			SDRAM				Flash					IS		Other
+--------------------------------------------------------------------------------
+$00000-$0FFBF		Nothing				Nothing					0
+$00000				NOP	CKE				/CS hi, CLK lo
+...
+$0FF90				NOP	CKE				/CS hi, CLK lo					InitActv <= ~BODf
+....
+$0FFA0				NOP	CKE				/CS lo, CLK lo
+...
+$0FFAF				NOP	CKE				/CS lo, CLK lo
+
+$0FFB0-$0FFBF		Init: Precharge		Send read cmd ($03)		1
+$0FFB0				NOP	CKE				CLK lo, MOSI 0 (b7)
+$0FFB1				NOP CKE				CLK hi
+$0FFB2				NOP	CKE				CLK lo, MOSI 0 (b6)
+$0FFB3				PC all				CLK hi
+$0FFB4				NOP	CKE				CLK lo, MOSI 0 (b5)
+$0FFB5				NOP	CKE				CLK hi
+$0FFB6				NOP	CKE				CLK lo, MOSI 0 (b4)
+$0FFB7				NOP	CKE				CLK hi
+$0FFB8				NOP	CKE				CLK lo, MOSI 0 (b3)
+$0FFB9				NOP	CKE				CLK hi
+$0FFBA				NOP	CKE				CLK lo, MOSI 0 (b2)
+$0FFBB				Load mode			CLK hi
+$0FFBC				NOP	CKE				CLK lo, MOSI 1 (b1)
+$0FFBD				NOP	CKE				CLK hi
+$0FFBE				NOP	CKE				CLK lo, MOSI 1 (b0)
+$0FFBF				NOP CKE				CLK hi
+
+$0FFC0-$0FFEF		Init: mode & ref	Send address ($000000)	2
+$0FFC0				NOP	CKE				CLK lo, MOSI 0 (b23)
+$0FFC1				NOP CKE				CLK hi
+$0FFC2				NOP	CKE				CLK lo, MOSI 0 (b22)
+$0FFC3				AREF				CLK hi
+$0FFC4				NOP	CKE				CLK lo, MOSI Firmware[1] (b21)
+$0FFC5				NOP	CKE				CLK hi
+$0FFC6				NOP	CKE				CLK lo, MOSI Firmware[0] (b20)
+$0FFC7				NOP	CKE				CLK hi
+$0FFC8				NOP	CKE				CLK lo, MOSI 0 (b19)
+$0FFC9				NOP	CKE				CLK hi
+$0FFCA				NOP	CKE				CLK lo, MOSI 0 (b18)
+$0FFCB				AREF				CLK hi
+$0FFCC				NOP CKE				CLK lo, MOSI 0 (b17)
+$0FFCD				NOP CKE				CLK hi
+$0FFCE				NOP	CKE				CLK lo, MOSI 0 (b16)
+$0FFCF				NOP CKE				CLK hi
+$0FFD0				NOP	CKE				CLK lo, MOSI 0 (b15)
+$0FFD1				NOP CKE				CLK hi
+$0FFD2				NOP	CKE				CLK lo, MOSI 0 (b14)
+$0FFD3				AREF				CLK hi
+$0FFD4				NOP	CKE				CLK lo, MOSI 0 (b13)
+$0FFD5				NOP	CKE				CLK hi
+$0FFD6				NOP	CKE				CLK lo, MOSI 0 (b12)
+$0FFD7				NOP	CKE				CLK hi
+$0FFD8				NOP	CKE				CLK lo, MOSI 0 (b11)
+$0FFD9				NOP	CKE				CLK hi
+$0FFDA				NOP	CKE				CLK lo, MOSI 0 (b10)
+$0FFDB				AREF				CLK hi
+$0FFDC				NOP CKE				CLK lo, MOSI 0 (b9)
+$0FFDD				NOP CKE				CLK hi
+$0FFDE				NOP	CKE				CLK lo, MOSI 0 (b8)
+$0FFDF				NOP CKE				CLK hi
+$0FFE0				NOP	CKE				CLK lo, MOSI 0 (b7)
+$0FFE1				NOP CKE				CLK hi
+$0FFE2				NOP	CKE				CLK lo, MOSI 0 (b6)
+$0FFE3				AREF				CLK hi
+$0FFE4				NOP	CKE				CLK lo, MOSI 0 (b5)
+$0FFE5				NOP	CKE				CLK hi
+$0FFE6				NOP	CKE				CLK lo, MOSI 0 (b4)
+$0FFE7				NOP	CKE				CLK hi
+$0FFE8				NOP	CKE				CLK lo, MOSI 0 (b3)
+$0FFE9				NOP	CKE				CLK hi
+$0FFEA				NOP	CKE				CLK lo, MOSI 0 (b2)
+$0FFEB				AREF				CLK hi
+$0FFEC				NOP CKE				CLK lo, MOSI 0 (b1)
+$0FFED				NOP CKE				CLK hi
+$0FFEE				NOP	CKE				CLK lo, MOSI 0 (b0)
+$0FFEF				NOP CKE				CLK hi
+
+$0FFF0-$0FFFF		Init: mode & ref	8 dummy clocks			2
+$0FFF0				NOP	CKE				CLK lo, MOSIOE 0
+$0FFF1				NOP CKE				CLK hi
+$0FFF2				NOP	CKE				CLK lo
+$0FFF3				AREF				CLK hi
+$0FFF4				NOP CKE				CLK lo
+$0FFF5				NOP	CKE				CLK hi
+$0FFF6				NOP	CKE				CLK lo
+$0FFF7				NOP	CKE				CLK hi
+$0FFF8				NOP	CKE				CLK lo
+$0FFF9				NOP	CKE				CLK hi
+$0FFFA				NOP	CKE				CLK lo
+$0FFFB				AREF				CLK hi
+$0FFFC				NOP CKE				CLK lo
+$0FFFD				NOP CKE				CLK hi
+$0FFFE				NOP	CKE				CLK lo
+$0FFFF				NOP CKE				CLK hi
+
+$10000-$2FFFF		Write ROM data		Shift in read data		3
+$10000				NOP CKE				CLK lo
+$10001				NOP CKE				CLK hi, get b7:6 of $000000
+$10002				NOP CKE				CLK lo
+$10003				AREF				CLK hi, get b5:4 of $000000
+$10004				NOP CKE				CLK lo
+$10005				ACT					CLK hi, get b3:2 of $000000
+$10006				NOP CKE				CLK lo
+$10007				WR AP				CLK hi, get b1:0 of $000000
+$10008				NOP CKE				CLK lo
+$10009				NOP CKE				CLK hi, get b7:6 of $000001
+$1000A				NOP CKE				CLK lo
+$1000B				AREF				CLK hi, get b5:4 of $000001
+$1000C				NOP CKE				CLK lo
+$1000D				ACT					CLK hi, get b3:2 of $000001
+$1000E				NOP CKE				CLK lo
+$1000F				WR AP				CLK hi, get b1:0 of $000001
+...
+$2FFF0				NOP CKE				CLK lo
+$2FFF1				NOP CKE				CLK hi, get b7:6 of $003FFE
+$2FFF2				NOP CKE				CLK lo
+$2FFF3				AREF				CLK hi, get b5:4 of $003FFE
+$2FFF4				NOP CKE				CLK lo
+$2FFF5				ACT					CLK hi, get b3:2 of $003FFE
+$2FFF6				NOP CKE				CLK lo
+$2FFF7				WR AP				CLK hi, get b1:0 of $003FFE
+$2FFF8				NOP CKE				CLK lo
+$2FFF9				NOP CKE				CLK hi, get b7:6 of $003FFF
+$2FFFA				NOP CKE				CLK lo
+$2FFFB				AREF				CLK hi, get b5:4 of $003FFF
+$2FFFC				NOP CKE				CLK lo
+$2FFFD				ACT					CLK hi, get b3:2 of $003FFF
+$2FFFE				NOP CKE				CLK lo
+$2FFFF				WR AP				CLK hi, get b1:0 of $003FFF
+
+$30000				NOP CKE				CLK lo, /CS hi			3
+$30001				NOP CKE				CLK lo, /CS hi			3
+$30002				NOP CKE				CLK lo, /CS hi			3		SDRAMActv <= InitActv && ~InitInterrupted
+
+

Documentation/RAM Map

@@ -0,0 +1,64 @@
+GR8RAM/LibraryCard Slinky RAM memory map
+			-----------------------------
+1 FF FFFF	|							|
+. .. ....	| LibCrd sect. cache (8 MB) |
+1 80 0000	|							|
+			-----------------------------
+1 7F FFFF	|							|
+. .. ....	|  LibCrd registers (1 MB)  |
+1 70 0000	|							|
+			-----------------------------
+1 6F FFFF	|							|
+. .. ....	|    reserved (5.9375 MB)   |
+1 11 0000	|							|
+			-----------------------------
+1 10 FFFF	|							|
+. .. ....	|     RAM shadow (64 kB)    |
+1 10 0000	|							|
+			-----------------------------
+1 0F FFFF	|							|
+. .. ....	|      firmware (1 MB)      |
+1 00 0000	|							|
+			-----------------------------
+0 FF FFFF	|							|
+. .. ....	|   RAMFactor RAM (16 MB)   |
+0 00 0000	|							|
+			-----------------------------
+
+Firmware area map (X == 0, 1, 2, or 3)
+			-----------------------------
+1 0F FFFF	|							|
+. .. ....	|     reserved (510 kB)     |
+1 08 0800	|							|
+			-----------------------------
+1 08 07FF	|							|
+. .. ....	|     IOSEL area (2 kB)     |
+1 08 0000	|							|
+			-----------------------------
+1 07 FFFF	|							|
+. .. ....	| 256x IOSTRB area (512 kB) |
+1 00 0000	|							|
+			-----------------------------
+
+Library Card register space
+			-----------------------------
+1 7F FFFF	|							|
+. .. ....	|     reserved (768 kB)     |
+1 74 0000	|							|
+			-----------------------------
+1 73 FFFF	|							|
+. .. ....	|    response B (64 kB)     |
+1 73 0000	|							|
+			-----------------------------
+1 72 FFFF	|							|
+. .. ....	|     command B (64 kB)     |
+1 72 0000	|							|
+			-----------------------------
+1 71 FFFF	|							|
+. .. ....	|    response A (64 kB)     |
+1 71 0000	|							|
+			-----------------------------
+1 70 FFFF	|							|
+. .. ....	|     command A (64 kB)     |
+1 70 0000	|							|
+			-----------------------------

Flip.sch

@@ -0,0 +1,16 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr B 17000 11000
+encoding utf-8
+Sheet 3 3
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$EndSCHEMATC

GR8RAM-cache.lib

@@ -1,38 +1,286 @@
 EESchema-LIBRARY Version 2.4
 #encoding utf-8
 #
-# Connector_AVR-JTAG-10
+# 74xx_74LS04
 #
-DEF Connector_AVR-JTAG-10 J 0 40 Y Y 1 F N
-F0 "J" 175 500 50 H V L CNN
-F1 "Connector_AVR-JTAG-10" 100 -500 50 H V L CNN
-F2 "" -150 150 50 V I C CNN
-F3 "" -1275 -550 50 H I C CNN
+DEF 74xx_74LS04 U 0 20 Y Y 7 L N
+F0 "U" 0 50 50 H V C CNN
+F1 "74xx_74LS04" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS 74HC04 74HCT04 74AHC04 74AHCT04
 $FPLIST
- IDC?Header*2x05*
- Pin?Header*2x05*
+ DIP*W7.62mm*
+ SSOP?14*
+ TSSOP?14*
 $ENDFPLIST
 DRAW
-S -105 450 -95 420 0 1 0 N
-S -5 -420 5 -450 0 1 0 N
-S -5 450 5 420 0 1 0 N
-S 350 -195 320 -205 0 1 0 N
-S 350 -95 320 -105 0 1 0 N
-S 350 5 320 -5 0 1 0 N
-S 350 105 320 95 0 1 0 N
-S 350 205 320 195 0 1 0 N
-S 350 305 320 295 0 1 0 N
-S 350 450 -350 -450 0 1 10 f
-X TCK 1 500 100 150 L 50 50 1 1 P
-X GND 10 0 -600 150 U 50 50 1 1 W
-X GND 2 0 -600 150 U 50 50 1 1 P N
-X TDO 3 500 -100 150 L 50 50 1 1 P
-X VREF 4 -100 600 150 D 50 50 1 1 P
-X TMS 5 500 0 150 L 50 50 1 1 P
-X ~SRST 6 500 300 150 L 50 50 1 1 P
-X VCC 7 0 600 150 D 50 50 1 1 W
-X ~TRST 8 500 200 150 L 50 50 1 1 P
-X TDI 9 500 -200 150 L 50 50 1 1 P
+S -200 300 200 -300 7 1 10 f
+P 4 1 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 2 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 3 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 4 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 5 0 10 -150 150 -150 -150 150 0 -150 150 f
+P 4 6 0 10 -150 150 -150 -150 150 0 -150 150 f
+X ~ 1 -300 0 150 R 50 50 1 0 I
+X ~ 2 300 0 150 L 50 50 1 0 O I
+X ~ 3 -300 0 150 R 50 50 2 0 I
+X ~ 4 300 0 150 L 50 50 2 0 O I
+X ~ 5 -300 0 150 R 50 50 3 0 I
+X ~ 6 300 0 150 L 50 50 3 0 O I
+X ~ 8 300 0 150 L 50 50 4 0 O I
+X ~ 9 -300 0 150 R 50 50 4 0 I
+X ~ 10 300 0 150 L 50 50 5 0 O I
+X ~ 11 -300 0 150 R 50 50 5 0 I
+X ~ 12 300 0 150 L 50 50 6 0 O I
+X ~ 13 -300 0 150 R 50 50 6 0 I
+X VCC 14 0 500 200 D 50 50 7 0 W
+X GND 7 0 -500 200 U 50 50 7 0 W
+ENDDRAW
+ENDDEF
+#
+# 74xx_74LS08
+#
+DEF 74xx_74LS08 U 0 40 Y Y 5 L N
+F0 "U" 0 50 50 H V C CNN
+F1 "74xx_74LS08" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS 74LS09
+$FPLIST
+ DIP*W7.62mm*
+$ENDFPLIST
+DRAW
+A 0 0 150 -899 899 1 1 10 f 0 -150 0 150
+A 0 0 150 -899 899 2 1 10 f 0 -150 0 150
+A 0 0 150 -899 899 3 1 10 f 0 -150 0 150
+A 0 0 150 -899 899 4 1 10 f 0 -150 0 150
+A -360 0 258 354 -354 1 2 10 N -150 150 -150 -150
+A -47 -52 204 150 837 1 2 10 f 150 0 -24 150
+A -47 52 204 -150 -837 1 2 10 f 150 0 -24 -150
+A -360 0 258 354 -354 2 2 10 N -150 150 -150 -150
+A -47 -52 204 150 837 2 2 10 f 150 0 -24 150
+A -47 52 204 -150 -837 2 2 10 f 150 0 -24 -150
+A -360 0 258 354 -354 3 2 10 N -150 150 -150 -150
+A -47 -52 204 150 837 3 2 10 f 150 0 -24 150
+A -47 52 204 -150 -837 3 2 10 f 150 0 -24 -150
+A -360 0 258 354 -354 4 2 10 N -150 150 -150 -150
+A -47 -52 204 150 837 4 2 10 f 150 0 -24 150
+A -47 52 204 -150 -837 4 2 10 f 150 0 -24 -150
+S -200 300 200 -300 5 1 10 f
+P 4 1 1 10 0 150 -150 150 -150 -150 0 -150 f
+P 4 2 1 10 0 150 -150 150 -150 -150 0 -150 f
+P 4 3 1 10 0 150 -150 150 -150 -150 0 -150 f
+P 4 4 1 10 0 150 -150 150 -150 -150 0 -150 f
+P 2 1 2 10 -150 -150 -25 -150 f
+P 2 1 2 10 -150 150 -25 150 f
+P 12 1 2 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 2 2 10 -150 -150 -25 -150 f
+P 2 2 2 10 -150 150 -25 150 f
+P 12 2 2 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 3 2 10 -150 -150 -25 -150 f
+P 2 3 2 10 -150 150 -25 150 f
+P 12 3 2 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 4 2 10 -150 -150 -25 -150 f
+P 2 4 2 10 -150 150 -25 150 f
+P 12 4 2 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+X VCC 14 0 500 200 D 50 50 5 0 W
+X GND 7 0 -500 200 U 50 50 5 0 W
+X ~ 1 -300 100 150 R 50 50 1 1 I
+X ~ 2 -300 -100 150 R 50 50 1 1 I
+X ~ 3 300 0 150 L 50 50 1 1 O
+X ~ 4 -300 100 150 R 50 50 2 1 I
+X ~ 5 -300 -100 150 R 50 50 2 1 I
+X ~ 6 300 0 150 L 50 50 2 1 O
+X ~ 10 -300 -100 150 R 50 50 3 1 I
+X ~ 8 300 0 150 L 50 50 3 1 O
+X ~ 9 -300 100 150 R 50 50 3 1 I
+X ~ 11 300 0 150 L 50 50 4 1 O
+X ~ 12 -300 100 150 R 50 50 4 1 I
+X ~ 13 -300 -100 150 R 50 50 4 1 I
+X ~ 1 -300 100 170 R 50 50 1 2 I I
+X ~ 2 -300 -100 170 R 50 50 1 2 I I
+X ~ 3 300 0 150 L 50 50 1 2 O I
+X ~ 4 -300 100 170 R 50 50 2 2 I I
+X ~ 5 -300 -100 170 R 50 50 2 2 I I
+X ~ 6 300 0 150 L 50 50 2 2 O I
+X ~ 10 -300 -100 170 R 50 50 3 2 I I
+X ~ 8 300 0 150 L 50 50 3 2 O I
+X ~ 9 -300 100 170 R 50 50 3 2 I I
+X ~ 11 300 0 150 L 50 50 4 2 O I
+X ~ 12 -300 100 170 R 50 50 4 2 I I
+X ~ 13 -300 -100 170 R 50 50 4 2 I I
+ENDDRAW
+ENDDEF
+#
+# 74xx_74LS32
+#
+DEF 74xx_74LS32 U 0 40 Y Y 5 L N
+F0 "U" 0 50 50 H V C CNN
+F1 "74xx_74LS32" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP?14*
+$ENDFPLIST
+DRAW
+A -360 0 258 354 -354 1 1 10 N -150 150 -150 -150
+A -47 -52 204 150 837 1 1 10 f 150 0 -24 150
+A -47 52 204 -150 -837 1 1 10 f 150 0 -24 -150
+A -360 0 258 354 -354 2 1 10 N -150 150 -150 -150
+A -47 -52 204 150 837 2 1 10 f 150 0 -24 150
+A -47 52 204 -150 -837 2 1 10 f 150 0 -24 -150
+A -360 0 258 354 -354 3 1 10 N -150 150 -150 -150
+A -47 -52 204 150 837 3 1 10 f 150 0 -24 150
+A -47 52 204 -150 -837 3 1 10 f 150 0 -24 -150
+A -360 0 258 354 -354 4 1 10 N -150 150 -150 -150
+A -47 -52 204 150 837 4 1 10 f 150 0 -24 150
+A -47 52 204 -150 -837 4 1 10 f 150 0 -24 -150
+A 0 0 150 -899 899 1 2 10 f 0 -150 0 150
+A 0 0 150 -899 899 2 2 10 f 0 -150 0 150
+A 0 0 150 -899 899 3 2 10 f 0 -150 0 150
+A 0 0 150 -899 899 4 2 10 f 0 -150 0 150
+S -200 300 200 -300 5 1 10 f
+P 2 1 1 10 -150 -150 -25 -150 f
+P 2 1 1 10 -150 150 -25 150 f
+P 12 1 1 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 2 1 10 -150 -150 -25 -150 f
+P 2 2 1 10 -150 150 -25 150 f
+P 12 2 1 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 3 1 10 -150 -150 -25 -150 f
+P 2 3 1 10 -150 150 -25 150 f
+P 12 3 1 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 4 1 10 -150 -150 -25 -150 f
+P 2 4 1 10 -150 150 -25 150 f
+P 12 4 1 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 4 1 2 10 0 150 -150 150 -150 -150 0 -150 f
+P 4 2 2 10 0 150 -150 150 -150 -150 0 -150 f
+P 4 3 2 10 0 150 -150 150 -150 -150 0 -150 f
+P 4 4 2 10 0 150 -150 150 -150 -150 0 -150 f
+X VCC 14 0 500 200 D 50 50 5 0 W
+X GND 7 0 -500 200 U 50 50 5 0 W
+X ~ 1 -300 100 170 R 50 50 1 1 I
+X ~ 2 -300 -100 170 R 50 50 1 1 I
+X ~ 3 300 0 150 L 50 50 1 1 O
+X ~ 4 -300 100 170 R 50 50 2 1 I
+X ~ 5 -300 -100 170 R 50 50 2 1 I
+X ~ 6 300 0 150 L 50 50 2 1 O
+X ~ 10 -300 -100 170 R 50 50 3 1 I
+X ~ 8 300 0 150 L 50 50 3 1 O
+X ~ 9 -300 100 170 R 50 50 3 1 I
+X ~ 11 300 0 150 L 50 50 4 1 O
+X ~ 12 -300 100 170 R 50 50 4 1 I
+X ~ 13 -300 -100 170 R 50 50 4 1 I
+X ~ 1 -300 100 150 R 50 50 1 2 I I
+X ~ 2 -300 -100 150 R 50 50 1 2 I I
+X ~ 3 300 0 150 L 50 50 1 2 O I
+X ~ 4 -300 100 150 R 50 50 2 2 I I
+X ~ 5 -300 -100 150 R 50 50 2 2 I I
+X ~ 6 300 0 150 L 50 50 2 2 O I
+X ~ 10 -300 -100 150 R 50 50 3 2 I I
+X ~ 8 300 0 150 L 50 50 3 2 O I
+X ~ 9 -300 100 150 R 50 50 3 2 I I
+X ~ 11 300 0 150 L 50 50 4 2 O I
+X ~ 12 -300 100 150 R 50 50 4 2 I I
+X ~ 13 -300 -100 150 R 50 50 4 2 I I
+ENDDRAW
+ENDDEF
+#
+# 74xx_74LS74
+#
+DEF 74xx_74LS74 U 0 40 Y Y 3 L N
+F0 "U" -300 350 50 H V C CNN
+F1 "74xx_74LS74" -300 -350 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS 74HC74
+$FPLIST
+ DIP*W7.62mm*
+$ENDFPLIST
+DRAW
+S -200 200 200 -200 1 1 10 f
+S -200 200 200 -200 2 1 10 f
+S -200 300 200 -300 3 1 10 f
+X ~R 1 0 -300 100 U 50 50 1 0 I
+X D 2 -300 100 100 R 50 50 1 0 I
+X C 3 -300 0 100 R 50 50 1 0 I C
+X ~S 4 0 300 100 D 50 50 1 0 I
+X Q 5 300 100 100 L 50 50 1 0 O
+X ~Q 6 300 -100 100 L 50 50 1 0 O
+X ~S 10 0 300 100 D 50 50 2 0 I
+X C 11 -300 0 100 R 50 50 2 0 I C
+X D 12 -300 100 100 R 50 50 2 0 I
+X ~R 13 0 -300 100 U 50 50 2 0 I
+X ~Q 8 300 -100 100 L 50 50 2 0 O
+X Q 9 300 100 100 L 50 50 2 0 O
+X VCC 14 0 400 100 D 50 50 3 0 W
+X GND 7 0 -400 100 U 50 50 3 0 W
+ENDDRAW
+ENDDEF
+#
+# 74xx_74LS86
+#
+DEF 74xx_74LS86 U 0 40 Y Y 5 L N
+F0 "U" 0 50 50 H V C CNN
+F1 "74xx_74LS86" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS 74HC86
+$FPLIST
+ DIP*W7.62mm*
+$ENDFPLIST
+DRAW
+A -385 0 258 354 -354 1 0 10 N -174 150 -174 -150
+A -360 0 258 354 -354 1 0 10 N -150 150 -150 -150
+A -47 -52 204 150 837 1 0 10 f 150 0 -24 150
+A -47 52 204 -150 -837 1 0 10 f 150 0 -24 -150
+A -385 0 258 354 -354 2 0 10 N -174 150 -174 -150
+A -360 0 258 354 -354 2 0 10 N -150 150 -150 -150
+A -47 -52 204 150 837 2 0 10 f 150 0 -24 150
+A -47 52 204 -150 -837 2 0 10 f 150 0 -24 -150
+A -385 0 258 354 -354 3 0 10 N -174 150 -174 -150
+A -360 0 258 354 -354 3 0 10 N -150 150 -150 -150
+A -47 -52 204 150 837 3 0 10 f 150 0 -24 150
+A -47 52 204 -150 -837 3 0 10 f 150 0 -24 -150
+A -385 0 258 354 -354 4 0 10 N -174 150 -174 -150
+A -360 0 258 354 -354 4 0 10 N -150 150 -150 -150
+A -47 -52 204 150 837 4 0 10 f 150 0 -24 150
+A -47 52 204 -150 -837 4 0 10 f 150 0 -24 -150
+S -200 300 200 -300 5 1 10 f
+P 2 1 0 10 -150 -150 -25 -150 f
+P 2 1 0 10 -150 150 -25 150 f
+P 12 1 0 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 2 0 10 -150 -150 -25 -150 f
+P 2 2 0 10 -150 150 -25 150 f
+P 12 2 0 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 3 0 10 -150 -150 -25 -150 f
+P 2 3 0 10 -150 150 -25 150 f
+P 12 3 0 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 4 0 10 -150 -150 -25 -150 f
+P 2 4 0 10 -150 150 -25 150 f
+P 12 4 0 -1000 -25 150 -150 150 -150 150 -140 134 -119 89 -106 41 -103 -10 -109 -59 -125 -107 -150 -150 -150 -150 -25 -150 f
+P 2 1 1 6 -150 -100 -125 -100 N
+P 2 1 1 6 -150 100 -125 100 N
+P 2 2 1 6 -150 -100 -125 -100 N
+P 2 2 1 6 -150 100 -125 100 N
+P 2 3 1 6 -150 -100 -125 -100 N
+P 2 3 1 6 -150 100 -125 100 N
+P 2 4 1 6 -150 -100 -125 -100 N
+P 2 4 1 6 -150 100 -125 100 N
+X ~ 1 -300 100 175 R 50 50 1 0 I
+X ~ 2 -300 -100 175 R 50 50 1 0 I
+X ~ 3 300 0 150 L 50 50 1 0 O
+X ~ 4 -300 100 175 R 50 50 2 0 I
+X ~ 5 -300 -100 175 R 50 50 2 0 I
+X ~ 6 300 0 150 L 50 50 2 0 O
+X ~ 10 -300 -100 175 R 50 50 3 0 I
+X ~ 8 300 0 150 L 50 50 3 0 O
+X ~ 9 -300 100 175 R 50 50 3 0 I
+X ~ 11 300 0 150 L 50 50 4 0 O
+X ~ 12 -300 100 175 R 50 50 4 0 I
+X ~ 13 -300 -100 175 R 50 50 4 0 I
+X VCC 14 0 500 200 D 50 50 5 0 W
+X GND 7 0 -500 200 U 50 50 5 0 W
 ENDDRAW
 ENDDEF
 #
@@ -151,23 +399,22 @@ X Pin_9 9 -200 400 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Device_CP_Small
+# Device_Battery_Cell
 #
-DEF Device_CP_Small C 0 10 N N 1 F N
-F0 "C" 10 70 50 H V L CNN
-F1 "Device_CP_Small" 10 -80 50 H V L CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- CP_*
-$ENDFPLIST
+DEF Device_Battery_Cell BT 0 0 N N 1 F N
+F0 "BT" 100 100 50 H V L CNN
+F1 "Device_Battery_Cell" 100 0 50 H V L CNN
+F2 "" 0 60 50 V I C CNN
+F3 "" 0 60 50 V I C CNN
 DRAW
-S -60 -12 60 -27 0 1 0 F
-S -60 27 60 12 0 1 0 N
-P 2 0 1 0 -50 60 -30 60 N
-P 2 0 1 0 -40 50 -40 70 N
-X ~ 1 0 100 73 D 50 50 1 1 P
-X ~ 2 0 -100 73 U 50 50 1 1 P
+S -90 70 90 60 0 1 0 F
+S -62 47 58 27 0 1 0 F
+P 2 0 1 0 0 30 0 0 N
+P 2 0 1 0 0 70 0 100 N
+P 2 0 1 10 20 135 60 135 N
+P 2 0 1 10 40 155 40 115 N
+X + 1 0 200 100 D 50 50 1 1 P
+X - 2 0 -100 100 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
@@ -189,6 +436,250 @@ X ~ 2 0 -100 80 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# Device_D_Schottky_Small_ALT
+#
+DEF Device_D_Schottky_Small_ALT D 0 10 N N 1 F N
+F0 "D" -50 80 50 H V L CNN
+F1 "Device_D_Schottky_Small_ALT" -280 -80 50 H V L CNN
+F2 "" 0 0 50 V I C CNN
+F3 "" 0 0 50 V I C CNN
+$FPLIST
+ TO-???*
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+P 2 0 1 0 -30 -40 -30 40 N
+P 2 0 1 0 -30 0 30 0 N
+P 3 0 1 0 -30 -40 -20 -40 -20 -30 N
+P 3 0 1 0 -30 40 -40 40 -40 30 N
+P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
+X K 1 -100 0 70 R 50 50 1 1 P
+X A 2 100 0 70 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R_Small
+#
+DEF Device_R_Small R 0 10 N N 1 F N
+F0 "R" 30 20 50 H V L CNN
+F1 "Device_R_Small" 30 -40 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -30 70 30 -70 0 1 8 N
+X ~ 1 0 100 30 D 50 50 1 1 P
+X ~ 2 0 -100 30 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_74138
+#
+DEF GW_Logic_74138 U 0 40 Y Y 1 F N
+F0 "U" 0 500 50 H V C CNN
+F1 "GW_Logic_74138" 0 -500 50 H V C CNN
+F2 "" 0 -650 50 H I C TNN
+F3 "" 0 100 60 H I C CNN
+DRAW
+S -200 450 200 -450 0 1 10 f
+X A0 1 -400 250 200 R 50 50 1 1 I
+X ~Q5~ 10 400 -150 200 L 50 50 1 1 I
+X ~Q4~ 11 400 -50 200 L 50 50 1 1 I
+X ~Q3~ 12 400 50 200 L 50 50 1 1 I
+X ~Q2~ 13 400 150 200 L 50 50 1 1 I
+X ~Q1~ 14 400 250 200 L 50 50 1 1 I
+X ~Q0~ 15 400 350 200 L 50 50 1 1 I
+X Vcc 16 -400 350 200 R 50 50 1 1 W
+X A1 2 -400 150 200 R 50 50 1 1 I
+X A2 3 -400 50 200 R 50 50 1 1 I
+X ~E1~ 4 -400 -250 200 R 50 50 1 1 I
+X ~E2~ 5 -400 -150 200 R 50 50 1 1 I
+X E3 6 -400 -50 200 R 50 50 1 1 I
+X ~Q7~ 7 400 -350 200 L 50 50 1 1 I
+X GND 8 -400 -350 200 R 50 50 1 1 W
+X ~Q6~ 9 400 -250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_74245
+#
+DEF GW_Logic_74245 U 0 40 Y Y 1 F N
+F0 "U" 0 600 50 H V C CNN
+F1 "GW_Logic_74245" 0 -600 50 H V C CNN
+F2 "" 0 -650 50 H I C TNN
+F3 "" 0 100 60 H I C CNN
+DRAW
+S -200 550 200 -550 0 1 10 f
+X AtoB 1 -400 450 200 R 50 50 1 1 I
+X GND 10 -400 -450 200 R 50 50 1 1 W
+X B7 11 400 -450 200 L 50 50 1 1 B
+X B6 12 400 -350 200 L 50 50 1 1 B
+X B5 13 400 -250 200 L 50 50 1 1 B
+X B4 14 400 -150 200 L 50 50 1 1 B
+X B3 15 400 -50 200 L 50 50 1 1 B
+X B2 16 400 50 200 L 50 50 1 1 B
+X B1 17 400 150 200 L 50 50 1 1 B
+X B0 18 400 250 200 L 50 50 1 1 B
+X ~OE~ 19 400 350 200 L 50 50 1 1 I
+X A0 2 -400 350 200 R 50 50 1 1 B
+X Vcc 20 400 450 200 L 50 50 1 1 W
+X A1 3 -400 250 200 R 50 50 1 1 B
+X A2 4 -400 150 200 R 50 50 1 1 B
+X A3 5 -400 50 200 R 50 50 1 1 B
+X A4 6 -400 -50 200 R 50 50 1 1 B
+X A5 7 -400 -150 200 R 50 50 1 1 B
+X A6 8 -400 -250 200 R 50 50 1 1 B
+X A7 9 -400 -350 200 R 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_74257
+#
+DEF GW_Logic_74257 U 0 40 Y Y 1 L N
+F0 "U" -300 500 50 H V C CNN
+F1 "GW_Logic_74257" 0 0 50 V V C CNN
+F2 "" 0 -250 50 H I C CNN
+F3 "" 0 -250 50 H I C CNN
+$FPLIST
+ DIP?16*
+$ENDFPLIST
+DRAW
+S -200 450 200 -450 1 1 10 f
+X S 1 400 -150 200 L 50 50 1 0 I
+X C1 10 -400 -150 200 R 50 50 1 0 I
+X C0 11 -400 -50 200 R 50 50 1 0 I
+X Zd 12 400 -50 200 L 50 50 1 0 O
+X D1 13 -400 -350 200 R 50 50 1 0 I
+X D0 14 -400 -250 200 R 50 50 1 0 I
+X ~OE~ 15 400 -250 200 L 50 50 1 0 I I
+X VCC 16 400 350 200 L 50 50 1 0 W
+X A0 2 -400 350 200 R 50 50 1 0 I
+X A1 3 -400 250 200 R 50 50 1 0 I
+X Za 4 400 250 200 L 50 50 1 0 O
+X B0 5 -400 150 200 R 50 50 1 0 I
+X B1 6 -400 50 200 R 50 50 1 0 I
+X Zb 7 400 150 200 L 50 50 1 0 O
+X GND 8 400 -350 200 L 50 50 1 0 W
+X Zc 9 400 50 200 L 50 50 1 0 O
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_74273
+#
+DEF GW_Logic_74273 U 0 20 Y Y 1 F N
+F0 "U" 0 600 50 H V C CNN
+F1 "GW_Logic_74273" 0 0 50 V V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+ALIAS 74HC273 74HCT273 74AHC273 74AHCT273
+$FPLIST
+ DIP?20*
+ SO?20*
+ SOIC?20*
+$ENDFPLIST
+DRAW
+S -200 550 200 -550 1 1 10 f
+X ~Mr 1 -400 -450 200 R 50 50 1 0 I I
+X GND 10 400 -450 200 L 50 50 1 0 W
+X Cp 11 -400 -350 200 R 50 50 1 0 I C
+X Q4 12 400 -50 200 L 50 50 1 0 O
+X D4 13 -400 50 200 R 50 50 1 0 I
+X D5 14 -400 -50 200 R 50 50 1 0 I
+X Q5 15 400 -150 200 L 50 50 1 0 O
+X Q6 16 400 -250 200 L 50 50 1 0 O
+X D6 17 -400 -150 200 R 50 50 1 0 I
+X D7 18 -400 -250 200 R 50 50 1 0 I
+X Q7 19 400 -350 200 L 50 50 1 0 O
+X Q0 2 400 350 200 L 50 50 1 0 O
+X VCC 20 400 450 200 L 50 50 1 0 W
+X D0 3 -400 450 200 R 50 50 1 0 I
+X D1 4 -400 350 200 R 50 50 1 0 I
+X Q1 5 400 250 200 L 50 50 1 0 O
+X Q2 6 400 150 200 L 50 50 1 0 O
+X D2 7 -400 250 200 R 50 50 1 0 I
+X D3 8 -400 150 200 R 50 50 1 0 I
+X Q3 9 400 50 200 L 50 50 1 0 O
+ENDDRAW
+ENDDEF
+#
+# GW_RAM_SRAM-512Kx16-TSOP2-44
+#
+DEF GW_RAM_SRAM-512Kx16-TSOP2-44 U 0 20 Y Y 1 F N
+F0 "U" 0 1200 50 H V C CNN
+F1 "GW_RAM_SRAM-512Kx16-TSOP2-44" 0 50 50 V V C CNN
+F2 "stdpads:TSOP-II-44_400mil_P0.8mm" 0 -1200 50 H I C CNN
+F3 "" 0 -150 50 H I C CNN
+$FPLIST
+ SOJ*10.16x23.49mm*P1.27mm*
+$ENDFPLIST
+DRAW
+S -300 1150 300 -1150 0 1 10 f
+X A4 1 -400 550 100 R 50 50 1 1 I
+X D3 10 400 750 100 L 50 50 1 1 B
+X VDD 11 -400 1050 100 R 50 50 1 1 W
+X GND 12 -400 -1050 100 R 50 50 1 1 P N
+X D4 13 400 650 100 L 50 50 1 1 B
+X D5 14 400 550 100 L 50 50 1 1 B
+X D6 15 400 450 100 L 50 50 1 1 B
+X D7 16 400 350 100 L 50 50 1 1 B
+X ~WE~ 17 400 -950 100 L 50 50 1 1 I
+X A16 18 -400 -650 100 R 50 50 1 1 I
+X A15 19 -400 -550 100 R 50 50 1 1 I
+X A3 2 -400 650 100 R 50 50 1 1 I
+X A14 20 -400 -450 100 R 50 50 1 1 I
+X A13 21 -400 -350 100 R 50 50 1 1 I
+X A12 22 -400 -250 100 R 50 50 1 1 I
+X A17 23 -400 -750 100 R 50 50 1 1 I
+X A11 24 -400 -150 100 R 50 50 1 1 I
+X A10 25 -400 -50 100 R 50 50 1 1 I
+X A9 26 -400 50 100 R 50 50 1 1 I
+X A8 27 -400 150 100 R 50 50 1 1 I
+X A18 28 -400 -850 100 R 50 50 1 1 I
+X D8 29 400 250 100 L 50 50 1 1 B
+X A2 3 -400 750 100 R 50 50 1 1 I
+X D9 30 400 150 100 L 50 50 1 1 B
+X D10 31 400 50 100 L 50 50 1 1 B
+X D11 32 400 -50 100 L 50 50 1 1 B
+X VDD 33 -400 1050 100 R 50 50 1 1 W N
+X GND 34 -400 -1050 100 R 50 50 1 1 W
+X D12 35 400 -150 100 L 50 50 1 1 B
+X D13 36 400 -250 100 L 50 50 1 1 B
+X D14 37 400 -350 100 L 50 50 1 1 B
+X D15 38 400 -450 100 L 50 50 1 1 B
+X ~LB~ 39 400 -850 100 L 50 50 1 1 I
+X A1 4 -400 850 100 R 50 50 1 1 I
+X ~UB~ 40 400 -750 100 L 50 50 1 1 I
+X ~OE~ 41 400 -1050 100 L 50 50 1 1 I
+X A7 42 -400 250 100 R 50 50 1 1 I
+X A6 43 -400 350 100 R 50 50 1 1 I
+X A5 44 -400 450 100 R 50 50 1 1 I
+X A0 5 -400 950 100 R 50 50 1 1 I
+X ~CE~ 6 400 -650 100 L 50 50 1 1 I
+X D0 7 400 1050 100 L 50 50 1 1 B
+X D1 8 400 950 100 L 50 50 1 1 B
+X D2 9 400 850 100 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# Mechanical_Fiducial
+#
+DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
+F0 "FID" 0 200 50 H V C CNN
+F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Fiducial*
+$ENDFPLIST
+DRAW
+C 0 0 50 0 1 20 f
+ENDDRAW
+ENDDEF
+#
 # Mechanical_MountingHole
 #
 DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
@@ -220,6 +711,29 @@ X 1 1 0 -100 100 U 50 50 1 1 I
 ENDDRAW
 ENDDEF
 #
+# Transistor_BJT_MMBT3904
+#
+DEF Transistor_BJT_MMBT3904 Q 0 0 Y N 1 F N
+F0 "Q" 200 75 50 H V L CNN
+F1 "Transistor_BJT_MMBT3904" 200 0 50 H V L CNN
+F2 "Package_TO_SOT_SMD:SOT-23" 200 -75 50 H I L CIN
+F3 "" 0 0 50 H I L CNN
+ALIAS BC818 BC846 BC847 BC848 BC849 BC850 MMBT3904 MMBT5550L MMBT5551L
+$FPLIST
+ SOT?23*
+$ENDFPLIST
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X B 1 -200 0 225 R 50 50 1 1 I
+X E 2 100 -200 100 U 50 50 1 1 P
+X C 3 100 200 100 D 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # power_+12V
 #
 DEF power_+12V #PWR 0 0 Y Y 1 F P
@@ -235,6 +749,22 @@ X +12V 1 0 0 0 U 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
+# power_+3V3
+#
+DEF power_+3V3 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+3V3" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
 # power_+5V
 #
 DEF power_+5V #PWR 0 0 Y Y 1 F P
@@ -289,194 +819,4 @@ X GND 1 0 0 0 D 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
-# stdparts_39F040
-#
-DEF stdparts_39F040 U 0 20 Y Y 1 F N
-F0 "U" 0 1050 50 H V C CNN
-F1 "stdparts_39F040" 0 0 50 V V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-S -300 1000 300 -1000 0 1 10 f
-X GND 16 500 -900 200 L 50 50 0 0 W
-X VCC 32 500 900 200 L 50 50 0 0 W
-X A18 1 -500 -900 200 R 50 50 1 1 I
-X A2 10 -500 700 200 R 50 50 1 1 I
-X A1 11 -500 800 200 R 50 50 1 1 I
-X A0 12 -500 900 200 R 50 50 1 1 I
-X D0 13 500 700 200 L 50 50 1 1 T
-X D1 14 500 600 200 L 50 50 1 1 T
-X D2 15 500 500 200 L 50 50 1 1 T
-X D3 17 500 400 200 L 50 50 1 1 T
-X D4 18 500 300 200 L 50 50 1 1 T
-X D5 19 500 200 200 L 50 50 1 1 T
-X A16 2 -500 -700 200 R 50 50 1 1 I
-X D6 20 500 100 200 L 50 50 1 1 T
-X D7 21 500 0 200 L 50 50 1 1 T
-X ~CS~ 22 500 -400 200 L 50 50 1 1 I L
-X A10 23 -500 -100 200 R 50 50 1 1 I
-X ~OE~ 24 500 -600 200 L 50 50 1 1 I L
-X A11 25 -500 -200 200 R 50 50 1 1 I
-X A9 26 -500 0 200 R 50 50 1 1 I
-X A8 27 -500 100 200 R 50 50 1 1 I
-X A13 28 -500 -400 200 R 50 50 1 1 I
-X A14 29 -500 -500 200 R 50 50 1 1 I
-X A15 3 -500 -600 200 R 50 50 1 1 I
-X A17 30 -500 -800 200 R 50 50 1 1 I
-X ~WE~ 31 500 -500 200 L 50 50 1 1 I L
-X A12 4 -500 -300 200 R 50 50 1 1 I
-X A7 5 -500 200 200 R 50 50 1 1 I
-X A6 6 -500 300 200 R 50 50 1 1 I
-X A5 7 -500 400 200 R 50 50 1 1 I
-X A4 8 -500 500 200 R 50 50 1 1 I
-X A3 9 -500 600 200 R 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# stdparts_AS4C4M4
-#
-DEF stdparts_AS4C4M4 U 0 20 Y Y 1 F N
-F0 "U" 0 800 50 H V C CNN
-F1 "stdparts_AS4C4M4" 0 0 50 V V C CNN
-F2 "Package_SO:TSOP-II-44_10.16x18.41mm_P0.8mm" 0 -900 50 H I C CNN
-F3 "" 0 -450 50 H I C CNN
-$FPLIST
- SOJ*10.16x23.49mm*P1.27mm*
-$ENDFPLIST
-DRAW
-S -300 750 300 -850 0 1 10 f
-X A4 1 -400 250 100 R 50 50 1 1 I
-X I/O2 11 400 250 100 L 50 50 1 1 B
-X VDD 11 400 650 100 L 50 50 1 1 W
-X GND 12 -400 -750 100 R 50 50 1 1 P N
-X I/O3 12 400 150 100 L 50 50 1 1 B
-X NC 15 -400 -550 100 R 50 50 1 1 N N
-X NC 16 -400 -550 100 R 50 50 1 1 N N
-X ~WE~ 17 400 -650 100 L 50 50 1 1 I
-X A3 2 -400 350 100 R 50 50 1 1 I
-X I/O4 25 400 50 100 L 50 50 1 1 B
-X I/O5 26 400 -50 100 L 50 50 1 1 B
-X A10 27 -400 -350 100 R 50 50 1 1 I
-X A9 28 -400 -250 100 R 50 50 1 1 I
-X I/O6 29 400 -150 100 L 50 50 1 1 B
-X NC 29 -400 -550 100 R 50 50 1 1 N N
-X A2 3 -400 450 100 R 50 50 1 1 I
-X I/O7 30 400 -250 100 L 50 50 1 1 B
-X NC 30 -400 -550 100 R 50 50 1 1 N N
-X VDD 33 400 650 100 L 50 50 1 1 W N
-X GND 34 -400 -750 100 R 50 50 1 1 W
-X NC 37 -400 -550 100 R 50 50 1 1 N N
-X NC 38 -400 -550 100 R 50 50 1 1 N N
-X A8 39 -400 -150 100 R 50 50 1 1 I
-X A1 4 -400 550 100 R 50 50 1 1 I
-X ~RAS~ 40 400 -550 100 L 50 50 1 1 I
-X ~OE~ 41 400 -750 100 L 50 50 1 1 I
-X A7 42 -400 -50 100 R 50 50 1 1 I
-X A6 43 -400 50 100 R 50 50 1 1 I
-X A5 44 -400 150 100 R 50 50 1 1 I
-X A0 5 -400 650 100 R 50 50 1 1 I
-X ~CAS~ 6 400 -450 100 L 50 50 1 1 I
-X I/O0 7 400 450 100 L 50 50 1 1 B
-X NC 7 -400 -550 100 R 50 50 1 1 N N
-X I/O1 8 400 350 100 L 50 50 1 1 B
-X NC 8 -400 -550 100 R 50 50 1 1 N N
-ENDDRAW
-ENDDEF
-#
-# stdparts_EPM7128SL84
-#
-DEF stdparts_EPM7128SL84 U 0 40 Y Y 1 F N
-F0 "U" 0 50 50 H V C CNN
-F1 "stdparts_EPM7128SL84" 0 -50 50 H V C CNN
-F2 "" -150 200 50 H I C CNN
-F3 "" -150 200 50 H I C CNN
-DRAW
-S -600 -1950 600 1850 0 1 10 f
-X ~GClr~ 1 750 900 150 L 50 50 1 1 I
-X I/O 10 750 1600 150 L 50 50 1 1 B
-X I/O 11 750 1700 150 L 50 50 1 1 B
-X I/O 12 -750 1700 150 R 50 50 1 1 B
-X VccIO 13 -350 2000 150 D 50 50 1 1 W
-X TDI 14 -750 1600 150 R 50 50 1 1 B
-X I/O 15 -750 1500 150 R 50 50 1 1 B
-X I/O 16 -750 1400 150 R 50 50 1 1 B
-X I/O 17 -750 1300 150 R 50 50 1 1 B
-X I/O 18 -750 1200 150 R 50 50 1 1 B
-X GND 19 -350 -2100 150 U 50 50 1 1 W
-X OE2/GClk2 2 750 1000 150 L 50 50 1 1 I
-X I/O 20 -750 1100 150 R 50 50 1 1 B
-X I/O 21 -750 1000 150 R 50 50 1 1 B
-X I/O 22 -750 900 150 R 50 50 1 1 B
-X TMS 23 -750 800 150 R 50 50 1 1 B
-X I/O 24 -750 700 150 R 50 50 1 1 B
-X I/O 25 -750 600 150 R 50 50 1 1 B
-X VccIO 26 -250 2000 150 D 50 50 1 1 W
-X I/O 27 -750 500 150 R 50 50 1 1 W
-X I/O 28 -750 400 150 R 50 50 1 1 B
-X I/O 29 -750 300 150 R 50 50 1 1 B
-X VccINT 3 350 2000 150 D 50 50 1 1 W
-X I/O 30 -750 200 150 R 50 50 1 1 B
-X I/O 31 -750 100 150 R 50 50 1 1 B
-X GND 32 -250 -2100 150 U 50 50 1 1 W
-X I/O 33 -750 -100 150 R 50 50 1 1 B
-X I/O 34 -750 -200 150 R 50 50 1 1 B
-X I/O 35 -750 -300 150 R 50 50 1 1 B
-X I/O 36 -750 -400 150 R 50 50 1 1 B
-X I/O 37 -750 -500 150 R 50 50 1 1 B
-X VccIO 38 -150 2000 150 D 50 50 1 1 W
-X I/O/NC 39 -750 -600 150 R 50 50 1 1 B
-X I/O 4 750 1100 150 L 50 50 1 1 B
-X I/O 40 -750 -700 150 R 50 50 1 1 B
-X I/O 41 -750 -800 150 R 50 50 1 1 B
-X GND 42 -150 -2100 150 U 50 50 1 1 W
-X VccINT 43 250 2000 150 D 50 50 1 1 W
-X I/O 44 -750 -900 150 R 50 50 1 1 B
-X I/O 45 -750 -1000 150 R 50 50 1 1 B
-X I/O/NC 46 -750 -1100 150 R 50 50 1 1 B
-X GND 47 -50 -2100 150 U 50 50 1 1 W
-X I/O 48 -750 -1200 150 R 50 50 1 1 B
-X I/O 49 -750 -1300 150 R 50 50 1 1 B
-X I/O 5 750 1200 150 L 50 50 1 1 B
-X I/O 50 -750 -1400 150 R 50 50 1 1 B
-X I/O 51 -750 -1500 150 R 50 50 1 1 B
-X I/O 52 -750 -1600 150 R 50 50 1 1 B
-X VccIO 53 -50 2000 150 D 50 50 1 1 W
-X I/O 54 750 -1800 150 L 50 50 1 1 B
-X I/O 55 750 -1700 150 L 50 50 1 1 B
-X I/O 56 750 -1600 150 L 50 50 1 1 B
-X I/O 57 750 -1500 150 L 50 50 1 1 B
-X I/O 58 750 -1400 150 L 50 50 1 1 B
-X GND 59 50 -2100 150 U 50 50 1 1 W
-X I/O/NC 6 750 1300 150 L 50 50 1 1 B
-X I/O 60 750 -1300 150 L 50 50 1 1 B
-X I/O 61 750 -1200 150 L 50 50 1 1 B
-X TCK 62 750 -1100 150 L 50 50 1 1 B
-X I/O 63 750 -1000 150 L 50 50 1 1 B
-X I/O 64 750 -900 150 L 50 50 1 1 B
-X I/O 65 750 -800 150 L 50 50 1 1 B
-X VccIO 66 50 2000 150 D 50 50 1 1 W
-X I/O 67 750 -700 150 L 50 50 1 1 B
-X I/O 68 750 -600 150 L 50 50 1 1 B
-X I/O 69 750 -500 150 L 50 50 1 1 B
-X GND 7 350 -2100 150 U 50 50 1 1 W
-X I/O 70 750 -400 150 L 50 50 1 1 B
-X TDO 71 750 -300 150 L 50 50 1 1 B
-X GND 72 150 -2100 150 U 50 50 1 1 W
-X I/O 73 750 -200 150 L 50 50 1 1 B
-X I/O 74 750 -100 150 L 50 50 1 1 B
-X I/O 75 750 100 150 L 50 50 1 1 B
-X I/O 76 750 200 150 L 50 50 1 1 B
-X I/O 77 750 300 150 L 50 50 1 1 B
-X VccIO 78 150 2000 150 D 50 50 1 1 W
-X I/O/NC 79 750 400 150 L 50 50 1 1 B
-X I/O 8 750 1400 150 L 50 50 1 1 B
-X I/O 80 750 500 150 L 50 50 1 1 B
-X I/O 81 750 600 150 L 50 50 1 1 B
-X GND 82 250 -2100 150 U 50 50 1 1 W
-X GClk1 83 750 700 150 L 50 50 1 1 I
-X OE1 84 750 800 150 L 50 50 1 1 I
-X I/O 9 750 1500 150 L 50 50 1 1 B
-ENDDRAW
-ENDDEF
-#
 #End Library

GR8RAM.pro

@@ -1,4 +1,4 @@
-update=Monday, June 10, 2019 at 02:27:25 PM
+update=Wednesday, January 06, 2021 at 01:09:33 AM
 version=1
 last_client=kicad
 [general]
@@ -12,16 +12,6 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=
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-LabSize=50
-ERC_TestSimilarLabels=1
 [pcbnew]
 version=1
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@@ -32,23 +22,36 @@ AllowMicroVias=0
 AllowBlindVias=0
 RequireCourtyardDefinitions=0
 ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.1524
-MinViaDiameter=0.4
-MinViaDrill=0.3
+MinTrackWidth=0.15
+MinViaDiameter=0.5
+MinViaDrill=0.2
 MinMicroViaDiameter=0.2
 MinMicroViaDrill=0.09999999999999999
 MinHoleToHole=0.25
-TrackWidth1=0.1524
+TrackWidth1=0.15
 TrackWidth2=0.2
-TrackWidth3=0.254
-TrackWidth4=0.508
-TrackWidth5=0.762
-TrackWidth6=1.27
-TrackWidth7=1.524
-ViaDiameter1=0.8
-ViaDrill1=0.4
-ViaDiameter2=1.524
-ViaDrill2=0.762
+TrackWidth3=0.25
+TrackWidth4=0.3
+TrackWidth5=0.35
+TrackWidth6=0.4
+TrackWidth7=0.45
+TrackWidth8=0.5
+TrackWidth9=0.6
+TrackWidth10=0.762
+TrackWidth11=0.8
+TrackWidth12=1
+TrackWidth13=1.27
+TrackWidth14=1.524
+ViaDiameter1=0.5
+ViaDrill1=0.2
+ViaDiameter2=0.6
+ViaDrill2=0.3
+ViaDiameter3=0.8
+ViaDrill3=0.4
+ViaDiameter4=1
+ViaDrill4=0.5
+ViaDiameter5=1.524
+ViaDrill5=0.762
 dPairWidth1=0.2
 dPairGap1=0.25
 dPairViaGap1=0.25
@@ -58,7 +61,7 @@ SilkTextSizeH=1
 SilkTextSizeThickness=0.15
 SilkTextItalic=0
 SilkTextUpright=1
-CopperLineWidth=0.1524
+CopperLineWidth=0.15
 CopperTextSizeV=1.5
 CopperTextSizeH=1.5
 CopperTextThickness=0.3
@@ -73,8 +76,8 @@ OthersTextSizeThickness=0.15
 OthersTextItalic=0
 OthersTextUpright=1
 SolderMaskClearance=0.07619999999999999
-SolderMaskMinWidth=0.1524
-SolderPasteClearance=-0.05
+SolderMaskMinWidth=0.127
+SolderPasteClearance=-0.03809999999999999
 SolderPasteRatio=0
 [pcbnew/Layer.F.Cu]
 Name=F.Cu
@@ -245,12 +248,22 @@ Enabled=0
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 [pcbnew/Netclasses/Default]
 Name=Default
-Clearance=0.1524
-TrackWidth=0.1524
-ViaDiameter=0.8
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+Clearance=0.15
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 uViaDiameter=0.3
 uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1

LICENSE

@@ -0,0 +1,20 @@
+Copyright (c) Garrett's Workshop
+
+Rationale
+----------------------------------------
+We at Garrett's Workshop create our products and release their source in
+hopes of encouraging others to contribute and build their own "clones,"
+even selling them and competing with us. One day, GW will be defunct,
+and it would be a shame if our hardware and software die along with GW.
+At the same time, however, we seek to protect our trademark and ensure
+that clones and derivative products do not masquerade as genuine
+Garrett's Workshop products.
+
+License Terms
+----------------------------------------
+This project may be licensed under one of two licenses:
+
+1. You may elect to license this project under CC BY-NC-SA 4.0.
+
+2. You may elect to license this project under CC BY-SA 4.0 ONLY IF
+   you remove all "Garrett's Workshop" trademarks from the project.

cpld/GR8RAM.dpf

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<pin_planner>
+	<pin_info>
+		<pin name="Ddor" source="Pin Planner" >
+		</pin>
+		<pin name="SDp1[" source="Pin Planner" >
+		</pin>
+		<pin name="sa[10[" source="Pin Planner" >
+		</pin>
+		<pin name="fw[0]" source="Pin Planner" >
+		</pin>
+	</pin_info>
+	<buses>
+	</buses>
+	<group_file_association>
+	</group_file_association>
+	<pin_planner_file_specifies>
+	</pin_planner_file_specifies>
+</pin_planner>

cpld/GR8RAM.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:41:40  March 15, 2021
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "13:41:40  March 15, 2021"
+
+# Revisions
+
+PROJECT_REVISION = "GR8RAM"

cpld/GR8RAM.qsf

@@ -0,0 +1,145 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:41:40  March 15, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		GR8RAM_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM240T100C5
+set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40  MARCH 15, 2021"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name SAFE_STATE_MACHINE OFF
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
+set_global_assignment -name AUTO_RESOURCE_SHARING ON
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
+set_global_assignment -name MUX_RESTRUCTURE ON
+set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
+set_global_assignment -name SYNTHESIS_SEED 123
+set_global_assignment -name SEED 235
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
+set_global_assignment -name VERILOG_FILE GR8RAM.v
+set_location_assignment PIN_1 -to RA[4]
+set_location_assignment PIN_2 -to RA[5]
+set_location_assignment PIN_3 -to RA[6]
+set_location_assignment PIN_4 -to RA[3]
+set_location_assignment PIN_5 -to nFCS
+set_location_assignment PIN_6 -to RA[7]
+set_location_assignment PIN_7 -to RA[8]
+set_location_assignment PIN_8 -to RA[9]
+set_location_assignment PIN_12 -to FCK
+set_location_assignment PIN_14 -to RA[10]
+set_location_assignment PIN_15 -to MOSI
+set_location_assignment PIN_16 -to MISO
+set_location_assignment PIN_17 -to Ddir
+set_location_assignment PIN_30 -to nRESout
+set_location_assignment PIN_34 -to RA[11]
+set_location_assignment PIN_35 -to RA[12]
+set_location_assignment PIN_36 -to RA[13]
+set_location_assignment PIN_37 -to RA[14]
+set_location_assignment PIN_38 -to RA[15]
+set_location_assignment PIN_39 -to nIOSEL
+set_location_assignment PIN_42 -to nIOSTRB
+set_location_assignment PIN_40 -to nDEVSEL
+set_location_assignment PIN_41 -to PHI0
+set_location_assignment PIN_43 -to nWE
+set_location_assignment PIN_44 -to nRES
+set_location_assignment PIN_47 -to SD[1]
+set_location_assignment PIN_50 -to SD[0]
+set_location_assignment PIN_51 -to SD[4]
+set_location_assignment PIN_100 -to RA[0]
+set_location_assignment PIN_99 -to RD[7]
+set_location_assignment PIN_52 -to SD[5]
+set_location_assignment PIN_54 -to SD[7]
+set_location_assignment PIN_55 -to SD[3]
+set_location_assignment PIN_56 -to SD[2]
+set_location_assignment PIN_53 -to SD[6]
+set_location_assignment PIN_57 -to DQMH
+set_location_assignment PIN_58 -to nSWE
+set_location_assignment PIN_62 -to nRAS
+set_location_assignment PIN_61 -to nCAS
+set_location_assignment PIN_64 -to C25M
+set_location_assignment PIN_66 -to RCKE
+set_location_assignment PIN_67 -to nRCS
+set_location_assignment PIN_68 -to SA[12]
+set_location_assignment PIN_69 -to SBA[0]
+set_location_assignment PIN_70 -to SA[11]
+set_location_assignment PIN_71 -to SBA[1]
+set_location_assignment PIN_72 -to SA[9]
+set_location_assignment PIN_73 -to SA[10]
+set_location_assignment PIN_74 -to SA[8]
+set_location_assignment PIN_75 -to SA[0]
+set_location_assignment PIN_76 -to SA[4]
+set_location_assignment PIN_77 -to SA[6]
+set_location_assignment PIN_78 -to SA[7]
+set_location_assignment PIN_81 -to SA[1]
+set_location_assignment PIN_82 -to SA[2]
+set_location_assignment PIN_83 -to SA[5]
+set_location_assignment PIN_84 -to SA[3]
+set_location_assignment PIN_85 -to DQML
+set_location_assignment PIN_86 -to RD[0]
+set_location_assignment PIN_87 -to RD[1]
+set_location_assignment PIN_88 -to RD[2]
+set_location_assignment PIN_89 -to RD[3]
+set_location_assignment PIN_90 -to RD[4]
+set_location_assignment PIN_91 -to RD[5]
+set_location_assignment PIN_92 -to RD[6]
+set_location_assignment PIN_97 -to RA[2]
+set_location_assignment PIN_98 -to RA[1]
+set_location_assignment PIN_96 -to SetFW[0]
+set_location_assignment PIN_95 -to SetFW[1]
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2

cpld/GR8RAM.v

@@ -0,0 +1,549 @@
+module GR8RAM(C25M, PHI0, nRES, nRESout,
+			  nIOSEL, nDEVSEL, nIOSTRB,
+			  SetFW,
+			  RA, nWE, RD, RDdir,
+			  SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
+			  nFCS, FCK, MISO, MOSI);
+
+	/* Clock signals */
+	input C25M, PHI0;
+	reg PHI0r1, PHI0r2;
+	always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
+
+	/* Reset/brown-out detect synchronized inputs */
+	input nRES;
+	reg nRESr0, nRESr;
+	always @(posedge C25M) begin nRESr0 <= nRES; nRESr <= nRESr0; end
+
+	/* Long state counter: counts from 0 to $3FFF */
+	reg [13:0] LS = 0;
+	always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
+
+	/* Init state */
+	output reg nRESout = 0;
+	reg [2:0] IS = 0;
+	always @(posedge C25M) begin
+		if (IS==7) nRESout <= 1;
+		else if (PS==15) begin
+			if (LS==14'h1FCE) IS <= 1; // PC all + load mode
+			else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
+			else if (LS==14'h1FFA) IS <= 5; // SPI flash command
+			else if (LS==14'h1FFF) IS <= 6; // Flash load driver
+			else if (LS==14'h3FFF) IS <= 7; // Operating mode
+		end
+	end
+
+	/* Apple IO area select signals */
+	input nIOSEL, nDEVSEL, nIOSTRB;
+
+	/* Apple address bus */
+	input [15:0] RA; input nWE;
+
+	/* Apple select signals */
+	wire ROMSpecSEL = RA[15:12]==4'hC && RA[11:8]!=4'h0;
+	wire BankSpecSEL = RA[3:0]==4'hF;
+	wire REGSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && REGEN;
+	wire RAMSpecSEL = REGSpecSEL && RA[3:0]==4'h3 && (~SetLim1M || Addr[23:20]==0) && (~SetLim8M || ~Addr[23]);
+	wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2;
+	wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1;
+	wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0;
+	reg ROMSpecSELr, RAMSpecSELr, nWEr;
+	wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
+	wire RAMSEL = ~nDEVSEL && RAMSpecSELr;
+	wire RAMWR = RAMSEL && ~nWEr;
+	wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
+	wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
+	wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
+	always @(posedge PHI0) begin
+		ROMSpecSELr <= ROMSpecSEL;
+		RAMSpecSELr <= RAMSpecSEL;
+		nWEr <= nWE;
+	end
+	
+	/* IOROMEN and REGEN control */
+	reg IOROMEN = 0;
+	reg REGEN = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (~nRESr) begin
+			IOROMEN <= 0;
+			REGEN <= 0;
+		end else if (PS==8 && ~nIOSTRB && RA[10:0]==11'h7FF) begin
+			IOROMEN <= 0;
+		end else if (PS==8 && ~nIOSEL) begin
+			IOROMEN <= 1;
+			REGEN <= 1;
+		end
+	end
+
+	/* Apple data bus */
+	inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
+	reg [7:0] RDD;
+	output RDdir = ~(PHI0r2 && nWE && PHI0 &&
+		(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)));
+
+	/* Slinky address registers */
+	reg [23:0] Addr = 0;
+	reg AddrIncL = 0;
+	reg AddrIncM = 0;
+	reg AddrIncH = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (~nRESr) begin
+			Addr[23:0] <= 24'h000000;
+			AddrIncL <= 0;
+			AddrIncM <= 0;
+			AddrIncH <= 0;
+		end else begin
+			if (PS==8 && RAMSEL) AddrIncL <= 1;
+			else AddrIncL <= 0;
+
+			if (PS==8 && AddrLSEL && ~nWEr) begin
+				Addr[7:0] <= RD[7:0];
+				AddrIncM <= Addr[7] && ~RD[7];
+			end else if (AddrIncL) begin
+				Addr[7:0] <= Addr[7:0]+1;
+				AddrIncM <= Addr[7:0]==8'hFF;
+			end else AddrIncM <= 0;
+
+			if (PS==8 && AddrMSEL && ~nWEr) begin
+				Addr[15:8] <= RD[7:0];
+				AddrIncH <= Addr[15] && ~RD[7];
+			end else if (AddrIncM) begin
+				Addr[15:8] <= Addr[15:8]+1;
+				AddrIncH <= Addr[15:8]==8'hFF;
+			end else AddrIncH <= 0;
+
+			if (PS==8 && AddrHSEL && ~nWEr) begin
+				Addr[23:16] <= RD[7:0];
+			end else if (AddrIncH) begin
+				Addr[23:16] <= Addr[23:16]+1;
+			end
+		end
+	end
+
+	/* ROM bank register */
+	reg Bank = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (~nRESr) Bank <= 0;
+		else if (PS==8 && BankSEL && ~nWEr) begin
+			Bank <= RD[0];
+		end
+	end
+
+	/* SPI flash */
+	output nFCS = ~FCS;
+	reg FCS = 0;
+	output reg FCK = 0;
+	inout MOSI = MOSIOE ? MOSIout : 1'bZ;
+	reg MOSIOE = 0;
+	reg MOSIout;
+	input MISO;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				FCK <= 1'b1;
+			end 1: begin // ACT
+				FCK <= ~(IS==5 || IS==6);
+			end 2: begin // RD
+				FCK <= 1'b1;
+			end 3: begin // NOP CKE
+				FCK <= ~(IS==5 || IS==6);
+			end 4: begin // NOP CKE
+				FCK <= 1'b1;
+			end 5: begin // NOP CKE
+				FCK <= ~(IS==5 || IS==6);
+			end 6: begin // NOP CKE
+				FCK <= 1'b1;
+			end 7: begin // NOP CKE
+				FCK <= ~(IS==5 || IS==6);
+			end 8: begin // WR AP
+				FCK <= 1'b1;
+			end 9: begin // NOP CKE
+				FCK <= ~(IS==5);
+			end 10: begin // PC all
+				FCK <= 1'b1;
+			end 11: begin // AREF
+				FCK <= ~(IS==5);
+			end 12: begin // NOP CKE
+				FCK <= 1'b1;
+			end 13: begin // NOP CKE
+				FCK <= ~(IS==5);
+			end 14: begin // NOP CKE
+				FCK <= 1'b1;
+			end 15: begin // NOP CKE
+				FCK <= ~(IS==5);
+			end
+		endcase
+		FCS <= IS==4 || IS==5 || IS==6;
+		MOSIOE <= IS==5;
+	end
+
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			1, 2: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 7
+					3'h4: MOSIout <= 1'b0; // Address bit 23
+					3'h5: MOSIout <= 1'b0; // Address bit 15
+					3'h6: MOSIout <= 1'b0; // Address bit 7
+					default MOSIout <= 1'b0;
+				endcase
+			end 3, 4: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 6
+					3'h4: MOSIout <= 1'b0; // Address bit 22
+					3'h5: MOSIout <= SetFW[1]; // Address bit 14
+					3'h6: MOSIout <= 1'b0; // Address bit 6
+					default MOSIout <= 1'b0;
+				endcase
+			end 5, 6: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 5
+					3'h4: MOSIout <= 1'b0; // Address bit 21
+					3'h5: MOSIout <= SetFW[0]; // Address bit 13
+					3'h6: MOSIout <= 1'b0; // Address bit 5
+					default MOSIout <= 1'b0;
+				endcase
+			end 7, 8: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 4
+					3'h4: MOSIout <= 1'b0; // Address bit 20
+					3'h5: MOSIout <= 1'b0; // Address bit 12
+					3'h6: MOSIout <= 1'b0; // Address bit 4
+					default MOSIout <= 1'b0;
+				endcase
+			end 9, 10: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 3
+					3'h4: MOSIout <= 1'b0; // Address bit 19
+					3'h5: MOSIout <= 1'b0; // Address bit 11
+					3'h6: MOSIout <= 1'b0; // Address bit 3
+					default MOSIout <= 1'b0;
+				endcase
+			end 11, 12: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 2
+					3'h4: MOSIout <= 1'b0; // Address bit 18
+					3'h5: MOSIout <= 1'b0; // Address bit 10
+					3'h6: MOSIout <= 1'b0; // Address bit 2
+					default MOSIout <= 1'b0;
+				endcase
+			end 13, 14: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 1
+					3'h4: MOSIout <= 1'b0; // Address bit 16
+					3'h5: MOSIout <= 1'b0; // Address bit 9
+					3'h6: MOSIout <= 1'b0; // Address bit 1
+					default MOSIout <= 1'b0;
+				endcase
+			end 15, 0: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 0
+					3'h4: MOSIout <= 1'b0; // Address bit 15
+					3'h5: MOSIout <= 1'b0; // Address bit 7
+					3'h6: MOSIout <= 1'b0; // Address bit 0
+					default MOSIout <= 1'b0;
+				endcase
+			end 
+		endcase
+	end
+
+	input [1:0] SetFW;
+	wire SetRF = SetFW[1:0] != 2'b11;
+	wire SetLim1M = SetFW[1];
+	wire SetLim8M = SetFW[1:0] != 2'b00;
+
+	/* SDRAM data bus */
+	inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
+	reg [7:0] WRD;
+	reg SDOE = 0;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				else WRD[7:0] <= RD[7:0];
+			end 1: begin // ACT
+			end 2: begin // RD
+				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				else WRD[7:0] <= RD[7:0];
+			end 3: begin // NOP CKE
+			end 4: begin // NOP CKE
+				if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
+				else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
+				else if (AddrHSpecSEL && SetRF) RDD[7:0] <= Addr[23:16];
+				else if (AddrHSpecSEL && ~SetRF) RDD[7:0] <= {4'hF, Addr[19:16]};
+				else RDD[7:0] <= SD[7:0];
+				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				else WRD[7:0] <= RD[7:0];
+			end 5: begin // NOP CKE
+			end 6: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				else WRD[7:0] <= RD[7:0];
+			end 7: begin // NOP CKE
+			end 8: begin // WR AP
+				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				else WRD[7:0] <= RD[7:0];
+			end 9: begin // NOP CKE
+			end 10: begin // PC all
+				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				else WRD[7:0] <= RD[7:0];
+			end 11: begin // AREF
+			end 12: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				else WRD[7:0] <= RD[7:0];
+			end 13: begin // NOP CKE
+			end 14: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				else WRD[7:0] <= RD[7:0];
+			end 15: begin // NOP CKE
+			end
+		endcase
+	end
+
+	reg [3:0] PS = 0;
+	wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
+	always @(posedge C25M) begin
+		if (PSStart) PS <= 1;
+		else if (PS==0) PS <= 0;
+		else PS <= PS+1;
+	end
+
+	/* SDRAM address/command */
+	output reg RCKE = 1;
+	output reg nRCS = 1;
+	output reg nRAS = 1;
+	output reg nCAS = 1;
+	output reg nSWE = 1;
+	wire RefReqd = LS[1:0] == 2'b11;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE / CKD
+				RCKE <= PSStart;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;	
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 1: begin // ACT CKE / NOP CKD
+				RCKE <= IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7);
+				nRCS <= ~(IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7));
+				nRAS <= 1'b0;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 2: begin // RD CKE / NOP CKD
+				RCKE <= (ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7;
+				nRCS <= ~((ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7);
+				nRAS <= 1'b1;
+				nCAS <= 1'b0;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 3: begin // NOP CKE / CKD
+				RCKE <= (ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 4: begin // NOP CKD
+				RCKE <= 1'b0;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 5: begin // NOP CKD
+				RCKE <= 1'b0;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 6: begin // NOP CKD
+				RCKE <= 1'b0;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 7: begin // NOP CKE / CKD
+				RCKE <= IS==6 || (RAMWR && IS==7);
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 8: begin // WR AP / NOP CKE (WR AP)
+				// NOP CKD / WR AP
+				RCKE <= IS==6 || (RAMWR && IS==7);
+				nRCS <= ~(IS==6 || (RAMWR && IS==7));
+				nRAS <= 1'b1;
+				nCAS <= 1'b0;
+				nSWE <= 1'b0;
+				SDOE <= IS==6 || (RAMWR && IS==7);
+			end 9: begin // NOP CKE / NOP CKD
+				RCKE <= (IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) || 
+					 (RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 10: begin // PC all / NOP CKD (PC all)
+				RCKE <= (IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
+					(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
+				nRCS <= ~((IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
+					(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7)));
+				nRAS <= 1'b0;
+				nCAS <= 1'b1;
+				nSWE <= 1'b0;
+				SDOE <= 0;
+			end 11: begin // AREF / NOP CKD (AREF)
+				RCKE <= RefReqd && (IS==4 || IS==5 || IS==6 || IS==7);
+				nRCS <= ~(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
+				nRAS <= 1'b0;
+				nCAS <= 1'b0;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 12: begin // NOP CKD
+				RCKE <= 1'b0;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 13: begin // NOP CKD
+				RCKE <= 1'b0;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 14: begin // NOP CKD
+				RCKE <= 1'b0;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end 15: begin // NOP CKD
+				RCKE <= 1'b0;
+				nRCS <= 1'b1;
+				nRAS <= 1'b1;
+				nCAS <= 1'b1;
+				nSWE <= 1'b1;
+				SDOE <= 0;
+			end
+		endcase
+	end
+	output reg DQML = 1;
+	output reg DQMH = 1;
+	output reg [1:0] SBA;
+	output reg [12:0] SA;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 1: begin // ACT
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				if (IS==6) begin
+					SBA[1:0] <= { 2'b10 };
+					SA[12:0] <= { 10'b0011000100, LS[12:10] };
+				end else if (RAMSpecSELr) begin
+					SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
+					SA[12:0] <= { SetRF ? Addr [22:20] : 3'b000, Addr[19:10]};
+				end else begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] };
+				end
+			end 2: begin // RD
+				if (RAMSpecSELr) begin
+					SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
+					SA[12:0] <= { 4'b0011, Addr[9:1] };
+					DQML <= Addr[0];
+					DQMH <= ~Addr[0];
+				end else begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 4'b0011, RA[9:1]};
+					DQML <= RA[0];
+					DQMH <= ~RA[0];
+				end
+			end 3: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 4: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 5: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 6: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 7: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 8: begin // WR AP
+				if (IS==6) begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 4'b0011, LS[9:1] };
+					DQML <= LS[0];
+					DQMH <= ~LS[0];
+				end else begin
+					SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
+					SA[12:0] <= { 4'b0011, Addr[9:1] };
+					DQML <= Addr[0];
+					DQMH <= ~Addr[0];
+				end
+			end 9: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 10: begin // PC all
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 11: begin // AREF / load mode
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0001000100000;
+			end 12: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 13: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 14: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 15: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end
+		endcase
+	end
+endmodule

cpld/UFM.qip

@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]

cpld/db/GR8RAM.asm.qmsg

@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161759471 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:38 2021 " "Processing started: Sun Apr 11 13:22:38 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618161760940 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618161760971 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:41 2021 " "Processing ended: Sun Apr 11 13:22:41 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618161761456 ""}

cpld/db/GR8RAM.cbx.xml

@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="GR8RAM">
+	</PROJECT>
+</LOG_ROOT>

cpld/db/GR8RAM.cmp.logdb

@@ -0,0 +1 @@
+v1

cpld/db/GR8RAM.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Sun Apr 11 00:06:29 2021

cpld/db/GR8RAM.fit.qmsg

@@ -0,0 +1,44 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618161749377 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618161749440 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618161749627 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618161749627 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618161750455 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618161750486 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618161750955 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 69 " "No exact pin location assignment(s) for 1 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 82 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 356 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618161750971 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618161750971 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618161751096 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618161751096 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618161751111 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618161751111 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         C25M " "   1.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI0 " "   1.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618161751111 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618161751127 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618161751127 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618161751143 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618161751205 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618161751205 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 350 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618161751221 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618161751252 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618161751377 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618161751393 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618161751393 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618161751393 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618161751408 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618161751408 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618161751408 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 26 12 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1618161751424 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 42 0 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1618161751424 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618161751424 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618161751424 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Ddir " "Node \"Ddir\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "Ddir" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1618161751455 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618161751455 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161751455 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618161751674 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161752080 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618161752111 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618161753690 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161753690 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618161753752 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618161754096 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618161754096 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161754737 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618161754737 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161754752 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1618161754768 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618161754768 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618161754893 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:35 2021 " "Processing ended: Sun Apr 11 13:22:35 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618161755065 ""}

cpld/db/GR8RAM.hier_info

@@ -0,0 +1,219 @@
+|GR8RAM
+C25M => SA[0]~reg0.CLK
+C25M => SA[1]~reg0.CLK
+C25M => SA[2]~reg0.CLK
+C25M => SA[3]~reg0.CLK
+C25M => SA[4]~reg0.CLK
+C25M => SA[5]~reg0.CLK
+C25M => SA[6]~reg0.CLK
+C25M => SA[7]~reg0.CLK
+C25M => SA[8]~reg0.CLK
+C25M => SA[9]~reg0.CLK
+C25M => SA[10]~reg0.CLK
+C25M => SA[11]~reg0.CLK
+C25M => SA[12]~reg0.CLK
+C25M => SBA[0]~reg0.CLK
+C25M => SBA[1]~reg0.CLK
+C25M => DQMH~reg0.CLK
+C25M => DQML~reg0.CLK
+C25M => SDOE.CLK
+C25M => nSWE~reg0.CLK
+C25M => nCAS~reg0.CLK
+C25M => nRAS~reg0.CLK
+C25M => nRCS~reg0.CLK
+C25M => RCKE~reg0.CLK
+C25M => PS[0].CLK
+C25M => PS[1].CLK
+C25M => PS[2].CLK
+C25M => PS[3].CLK
+C25M => RDD[0].CLK
+C25M => RDD[1].CLK
+C25M => RDD[2].CLK
+C25M => RDD[3].CLK
+C25M => RDD[4].CLK
+C25M => RDD[5].CLK
+C25M => RDD[6].CLK
+C25M => RDD[7].CLK
+C25M => WRD[0].CLK
+C25M => WRD[1].CLK
+C25M => WRD[2].CLK
+C25M => WRD[3].CLK
+C25M => WRD[4].CLK
+C25M => WRD[5].CLK
+C25M => WRD[6].CLK
+C25M => WRD[7].CLK
+C25M => MOSIout.CLK
+C25M => MOSIOE.CLK
+C25M => FCS.CLK
+C25M => FCK~reg0.CLK
+C25M => Bank.CLK
+C25M => AddrIncH.CLK
+C25M => AddrIncM.CLK
+C25M => AddrIncL.CLK
+C25M => Addr[0].CLK
+C25M => Addr[1].CLK
+C25M => Addr[2].CLK
+C25M => Addr[3].CLK
+C25M => Addr[4].CLK
+C25M => Addr[5].CLK
+C25M => Addr[6].CLK
+C25M => Addr[7].CLK
+C25M => Addr[8].CLK
+C25M => Addr[9].CLK
+C25M => Addr[10].CLK
+C25M => Addr[11].CLK
+C25M => Addr[12].CLK
+C25M => Addr[13].CLK
+C25M => Addr[14].CLK
+C25M => Addr[15].CLK
+C25M => Addr[16].CLK
+C25M => Addr[17].CLK
+C25M => Addr[18].CLK
+C25M => Addr[19].CLK
+C25M => Addr[20].CLK
+C25M => Addr[21].CLK
+C25M => Addr[22].CLK
+C25M => Addr[23].CLK
+C25M => REGEN.CLK
+C25M => IOROMEN.CLK
+C25M => nRESout~reg0.CLK
+C25M => LS[0].CLK
+C25M => LS[1].CLK
+C25M => LS[2].CLK
+C25M => LS[3].CLK
+C25M => LS[4].CLK
+C25M => LS[5].CLK
+C25M => LS[6].CLK
+C25M => LS[7].CLK
+C25M => LS[8].CLK
+C25M => LS[9].CLK
+C25M => LS[10].CLK
+C25M => LS[11].CLK
+C25M => LS[12].CLK
+C25M => LS[13].CLK
+C25M => nRESr.CLK
+C25M => nRESr0.CLK
+C25M => PHI0r2.CLK
+C25M => PHI0r1.CLK
+C25M => IS~7.DATAIN
+PHI0 => comb.IN1
+PHI0 => nWEr.CLK
+PHI0 => RAMSpecSELr.CLK
+PHI0 => ROMSpecSELr.CLK
+PHI0 => PHI0r1.DATAIN
+nRES => nRESr0.DATAIN
+nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nIOSEL => comb.IN0
+nIOSEL => always5.IN1
+nDEVSEL => comb.IN1
+nDEVSEL => RAMSEL.IN1
+nDEVSEL => comb.IN1
+nIOSTRB => comb.IN1
+nIOSTRB => always5.IN1
+SetFW[0] => Mux1.IN10
+SetFW[0] => Equal18.IN1
+SetFW[0] => Equal19.IN1
+SetFW[1] => MOSIout.DATAB
+SetFW[1] => comb.IN1
+SetFW[1] => Equal18.IN0
+SetFW[1] => Equal19.IN0
+RA[0] => DQML.DATAA
+RA[0] => Equal6.IN3
+RA[0] => Equal9.IN1
+RA[0] => Equal11.IN3
+RA[0] => Equal12.IN0
+RA[0] => Equal13.IN3
+RA[0] => Equal14.IN10
+RA[0] => DQMH.DATAA
+RA[1] => SA.DATAA
+RA[1] => Equal6.IN2
+RA[1] => Equal9.IN0
+RA[1] => Equal11.IN0
+RA[1] => Equal12.IN3
+RA[1] => Equal13.IN2
+RA[1] => Equal14.IN9
+RA[2] => SA.DATAA
+RA[2] => Equal6.IN1
+RA[2] => Equal9.IN3
+RA[2] => Equal11.IN2
+RA[2] => Equal12.IN2
+RA[2] => Equal13.IN1
+RA[2] => Equal14.IN8
+RA[3] => SA.DATAA
+RA[3] => Equal6.IN0
+RA[3] => Equal9.IN2
+RA[3] => Equal11.IN1
+RA[3] => Equal12.IN1
+RA[3] => Equal13.IN0
+RA[3] => Equal14.IN7
+RA[4] => SA.DATAA
+RA[4] => Equal14.IN6
+RA[5] => SA.DATAA
+RA[5] => Equal14.IN5
+RA[6] => SA.DATAA
+RA[6] => Equal14.IN4
+RA[7] => comb.IN1
+RA[7] => SA.DATAA
+RA[7] => Equal14.IN3
+RA[8] => SA.DATAA
+RA[8] => Equal8.IN3
+RA[8] => Equal14.IN2
+RA[9] => SA.DATAA
+RA[9] => Equal8.IN2
+RA[9] => Equal14.IN1
+RA[10] => SA.DATAA
+RA[10] => Equal8.IN1
+RA[10] => Equal14.IN0
+RA[11] => SA.DATAA
+RA[11] => Equal8.IN0
+RA[12] => Equal7.IN3
+RA[13] => Equal7.IN2
+RA[14] => Equal7.IN1
+RA[15] => Equal7.IN0
+nWE => comb.IN1
+nWE => nWEr.DATAIN
+RD[0] <> RD[0]
+RD[1] <> RD[1]
+RD[2] <> RD[2]
+RD[3] <> RD[3]
+RD[4] <> RD[4]
+RD[5] <> RD[5]
+RD[6] <> RD[6]
+RD[7] <> RD[7]
+RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
+SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SD[0] <> SD[0]
+SD[1] <> SD[1]
+SD[2] <> SD[2]
+SD[3] <> SD[3]
+SD[4] <> SD[4]
+SD[5] <> SD[5]
+SD[6] <> SD[6]
+SD[7] <> SD[7]
+nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE
+FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+MISO => WRD.DATAB
+MOSI <> MOSI
+
+

cpld/db/GR8RAM.lpc.html

@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>

cpld/db/GR8RAM.lpc.txt

@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

cpld/db/GR8RAM.map.logdb

@@ -0,0 +1 @@
+v1

cpld/db/GR8RAM.map.qmsg

@@ -0,0 +1,18 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161736158 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:15 2021 " "Processing started: Sun Apr 11 13:22:15 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161737908 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(256) " "Verilog HDL warning at GR8RAM.v(256): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 256 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618161738314 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(307) " "Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 307 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738330 "|GR8RAM"}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618161740127 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618161740877 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_LCELLS" "240 " "Implemented 240 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618161740986 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618161740986 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618161741470 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:21 2021 " "Processing ended: Sun Apr 11 13:22:21 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""}

cpld/db/GR8RAM.rpp.qmsg

@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616386555172 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616386555172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 00:15:54 2021 " "Processing started: Mon Mar 22 00:15:54 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616386555172 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555172 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp GR8RAM -c GR8RAM --netlist_type=atom " "Command: quartus_rpp GR8RAM -c GR8RAM --netlist_type=atom" {  } {  } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555172 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "207 " "Peak virtual memory: 207 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 00:15:55 2021 " "Processing ended: Mon Mar 22 00:15:55 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555922 ""}

cpld/db/GR8RAM.smart_action.txt

@@ -0,0 +1 @@
+DONE

cpld/db/GR8RAM.smp_dump.txt

@@ -0,0 +1,9 @@
+
+State Machine - |GR8RAM|IS
+Name IS.state_bit_2 IS.state_bit_1 IS.state_bit_0 
+IS.000 0 0 0 
+IS.001 0 0 1 
+IS.100 1 0 0 
+IS.101 1 0 1 
+IS.110 0 1 0 
+IS.111 0 1 1 

cpld/db/GR8RAM.sta.qmsg

@@ -0,0 +1,23 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161764909 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:43 2021 " "Processing started: Sun Apr 11 13:22:43 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618161765159 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161765987 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618161766331 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618161766815 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618161767003 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618161767003 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618161767050 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618161767331 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.908 " "Worst-case setup slack is -9.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -9.908      -697.920 C25M  " "   -9.908      -697.920 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.302        -1.302 PHI0  " "   -1.302        -1.302 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.012 " "Worst-case hold slack is 1.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.012         0.000 PHI0  " "    1.012         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.288         0.000 C25M  " "    1.288         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.389      -131.670 C25M  " "   -4.389      -131.670 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.835         0.000 C25M  " "    4.835         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 C25M  " "   -2.289        -2.289 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI0  " "   -2.289        -2.289 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618161767706 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:48 2021 " "Processing ended: Sun Apr 11 13:22:48 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""}

cpld/db/GR8RAM.tmw_info

@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:32
+start_analysis_synthesis:s:00:00:07-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:12-start_full_compilation
+start_assembler:s:00:00:06-start_full_compilation
+start_timing_analyzer:s:00:00:07-start_full_compilation

cpld/db/prev_cmp_GR8RAM.qmsg

@@ -0,0 +1,99 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618116856343 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:16 2021 " "Processing started: Sun Apr 11 00:54:16 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618116858062 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618116858250 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(256) " "Verilog HDL warning at GR8RAM.v(256): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 256 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618116858250 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618116858250 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618116858250 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618116858344 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(307) " "Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 307 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618116859969 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618116861047 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_LCELLS" "240 " "Implemented 240 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618116861078 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618116861078 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618116861313 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:21 2021 " "Processing ended: Sun Apr 11 00:54:21 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618116865000 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116865016 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:23 2021 " "Processing started: Sun Apr 11 00:54:23 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116865016 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618116865016 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618116865016 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618116865219 ""}
+{ "Info" "0" "" "Project  = GR8RAM" {  } {  } 0 0 "Project  = GR8RAM" 0 0 "Fitter" 0 0 1618116865219 ""}
+{ "Info" "0" "" "Revision = GR8RAM" {  } {  } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618116865219 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618116865922 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618116865938 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618116866110 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618116866110 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618116866391 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618116866422 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618116866766 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 69 " "No exact pin location assignment(s) for 1 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 82 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 356 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618116866766 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618116866766 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618116866938 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618116866938 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618116866954 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618116866954 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         C25M " "   1.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI0 " "   1.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618116866954 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618116866954 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618116866954 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618116866969 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618116866985 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618116866985 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 350 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618116867032 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618116867110 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618116867126 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618116867126 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618116867126 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618116867141 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618116867141 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618116867141 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 26 12 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1618116867141 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 42 0 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1618116867141 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618116867141 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618116867141 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Ddir " "Node \"Ddir\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "Ddir" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1618116867188 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618116867188 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116867188 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618116867376 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116867719 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618116867751 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618116869157 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116869157 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618116869204 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618116869595 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618116869595 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116870251 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618116870267 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116870282 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1618116870329 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618116870329 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618116870501 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:30 2021 " "Processing ended: Sun Apr 11 00:54:30 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618116870720 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618116872954 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116872954 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:32 2021 " "Processing started: Sun Apr 11 00:54:32 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116872954 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618116872954 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618116872954 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618116874064 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618116874079 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:34 2021 " "Processing ended: Sun Apr 11 00:54:34 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618116874548 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618116875298 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618116877189 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:36 2021 " "Processing started: Sun Apr 11 00:54:36 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618116877408 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618116878158 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618116878314 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618116878314 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618116878502 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618116879064 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618116879220 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618116879236 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618116879361 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.908 " "Worst-case setup slack is -9.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -9.908      -697.920 C25M  " "   -9.908      -697.920 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.302        -1.302 PHI0  " "   -1.302        -1.302 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.012 " "Worst-case hold slack is 1.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.012         0.000 PHI0  " "    1.012         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.288         0.000 C25M  " "    1.288         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.389      -131.670 C25M  " "   -4.389      -131.670 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.835         0.000 C25M  " "    4.835         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 C25M  " "   -2.289        -2.289 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI0  " "   -2.289        -2.289 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618116879611 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618116879705 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618116879705 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:39 2021 " "Processing ended: Sun Apr 11 00:54:39 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116880814 ""}

cpld/greybox_tmp/cbx_args.txt

@@ -0,0 +1,25 @@
+ERASE_TIME=500000000
+INTENDED_DEVICE_FAMILY="MAX II"
+LPM_FILE=UNUSED
+LPM_HINT=UNUSED
+LPM_TYPE=altufm_none
+OSC_FREQUENCY=180000
+PORT_ARCLKENA=PORT_UNUSED
+PORT_DRCLKENA=PORT_UNUSED
+PROGRAM_TIME=1600000
+WIDTH_UFM_ADDRESS=9
+DEVICE_FAMILY="MAX II"
+CBX_AUTO_BLACKBOX=ALL
+arclk
+ardin
+arshft
+busy
+drclk
+drdin
+drdout
+drshft
+erase
+osc
+oscena
+program
+rtpbusy

cpld/incremental_db/README

@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+

cpld/incremental_db/compiled_partitions/GR8RAM.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Thu Mar 18 03:51:58 2021

cpld/output_files/GR8RAM.asm.rpt

@@ -0,0 +1,114 @@
+Assembler report for GR8RAM
+Sun Apr 11 13:22:41 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Sun Apr 11 13:22:41 2021 ;
+; Revision Name         ; GR8RAM                                ;
+; Top-level Entity Name ; GR8RAM                                ;
+; Family                ; MAX II                                ;
+; Device                ; EPM240T100C5                          ;
++-----------------------+---------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                      ;
++-----------------------------------------------------------------------------+-----------+---------------+
+; Option                                                                      ; Setting   ; Default Value ;
++-----------------------------------------------------------------------------+-----------+---------------+
+; Use smart compilation                                                       ; Off       ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On        ; On            ;
+; Enable compact report table                                                 ; Off       ; Off           ;
+; Compression mode                                                            ; Off       ; Off           ;
+; Clock source for configuration device                                       ; Internal  ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ    ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1         ; 1             ;
+; Auto user code                                                              ; On        ; On            ;
+; Security bit                                                                ; Off       ; Off           ;
+; Use configuration device                                                    ; On        ; On            ;
+; Configuration device                                                        ; Auto      ; Auto          ;
+; Configuration device auto user code                                         ; Off       ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off       ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off       ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off       ; Off           ;
+; Hexadecimal Output File start address                                       ; 0         ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up        ; Up            ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off       ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off       ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off       ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On        ; On            ;
+; In-System Programming Default Clamp State                                   ; Tri-state ; Tri-state     ;
++-----------------------------------------------------------------------------+-----------+---------------+
+
+
++----------------------------------------------+
+; Assembler Generated Files                    ;
++----------------------------------------------+
+; File Name                                    ;
++----------------------------------------------+
+; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
++----------------------------------------------+
+
+
++------------------------------------------------------------------------+
+; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
++----------------+-------------------------------------------------------+
+; Option         ; Setting                                               ;
++----------------+-------------------------------------------------------+
+; Device         ; EPM240T100C5                                          ;
+; JTAG usercode  ; 0x00162982                                            ;
+; Checksum       ; 0x00162E02                                            ;
++----------------+-------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Sun Apr 11 13:22:38 2021
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 293 megabytes
+    Info: Processing ended: Sun Apr 11 13:22:41 2021
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:03
+
+

cpld/output_files/GR8RAM.done

@@ -0,0 +1 @@
+Sun Apr 11 13:22:49 2021

cpld/output_files/GR8RAM.fit.smsg

@@ -0,0 +1,4 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176244): Moving registers into LUTs to improve timing and density
+Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00

cpld/output_files/GR8RAM.fit.summary

@@ -0,0 +1,11 @@
+Fitter Status : Successful - Sun Apr 11 13:22:34 2021
+Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : GR8RAM
+Top-level Entity Name : GR8RAM
+Family : MAX II
+Device : EPM240T100C5
+Timing Models : Final
+Total logic elements : 227 / 240 ( 95 % )
+Total pins : 69 / 80 ( 86 % )
+Total virtual pins : 0
+UFM blocks : 0 / 1 ( 0 % )

cpld/output_files/GR8RAM.flow.rpt

@@ -0,0 +1,134 @@
+Flow report for GR8RAM
+Sun Apr 11 13:22:47 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------+
+; Flow Summary                                                                ;
++---------------------------+-------------------------------------------------+
+; Flow Status               ; Successful - Sun Apr 11 13:22:41 2021           ;
+; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name             ; GR8RAM                                          ;
+; Top-level Entity Name     ; GR8RAM                                          ;
+; Family                    ; MAX II                                          ;
+; Device                    ; EPM240T100C5                                    ;
+; Timing Models             ; Final                                           ;
+; Total logic elements      ; 227 / 240 ( 95 % )                              ;
+; Total pins                ; 69 / 80 ( 86 % )                                ;
+; Total virtual pins        ; 0                                               ;
+; UFM blocks                ; 0 / 1 ( 0 % )                                   ;
++---------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 04/11/2021 13:22:17 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; GR8RAM              ;
++-------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                            ;
++-------------------------------------------------+--------------------------------+---------------+-------------+------------+
+; Assignment Name                                 ; Value                          ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------------------+--------------------------------+---------------+-------------+------------+
+; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP             ; On                             ; Off           ; --          ; --         ;
+; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always                         ; Auto          ; --          ; --         ;
+; ALM_REGISTER_PACKING_EFFORT                     ; High                           ; Medium        ; --          ; --         ;
+; AUTO_PACKED_REGISTERS_MAXII                     ; Minimize Area                  ; Auto          ; --          ; --         ;
+; AUTO_RESOURCE_SHARING                           ; On                             ; Off           ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                           ; 44085571633675.161816173700648 ; --            ; --          ; --         ;
+; FINAL_PLACEMENT_OPTIMIZATION                    ; Always                         ; Automatically ; --          ; --         ;
+; FITTER_EFFORT                                   ; Standard Fit                   ; Auto Fit      ; --          ; --         ;
+; IOBANK_VCCIO                                    ; 3.3V                           ; --            ; --          ; 1          ;
+; IOBANK_VCCIO                                    ; 3.3V                           ; --            ; --          ; 2          ;
+; MAXII_OPTIMIZATION_TECHNIQUE                    ; Area                           ; Balanced      ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                          ; 85                             ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                          ; 0                              ; --            ; --          ; --         ;
+; MUX_RESTRUCTURE                                 ; On                             ; Auto          ; --          ; --         ;
+; PLACEMENT_EFFORT_MULTIPLIER                     ; 2.0                            ; 1.0           ; --          ; --         ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR           ; 3.3V                           ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY                        ; output_files                   ; --            ; --          ; --         ;
+; REMOVE_REDUNDANT_LOGIC_CELLS                    ; On                             ; Off           ; --          ; --         ;
+; ROUTER_EFFORT_MULTIPLIER                        ; 2.0                            ; 1.0           ; --          ; --         ;
+; ROUTER_REGISTER_DUPLICATION                     ; Off                            ; Auto          ; --          ; --         ;
+; SEED                                            ; 235                            ; 1             ; --          ; --         ;
+; STATE_MACHINE_PROCESSING                        ; Minimal Bits                   ; Auto          ; --          ; --         ;
+; SYNTHESIS_SEED                                  ; 123                            ; 1             ; --          ; --         ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS                   ; Off                            ; --            ; --          ; --         ;
++-------------------------------------------------+--------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:06     ; 1.0                     ; 301 MB              ; 00:00:06                           ;
+; Fitter                    ; 00:00:10     ; 1.4                     ; 382 MB              ; 00:00:09                           ;
+; Assembler                 ; 00:00:03     ; 1.0                     ; 292 MB              ; 00:00:03                           ;
+; TimeQuest Timing Analyzer ; 00:00:04     ; 1.0                     ; 278 MB              ; 00:00:04                           ;
+; Total                     ; 00:00:23     ; --                      ; --                  ; 00:00:22                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                         ;
++---------------------------+------------------+------------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++---------------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis      ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
+; Fitter                    ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
+; Assembler                 ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
+; TimeQuest Timing Analyzer ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
++---------------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
+quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+quartus_sta GR8RAM -c GR8RAM
+
+
+

cpld/output_files/GR8RAM.jdi

@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="a474eff98051f7f4d66b"/>
+  </project>
+  <file_info>
+    <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>

cpld/output_files/GR8RAM.map.rpt

@@ -0,0 +1,315 @@
+Analysis & Synthesis report for GR8RAM
+Sun Apr 11 13:22:21 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. State Machine - |GR8RAM|IS
+  9. Registers Removed During Synthesis
+ 10. General Register Statistics
+ 11. Inverted Register Statistics
+ 12. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 13. Analysis & Synthesis Messages
+ 14. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                  ;
++-----------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sun Apr 11 13:22:21 2021           ;
+; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name               ; GR8RAM                                          ;
+; Top-level Entity Name       ; GR8RAM                                          ;
+; Family                      ; MAX II                                          ;
+; Total logic elements        ; 240                                             ;
+; Total pins                  ; 69                                              ;
+; Total virtual pins          ; 0                                               ;
+; UFM blocks                  ; 0 / 1 ( 0 % )                                   ;
++-----------------------------+-------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EPM240T100C5       ;                    ;
+; Top-level entity name                                                      ; GR8RAM             ; GR8RAM             ;
+; Family name                                                                ; MAX II             ; Cyclone IV GX      ;
+; Restructure Multiplexers                                                   ; On                 ; Auto               ;
+; State Machine Processing                                                   ; Minimal Bits       ; Auto               ;
+; Remove Redundant Logic Cells                                               ; On                 ; Off                ;
+; Optimization Technique                                                     ; Area               ; Balanced           ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; On                 ; Off                ;
+; Allow Shift Register Merging across Hierarchies                            ; Always             ; Auto               ;
+; Auto Resource Sharing                                                      ; On                 ; Off                ;
+; Synthesis Seed                                                             ; 123                ; 1                  ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 2           ;
+; Maximum allowed            ; 2           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
++----------------------------+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                ;
++----------------------------------+-----------------+------------------------+-------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path  ; Library ;
++----------------------------------+-----------------+------------------------+-------------------------------+---------+
+; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ;         ;
++----------------------------------+-----------------+------------------------+-------------------------------+---------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary         ;
++---------------------------------------------+-------+
+; Resource                                    ; Usage ;
++---------------------------------------------+-------+
+; Total logic elements                        ; 240   ;
+;     -- Combinational with no register       ; 138   ;
+;     -- Register only                        ; 14    ;
+;     -- Combinational with a register        ; 88    ;
+;                                             ;       ;
+; Logic element usage by number of LUT inputs ;       ;
+;     -- 4 input functions                    ; 130   ;
+;     -- 3 input functions                    ; 30    ;
+;     -- 2 input functions                    ; 66    ;
+;     -- 1 input functions                    ; 0     ;
+;     -- 0 input functions                    ; 0     ;
+;                                             ;       ;
+; Logic elements by mode                      ;       ;
+;     -- normal mode                          ; 207   ;
+;     -- arithmetic mode                      ; 33    ;
+;     -- qfbk mode                            ; 0     ;
+;     -- register cascade mode                ; 0     ;
+;     -- synchronous clear/load mode          ; 35    ;
+;     -- asynchronous clear/load mode         ; 30    ;
+;                                             ;       ;
+; Total registers                             ; 102   ;
+; Total logic cells in carry chains           ; 37    ;
+; I/O pins                                    ; 69    ;
+; Maximum fan-out node                        ; C25M  ;
+; Maximum fan-out                             ; 99    ;
+; Total fan-out                               ; 1036  ;
+; Average fan-out                             ; 3.35  ;
++---------------------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
+; |GR8RAM                    ; 240 (240)   ; 102          ; 0          ; 69   ; 0            ; 138 (138)    ; 14 (14)           ; 88 (88)          ; 37 (37)         ; 0 (0)      ; |GR8RAM             ; work         ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type:  Minimal Bits
++-----------------------------------------------------------+
+; State Machine - |GR8RAM|IS                                ;
++--------+----------------+----------------+----------------+
+; Name   ; IS.state_bit_2 ; IS.state_bit_1 ; IS.state_bit_0 ;
++--------+----------------+----------------+----------------+
+; IS.000 ; 0              ; 0              ; 0              ;
+; IS.001 ; 0              ; 0              ; 1              ;
+; IS.100 ; 1              ; 0              ; 0              ;
+; IS.101 ; 1              ; 0              ; 1              ;
+; IS.110 ; 0              ; 1              ; 0              ;
+; IS.111 ; 0              ; 1              ; 1              ;
++--------+----------------+----------------+----------------+
+
+
++------------------------------------------------------------+
+; Registers Removed During Synthesis                         ;
++---------------------------------------+--------------------+
+; Register name                         ; Reason for Removal ;
++---------------------------------------+--------------------+
+; IS~10                                 ; Lost fanout        ;
+; Total Number of Removed Registers = 1 ;                    ;
++---------------------------------------+--------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 102   ;
+; Number of registers using Synchronous Clear  ; 10    ;
+; Number of registers using Synchronous Load   ; 25    ;
+; Number of registers using Asynchronous Clear ; 30    ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 29    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; nRCS~reg0                              ; 1       ;
+; nRAS~reg0                              ; 1       ;
+; nCAS~reg0                              ; 1       ;
+; nSWE~reg0                              ; 1       ;
+; DQML~reg0                              ; 1       ;
+; DQMH~reg0                              ; 1       ;
+; RCKE~reg0                              ; 1       ;
+; Total number of inverted registers = 7 ;         ;
++----------------------------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|PS[1]              ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |GR8RAM|SA[12]~reg0        ;
+; 20:1               ; 6 bits    ; 78 LEs        ; 24 LEs               ; 54 LEs                 ; Yes        ; |GR8RAM|SA[3]~reg0         ;
+; 20:1               ; 3 bits    ; 39 LEs        ; 18 LEs               ; 21 LEs                 ; Yes        ; |GR8RAM|SA[1]~reg0         ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |GR8RAM|WRD[0]             ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|WRD[7]             ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|RDD[1]             ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |GR8RAM|RDD[4]             ;
+; 18:1               ; 2 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |GR8RAM|DQMH~reg0          ;
+; 8:1                ; 5 bits    ; 25 LEs        ; 20 LEs               ; 5 LEs                  ; No         ; |GR8RAM|IS                 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Sun Apr 11 13:22:15 2021
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
+    Info (12023): Found entity 1: GR8RAM
+Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)
+Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
+Info (17049): 1 registers lost all their fanouts during netlist optimizations.
+Info (21057): Implemented 309 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 26 input pins
+    Info (21059): Implemented 26 output pins
+    Info (21060): Implemented 17 bidirectional pins
+    Info (21061): Implemented 240 logic cells
+Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
+Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 301 megabytes
+    Info: Processing ended: Sun Apr 11 13:22:21 2021
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:06
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
+
+

cpld/output_files/GR8RAM.map.smsg

@@ -0,0 +1,2 @@
+Warning (10273): Verilog HDL warning at GR8RAM.v(79): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at GR8RAM.v(256): extended using "x" or "z"

cpld/output_files/GR8RAM.map.summary

@@ -0,0 +1,9 @@
+Analysis & Synthesis Status : Successful - Sun Apr 11 13:22:21 2021
+Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : GR8RAM
+Top-level Entity Name : GR8RAM
+Family : MAX II
+Total logic elements : 240
+Total pins : 69
+Total virtual pins : 0
+UFM blocks : 0 / 1 ( 0 % )

cpld/output_files/GR8RAM.pin

@@ -0,0 +1,164 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (2.5V/3.3V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+CHIP  "GR8RAM"  ASSIGNED TO AN: EPM240T100C5
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+RA[4]                        : 1         : input  : 3.3-V LVTTL       :         : 2         : Y              
+RA[5]                        : 2         : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[6]                        : 3         : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[3]                        : 4         : input  : 3.3-V LVTTL       :         : 1         : Y              
+nFCS                         : 5         : output : 3.3-V LVTTL       :         : 1         : Y              
+RA[7]                        : 6         : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[8]                        : 7         : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[9]                        : 8         : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 10        : gnd    :                   :         :           :                
+GNDINT                       : 11        : gnd    :                   :         :           :                
+FCK                          : 12        : output : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : 13        : power  :                   : 2.5V/3.3V :           :                
+RA[10]                       : 14        : input  : 3.3-V LVTTL       :         : 1         : Y              
+MOSI                         : 15        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+MISO                         : 16        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RDdir                        : 17        : output : 3.3-V LVTTL       :         : 1         : N              
+GND*                         : 18        :        :                   :         : 1         :                
+GND*                         : 19        :        :                   :         : 1         :                
+GND*                         : 20        :        :                   :         : 1         :                
+GND*                         : 21        :        :                   :         : 1         :                
+TMS                          : 22        : input  :                   :         : 1         :                
+TDI                          : 23        : input  :                   :         : 1         :                
+TCK                          : 24        : input  :                   :         : 1         :                
+TDO                          : 25        : output :                   :         : 1         :                
+GND*                         : 26        :        :                   :         : 1         :                
+GND*                         : 27        :        :                   :         : 1         :                
+GND*                         : 28        :        :                   :         : 1         :                
+GND*                         : 29        :        :                   :         : 1         :                
+nRESout                      : 30        : output : 3.3-V LVTTL       :         : 1         : Y              
+VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 32        : gnd    :                   :         :           :                
+GND*                         : 33        :        :                   :         : 1         :                
+RA[11]                       : 34        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[12]                       : 35        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[13]                       : 36        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[14]                       : 37        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RA[15]                       : 38        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nIOSEL                       : 39        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nDEVSEL                      : 40        : input  : 3.3-V LVTTL       :         : 1         : Y              
+PHI0                         : 41        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nIOSTRB                      : 42        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nWE                          : 43        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nRES                         : 44        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
+GNDIO                        : 46        : gnd    :                   :         :           :                
+SD[1]                        : 47        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+GND*                         : 48        :        :                   :         : 1         :                
+GND*                         : 49        :        :                   :         : 1         :                
+SD[0]                        : 50        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+SD[4]                        : 51        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+SD[5]                        : 52        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+SD[6]                        : 53        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+SD[7]                        : 54        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+SD[3]                        : 55        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+SD[2]                        : 56        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+DQMH                         : 57        : output : 3.3-V LVTTL       :         : 2         : Y              
+nSWE                         : 58        : output : 3.3-V LVTTL       :         : 2         : Y              
+VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
+GNDIO                        : 60        : gnd    :                   :         :           :                
+nCAS                         : 61        : output : 3.3-V LVTTL       :         : 2         : Y              
+nRAS                         : 62        : output : 3.3-V LVTTL       :         : 2         : Y              
+VCCINT                       : 63        : power  :                   : 2.5V/3.3V :           :                
+C25M                         : 64        : input  : 3.3-V LVTTL       :         : 2         : Y              
+GNDINT                       : 65        : gnd    :                   :         :           :                
+RCKE                         : 66        : output : 3.3-V LVTTL       :         : 2         : Y              
+nRCS                         : 67        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[12]                       : 68        : output : 3.3-V LVTTL       :         : 2         : Y              
+SBA[0]                       : 69        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[11]                       : 70        : output : 3.3-V LVTTL       :         : 2         : Y              
+SBA[1]                       : 71        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[9]                        : 72        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[10]                       : 73        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[8]                        : 74        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[0]                        : 75        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[4]                        : 76        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[6]                        : 77        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[7]                        : 78        : output : 3.3-V LVTTL       :         : 2         : Y              
+GNDIO                        : 79        : gnd    :                   :         :           :                
+VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
+SA[1]                        : 81        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[2]                        : 82        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[5]                        : 83        : output : 3.3-V LVTTL       :         : 2         : Y              
+SA[3]                        : 84        : output : 3.3-V LVTTL       :         : 2         : Y              
+DQML                         : 85        : output : 3.3-V LVTTL       :         : 2         : Y              
+RD[0]                        : 86        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[1]                        : 87        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[2]                        : 88        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[3]                        : 89        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[4]                        : 90        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[5]                        : 91        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RD[6]                        : 92        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+GNDIO                        : 93        : gnd    :                   :         :           :                
+VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
+SetFW[1]                     : 95        : input  : 3.3-V LVTTL       :         : 2         : Y              
+SetFW[0]                     : 96        : input  : 3.3-V LVTTL       :         : 2         : Y              
+RA[2]                        : 97        : input  : 3.3-V LVTTL       :         : 2         : Y              
+RA[1]                        : 98        : input  : 3.3-V LVTTL       :         : 2         : Y              
+RD[7]                        : 99        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+RA[0]                        : 100       : input  : 3.3-V LVTTL       :         : 2         : Y              

cpld/output_files/GR8RAM.sta.summary

@@ -0,0 +1,37 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Setup 'C25M'
+Slack : -9.908
+TNS   : -697.920
+
+Type  : Setup 'PHI0'
+Slack : -1.302
+TNS   : -1.302
+
+Type  : Hold 'PHI0'
+Slack : 1.012
+TNS   : 0.000
+
+Type  : Hold 'C25M'
+Slack : 1.288
+TNS   : 0.000
+
+Type  : Recovery 'C25M'
+Slack : -4.389
+TNS   : -131.670
+
+Type  : Removal 'C25M'
+Slack : 4.835
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'C25M'
+Slack : -2.289
+TNS   : -2.289
+
+Type  : Minimum Pulse Width 'PHI0'
+Slack : -2.289
+TNS   : -2.289
+
+------------------------------------------------------------

cpld/serv_req_info.txt

@@ -0,0 +1,8 @@
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>MEM</sub_system>
+	<error>*** Fatal Error: Out of memory in module quartus.exe (1999 megabytes used)</error>
+	<date>Mon Mar 22 01:13:02 2021</date>
+	<version>Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition</version>
+</internal_error>
+

gerber/GR8RAM-BOM.csv

@@ -0,0 +1,21 @@
+Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
+C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
+C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
+FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
+H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
+H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
+J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
+J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
+J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
+R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
+R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
+RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
+RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
+SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
+U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
+U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
+U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
+U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
+U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
+U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
+U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"