idk

This reverts commit 691c076b4d.

.gitignore

@@ -6,6 +6,7 @@
 *.bak
 *.bck
 *.kicad_pcb-bak
+*.sch-bak
 *~
 _autosave-*
 *.tmp
@@ -13,6 +14,7 @@ _autosave-*
 *-save.pro
 *-save.kicad_pcb
 fp-info-cache
+GR8RAM-backups/*
 
 # Netlist files (exported from Eeschema)
 *.net
@@ -21,8 +23,8 @@ fp-info-cache
 *.dsn
 *.ses
 
-# Exported BOM files
-*.xml
-*.csv
-
 *.DS_Store
+cpld/db/GR8RAM.db_info
+cpld/db/GR8RAM.tmw_info
+cpld/GR8RAM.qws
+Documentation/~$4205AManual.docx

Documentation/Flash Map

@@ -0,0 +1,38 @@
+GR8RAM flash memory map
+
+....		-----------------------------
+7FFF		|							|
+....		|     firmware 3 (8 kB)     |
+6000		|							|
+			-----------------------------
+5FFF		|							|
+....		|     firmware 2 (8 kB)     |
+4000		|							|
+			-----------------------------
+3FFF		|							|
+....		|     firmware 1 (8 kB)     |
+2000		|							|
+			-----------------------------
+1FFF		|							|
+....		|     firmware 0 (8 kB)     |
+0000		|							|
+			-----------------------------
+
+Firmware area map (N=$0000, $2000, $4000, $6000)
+			-----------------------------
+N+1FFF		|							|
+....		|    IOSTRB bank 1 (2 kB)   |
+N+1800		|							|
+			-----------------------------
+N+17FF		|							|
+....		|    IOSEL bank 1 (2 kB)    |
+N+1000		|							|
+			-----------------------------
+N+0FFF		|							|
+....		|    IOSTRB bank 0 (2 kB)   |
+N+0800		|							|
+			-----------------------------
+N+07FF		|							|
+....		|    IOSEL bank 0 (2 kB)    |
+N+0000		|							|
+			-----------------------------

Documentation/Initialization Sequence

@@ -0,0 +1,13 @@
+Init sequence
+
+LS				SDRAM					Flash					IS
+-------------------------------------------------------------------
+$0000-$1FCE		Nothing					Nothing					0
+$1FCF			Init: Precharge			Nothing					1
+$1FD0-$1FFA		Init: AREF Pause		SPI Select				4
+$1FFB			Init: AREF Pause		Dual Read (0x3B)		5
+$1FFC			Init: AREF Pause		A[23:16] (0)			5
+$1FFD			Init: AREF Pause		A[15:08] (FW in 14:13)	5
+$1FFE			Init: AREF Pause		A[07:00] (0)			5
+$1FFF			Init: AREF Pause		Dummy					5
+$2000-$3FFF		Init: Write ROM			Shift MISO into WRD		6

Documentation/RAM Map

@@ -0,0 +1,32 @@
+GR8RAM/LibraryCard Slinky RAM memory map
+			-----------------------------
+1 FF FFFF	|							|
+. .. ....	|    reserved (16,376 kB)   |
+1 00 2000	|							|
+			-----------------------------
+1 00 1FFF	|							|
+. .. ....	|      firmware (8 kB)      |
+1 00 0000	|							|
+			-----------------------------
+0 FF FFFF	|							|
+. .. ....	|     Slinky RAM (16 MB)    |
+0 00 0000	|							|
+			-----------------------------
+
+			-----------------------------
+1 00 1FFF	|							|
+....		|    IOSTRB bank 1 (2 kB)   |
+1 00 1800	|							|
+			-----------------------------
+1 00 17FF	|							|
+....		|    IOSEL bank 1 (2 kB)    |
+1 00 1000	|							|
+			-----------------------------
+1 00 0FFF	|							|
+....		|    IOSTRB bank 0 (2 kB)   |
+1 00 0800	|							|
+			-----------------------------
+1 00 07FF	|							|
+....		|    IOSEL bank 0 (2 kB)    |
+1 00 0000	|							|
+			-----------------------------

Flash.kicad_sch

@@ -0,0 +1,711 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 338db033-7222-493c-b07e-a7cf97c3103c)
+
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+
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+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "GND_1_1"
+        (pin power_in line (at 0 0 270) (length 0) hide
+          (name "GND" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
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+    )
+  )
+
+  (junction (at 158.75 106.68) (diameter 0) (color 0 0 0 0)
+    (uuid 1a88f95e-d161-4753-b140-b5a012b485be)
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+    (uuid 3416b871-7601-4f2d-9c27-d5f5edd75a6a)
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+    (effects (font (size 1.27 1.27)) (justify right bottom))
+    (uuid 93977d39-89c2-44e6-bc89-4227aa84e968)
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+    (effects (font (size 1.27 1.27)) (justify right bottom))
+    (uuid dc132665-d1e0-4b8b-8996-065a4c2cb7aa)
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+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid f7988507-b7fe-4f02-9eb3-187c7062c8c8)
+  )
+
+  (hierarchical_label "F~{CS}" (shape input) (at 74.93 54.61 180)
+    (effects (font (size 1.27 1.27)) (justify right))
+    (uuid 01429c06-83ed-414a-a40d-4ba390ac8fb8)
+  )
+  (hierarchical_label "MISO" (shape output) (at 96.52 85.09 180)
+    (effects (font (size 1.27 1.27)) (justify right))
+    (uuid 0cba2933-e2d7-4a4b-9a47-919a981eb044)
+  )
+  (hierarchical_label "F~{CS}" (shape input) (at 96.52 82.55 180)
+    (effects (font (size 1.27 1.27)) (justify right))
+    (uuid 16a6575c-5439-477a-bee5-d21abf841a68)
+  )
+  (hierarchical_label "MOSI" (shape input) (at 102.87 62.23 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 35c22462-6f01-48dc-90d5-2a240506684d)
+  )
+  (hierarchical_label "MOSI" (shape input) (at 109.22 90.17 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 3600b759-341c-4990-afb4-b75a0139da56)
+  )
+  (hierarchical_label "MISO" (shape output) (at 74.93 57.15 180)
+    (effects (font (size 1.27 1.27)) (justify right))
+    (uuid a20adb77-ed8b-465b-9963-0f26585d4a9c)
+  )
+  (hierarchical_label "FCK" (shape input) (at 102.87 59.69 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid bec172b6-ac1f-49a4-9dc2-08da84ed71c2)
+  )
+  (hierarchical_label "FCK" (shape input) (at 119.38 87.63 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid f69edbe5-6379-4060-9db0-cf4a0df39628)
+  )
+
+  (symbol (lib_id "Device:R_Pack04") (at 153.67 109.22 270) (mirror x) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid 06a85e9e-5bf4-4144-9ff8-0784f7b0da68)
+    (property "Reference" "RN?" (id 0) (at 153.67 104.14 90))
+    (property "Value" "4x10k" (id 1) (at 153.67 116.84 90))
+    (property "Footprint" "stdpads:R4_0402" (id 2) (at 153.67 102.235 90)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 153.67 109.22 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "LCSC Part" "C25725" (id 4) (at 153.67 109.22 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 19d5f76d-a4a0-4344-8d2d-d42edac87a6e))
+    (pin "2" (uuid e41b2af2-2b54-4903-b0a8-6a14a012f500))
+    (pin "3" (uuid dd44d10e-69da-4fd7-a162-ac12fcc397b2))
+    (pin "4" (uuid c4941c42-e1b3-4cb2-9653-35644c33526f))
+    (pin "5" (uuid 19de293e-6f7b-4d21-9dc8-9aeba311d73d))
+    (pin "6" (uuid c96bf30c-2342-46a2-8aac-82843097120d))
+    (pin "7" (uuid c7355bd4-47b9-4b69-8e2d-77b4552d0701))
+    (pin "8" (uuid 20df0ca2-4e3b-4a3e-9112-2c365f662309))
+  )
+
+  (symbol (lib_id "Device:R_Small") (at 116.84 87.63 270) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid 10ce3bb5-218d-4caa-96bd-811a943cb53e)
+    (property "Reference" "R?" (id 0) (at 116.84 83.82 90))
+    (property "Value" "47" (id 1) (at 116.84 86.36 90)
+      (effects (font (size 1.27 1.27)) (justify bottom))
+    )
+    (property "Footprint" "stdpads:R_0603" (id 2) (at 116.84 87.63 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 116.84 87.63 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "LCSC Part" "" (id 4) (at 116.84 87.63 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid d98de1d0-d0f2-4e49-8cd6-bf9def14e1ed))
+    (pin "2" (uuid 74d5557d-bb63-4850-8502-4e35b7adfc43))
+  )
+
+  (symbol (lib_id "GW_RAM:SPIFlash-SO-8") (at 88.9 59.69 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid 2082e0e4-9f8f-40a8-b863-089c07cb0131)
+    (property "Reference" "U?" (id 0) (at 88.9 50.8 0))
+    (property "Value" "W25Q128JVSIQ" (id 1) (at 88.9 66.04 0))
+    (property "Footprint" "stdpads:SOIC-8_5.3mm" (id 2) (at 88.9 67.31 0)
+      (effects (font (size 1.27 1.27)) (justify top) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 88.9 59.69 0)
+      (effects (font (size 1.27 1.27)) (justify top) hide)
+    )
+    (property "LCSC Part" "C164122" (id 4) (at 88.9 59.69 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid f81f5ef0-24ec-417b-8434-c9f1d2aeb6b6))
+    (pin "2" (uuid 561876a4-2b38-42ee-8263-989ab1b07347))
+    (pin "3" (uuid 65582bb9-e0a4-4ddb-809d-78b83f43fcc3))
+    (pin "4" (uuid 22369056-74fd-434c-a636-3f09b2c3ce1e))
+    (pin "5" (uuid eebafad4-6c2e-42f2-979f-91ea991c18c4))
+    (pin "6" (uuid de9039d2-c4db-43bb-b87e-b63154be598f))
+    (pin "7" (uuid e6506ff1-76aa-41fd-a2c6-bcbcd8532d89))
+    (pin "8" (uuid cc0c2023-0092-4999-9c93-7f92fc9755cd))
+  )
+
+  (symbol (lib_id "power:+3V3") (at 158.75 106.68 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid 31034218-c614-477b-93ce-017b481cabca)
+    (property "Reference" "#PWR?" (id 0) (at 158.75 110.49 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "+3V3" (id 1) (at 158.75 102.87 0))
+    (property "Footprint" "" (id 2) (at 158.75 106.68 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 158.75 106.68 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 9e7dd23f-b28f-4422-adc0-ffd72f356804))
+  )
+
+  (symbol (lib_id "power:+3V3") (at 109.22 82.55 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid 333e6a54-9423-463b-9330-602daf448467)
+    (property "Reference" "#PWR?" (id 0) (at 109.22 86.36 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "+3V3" (id 1) (at 109.22 78.74 0))
+    (property "Footprint" "" (id 2) (at 109.22 82.55 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 109.22 82.55 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid e021b3fc-45f4-4295-9ccb-f7e885af5a98))
+  )
+
+  (symbol (lib_id "Connector_Generic:Conn_02x05_Odd_Even") (at 101.6 87.63 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid 6b67c587-d478-49d7-b921-d4dc59485d9d)
+    (property "Reference" "J?" (id 0) (at 102.87 80.01 0))
+    (property "Value" "Flash" (id 1) (at 102.87 95.25 0))
+    (property "Footprint" "Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical" (id 2) (at 101.6 87.63 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 101.6 87.63 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 01926532-1189-44af-8b1c-a203d15bf666))
+    (pin "10" (uuid 28efda38-8d08-41ba-a2a9-66fb1cee76d2))
+    (pin "2" (uuid 493171e7-e51b-409c-83c8-04d3a8124794))
+    (pin "3" (uuid 5da258e9-bec9-464d-97fd-9d90c9292603))
+    (pin "4" (uuid e4e12670-95ca-4032-b81f-fceb19f51ab0))
+    (pin "5" (uuid 01dc48ba-7884-45db-9bbd-2aaebdb9450b))
+    (pin "6" (uuid 9d1057a1-660f-4ff1-84d4-77f0a864ba4e))
+    (pin "7" (uuid ef01915a-b0ec-4362-b25e-a8447d9c9487))
+    (pin "8" (uuid 5f2e213c-cff9-48c0-85cf-a68eb46a0955))
+    (pin "9" (uuid 2d01030a-9b84-4fe6-8bab-90674c68464a))
+  )
+
+  (symbol (lib_id "power:+3V3") (at 102.87 54.61 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid cf6ca64f-914b-4e73-a137-483d4591d37a)
+    (property "Reference" "#PWR?" (id 0) (at 102.87 58.42 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "+3V3" (id 1) (at 102.87 50.8 0))
+    (property "Footprint" "" (id 2) (at 102.87 54.61 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 102.87 54.61 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 717e6592-a7a1-44b3-86ed-4a7db50428b2))
+  )
+
+  (symbol (lib_id "power:GND") (at 74.93 62.23 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid d8f35148-ef45-4722-9e07-509ab8d3695e)
+    (property "Reference" "#PWR?" (id 0) (at 74.93 68.58 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 74.93 66.04 0))
+    (property "Footprint" "" (id 2) (at 74.93 62.23 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 74.93 62.23 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 1cecbf72-1147-457f-a6fd-d4a166ff67d2))
+  )
+
+  (symbol (lib_id "power:GND") (at 93.98 90.17 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid e0072c1b-6727-4e16-9dba-1bf65c7024c3)
+    (property "Reference" "#PWR?" (id 0) (at 93.98 96.52 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 93.98 93.98 0))
+    (property "Footprint" "" (id 2) (at 93.98 90.17 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 93.98 90.17 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 0b3b63b6-6205-4188-9ef9-e689bcd5562d))
+  )
+)

GR8RAM

@@ -0,0 +1,21 @@
+Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
+C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
+C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
+FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
+H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
+H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
+J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
+J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
+J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
+R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
+R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
+RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
+RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
+SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
+U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
+U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
+U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
+U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
+U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
+U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
+U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"

GR8RAM-cache.lib

@@ -1,38 +1,38 @@
 EESchema-LIBRARY Version 2.4
 #encoding utf-8
 #
-# Connector_AVR-JTAG-10
+# Connector_Generic_Conn_02x05_Odd_Even
 #
-DEF Connector_AVR-JTAG-10 J 0 40 Y Y 1 F N
-F0 "J" 175 500 50 H V L CNN
-F1 "Connector_AVR-JTAG-10" 100 -500 50 H V L CNN
-F2 "" -150 150 50 V I C CNN
-F3 "" -1275 -550 50 H I C CNN
+DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
+F0 "J" 50 300 50 H V C CNN
+F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
 $FPLIST
- IDC?Header*2x05*
- Pin?Header*2x05*
+ Connector*:*_2x??_*
 $ENDFPLIST
 DRAW
-S -105 450 -95 420 0 1 0 N
-S -5 -420 5 -450 0 1 0 N
-S -5 450 5 420 0 1 0 N
-S 350 -195 320 -205 0 1 0 N
-S 350 -95 320 -105 0 1 0 N
-S 350 5 320 -5 0 1 0 N
-S 350 105 320 95 0 1 0 N
-S 350 205 320 195 0 1 0 N
-S 350 305 320 295 0 1 0 N
-S 350 450 -350 -450 0 1 10 f
-X TCK 1 500 100 150 L 50 50 1 1 P
-X GND 10 0 -600 150 U 50 50 1 1 W
-X GND 2 0 -600 150 U 50 50 1 1 P N
-X TDO 3 500 -100 150 L 50 50 1 1 P
-X VREF 4 -100 600 150 D 50 50 1 1 P
-X TMS 5 500 0 150 L 50 50 1 1 P
-X ~SRST 6 500 300 150 L 50 50 1 1 P
-X VCC 7 0 600 150 D 50 50 1 1 W
-X ~TRST 8 500 200 150 L 50 50 1 1 P
-X TDI 9 500 -200 150 L 50 50 1 1 P
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 205 0 195 1 1 6 N
+S -50 250 150 -250 1 1 10 f
+S 150 -195 100 -205 1 1 6 N
+S 150 -95 100 -105 1 1 6 N
+S 150 5 100 -5 1 1 6 N
+S 150 105 100 95 1 1 6 N
+S 150 205 100 195 1 1 6 N
+X Pin_1 1 -200 200 150 R 50 50 1 1 P
+X Pin_10 10 300 -200 150 L 50 50 1 1 P
+X Pin_2 2 300 200 150 L 50 50 1 1 P
+X Pin_3 3 -200 100 150 R 50 50 1 1 P
+X Pin_4 4 300 100 150 L 50 50 1 1 P
+X Pin_5 5 -200 0 150 R 50 50 1 1 P
+X Pin_6 6 300 0 150 L 50 50 1 1 P
+X Pin_7 7 -200 -100 150 R 50 50 1 1 P
+X Pin_8 8 300 -100 150 L 50 50 1 1 P
+X Pin_9 9 -200 -200 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
@@ -151,26 +151,6 @@ X Pin_9 9 -200 400 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Device_CP_Small
-#
-DEF Device_CP_Small C 0 10 N N 1 F N
-F0 "C" 10 70 50 H V L CNN
-F1 "Device_CP_Small" 10 -80 50 H V L CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- CP_*
-$ENDFPLIST
-DRAW
-S -60 -12 60 -27 0 1 0 F
-S -60 27 60 12 0 1 0 N
-P 2 0 1 0 -50 60 -30 60 N
-P 2 0 1 0 -40 50 -40 70 N
-X ~ 1 0 100 73 D 50 50 1 1 P
-X ~ 2 0 -100 73 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
 # Device_C_Small
 #
 DEF Device_C_Small C 0 10 N N 1 F N
@@ -189,6 +169,354 @@ X ~ 2 0 -100 80 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# Device_R_Pack04
+#
+DEF Device_R_Pack04 RN 0 0 Y N 1 F N
+F0 "RN" -300 0 50 V V C CNN
+F1 "Device_R_Pack04" 200 0 50 V V C CNN
+F2 "" 275 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ DIP*
+ SOIC*
+$ENDFPLIST
+DRAW
+S -250 -95 150 95 0 1 10 f
+S -225 75 -175 -75 0 1 10 N
+S -125 75 -75 -75 0 1 10 N
+S -25 75 25 -75 0 1 10 N
+S 75 75 125 -75 0 1 10 N
+P 2 0 1 0 -200 -100 -200 -75 N
+P 2 0 1 0 -200 75 -200 100 N
+P 2 0 1 0 -100 -100 -100 -75 N
+P 2 0 1 0 -100 75 -100 100 N
+P 2 0 1 0 0 -100 0 -75 N
+P 2 0 1 0 0 75 0 100 N
+P 2 0 1 0 100 -100 100 -75 N
+P 2 0 1 0 100 75 100 100 N
+X R1.1 1 -200 -200 100 U 50 50 1 1 P
+X R2.1 2 -100 -200 100 U 50 50 1 1 P
+X R3.1 3 0 -200 100 U 50 50 1 1 P
+X R4.1 4 100 -200 100 U 50 50 1 1 P
+X R4.2 5 100 200 100 D 50 50 1 1 P
+X R3.2 6 0 200 100 D 50 50 1 1 P
+X R2.2 7 -100 200 100 D 50 50 1 1 P
+X R1.2 8 -200 200 100 D 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R_Small
+#
+DEF Device_R_Small R 0 10 N N 1 F N
+F0 "R" 30 20 50 H V L CNN
+F1 "Device_R_Small" 30 -40 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -30 70 30 -70 0 1 8 N
+X ~ 1 0 100 30 D 50 50 1 1 P
+X ~ 2 0 -100 30 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_741G125GW
+#
+DEF GW_Logic_741G125GW U 0 40 Y Y 1 F N
+F0 "U" 0 250 50 H V C CNN
+F1 "GW_Logic_741G125GW" 0 -250 50 H V C CNN
+F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
+F3 "" 0 -200 60 H I C CNN
+DRAW
+S 200 -200 -200 200 0 1 10 f
+X ~OE~ 1 -400 100 200 R 50 50 1 1 I
+X A 2 -400 0 200 R 50 50 1 1 I
+X GND 3 -400 -100 200 R 50 50 1 1 W
+X Y 4 400 -100 200 L 50 50 1 1 O
+X Vcc 5 400 100 200 L 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_74245
+#
+DEF GW_Logic_74245 U 0 40 Y Y 1 F N
+F0 "U" 0 600 50 H V C CNN
+F1 "GW_Logic_74245" 0 -600 50 H V C CNN
+F2 "" 0 -650 50 H I C TNN
+F3 "" 0 100 60 H I C CNN
+DRAW
+S -200 550 200 -550 0 1 10 f
+X AtoB 1 -400 450 200 R 50 50 1 1 I
+X GND 10 -400 -450 200 R 50 50 1 1 W
+X B7 11 400 -450 200 L 50 50 1 1 B
+X B6 12 400 -350 200 L 50 50 1 1 B
+X B5 13 400 -250 200 L 50 50 1 1 B
+X B4 14 400 -150 200 L 50 50 1 1 B
+X B3 15 400 -50 200 L 50 50 1 1 B
+X B2 16 400 50 200 L 50 50 1 1 B
+X B1 17 400 150 200 L 50 50 1 1 B
+X B0 18 400 250 200 L 50 50 1 1 B
+X ~OE~ 19 400 350 200 L 50 50 1 1 I
+X A0 2 -400 350 200 R 50 50 1 1 B
+X Vcc 20 400 450 200 L 50 50 1 1 W
+X A1 3 -400 250 200 R 50 50 1 1 B
+X A2 4 -400 150 200 R 50 50 1 1 B
+X A3 5 -400 50 200 R 50 50 1 1 B
+X A4 6 -400 -50 200 R 50 50 1 1 B
+X A5 7 -400 -150 200 R 50 50 1 1 B
+X A6 8 -400 -250 200 R 50 50 1 1 B
+X A7 9 -400 -350 200 R 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# GW_Logic_Oscillator_4P
+#
+DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
+F0 "U" 0 250 50 H V C CNN
+F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -250 200 250 -100 0 1 10 f
+X EN 1 -350 100 100 R 50 50 1 1 I
+X GND 2 -350 0 100 R 50 50 1 1 W
+X Output 3 350 0 100 L 50 50 1 1 O
+X Vdd 4 350 100 100 L 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# GW_PLD_EPM240T100
+#
+DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 F N
+F0 "U" 0 50 50 H V C CNN
+F1 "GW_PLD_EPM240T100" 0 -50 50 H V C CNN
+F2 "stdpads:TQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ *QFP*P0.5mm*
+$ENDFPLIST
+DRAW
+S -800 2200 800 -2200 1 1 10 f
+X IO2_1 1 1000 2100 200 L 50 50 1 1 B
+X GNDIO 10 -200 -2400 200 U 50 50 1 1 W
+X IO2_100 100 1000 -2000 200 L 50 50 1 1 B
+X GNDINT 11 -400 -2400 200 U 50 50 1 1 W
+X IO1_12/GCLK0 12 -1000 1400 200 R 50 50 1 1 B C
+X VCCINT 13 -400 2400 200 D 50 50 1 1 W
+X IO1_14/GCLK1 14 -1000 1300 200 R 50 50 1 1 B C
+X IO1_15 15 -1000 1200 200 R 50 50 1 1 B
+X IO1_16 16 -1000 1100 200 R 50 50 1 1 B
+X IO1_17 17 -1000 1000 200 R 50 50 1 1 B
+X IO1_18 18 -1000 900 200 R 50 50 1 1 B
+X IO1_19 19 -1000 800 200 R 50 50 1 1 B
+X IO1_2 2 -1000 2100 200 R 50 50 1 1 B
+X IO1_20 20 -1000 700 200 R 50 50 1 1 B
+X IO1_21 21 -1000 600 200 R 50 50 1 1 B
+X TMS 22 -1000 -1700 200 R 50 50 1 1 I
+X TDI 23 -1000 -1800 200 R 50 50 1 1 I
+X TCK 24 -1000 -1900 200 R 50 50 1 1 I C
+X TDO 25 -1000 -2000 200 R 50 50 1 1 O
+X IO1_26 26 -1000 500 200 R 50 50 1 1 B
+X IO1_27 27 -1000 400 200 R 50 50 1 1 B
+X IO1_28 28 -1000 300 200 R 50 50 1 1 B
+X IO1_29 29 -1000 200 200 R 50 50 1 1 B
+X IO1_3 3 -1000 2000 200 R 50 50 1 1 B
+X IO1_30 30 -1000 100 200 R 50 50 1 1 B
+X VCCIO1 31 -100 2400 200 D 50 50 1 1 W
+X GNDIO 32 -100 -2400 200 U 50 50 1 1 W
+X IO1_33 33 -1000 0 200 R 50 50 1 1 B
+X IO1_34 34 -1000 -100 200 R 50 50 1 1 B
+X IO1_35 35 -1000 -200 200 R 50 50 1 1 B
+X IO1_36 36 -1000 -300 200 R 50 50 1 1 B
+X IO1_37 37 -1000 -400 200 R 50 50 1 1 B
+X IO1_38 38 -1000 -500 200 R 50 50 1 1 B
+X IO1_39 39 -1000 -600 200 R 50 50 1 1 B
+X IO1_4 4 -1000 1900 200 R 50 50 1 1 B
+X IO1_40 40 -1000 -700 200 R 50 50 1 1 B
+X IO1_41 41 -1000 -800 200 R 50 50 1 1 B
+X IO1_42 42 -1000 -900 200 R 50 50 1 1 B
+X IO1_43/DEV_OE 43 -1000 -1000 200 R 50 50 1 1 B
+X IO1_44/DEV_CLRn 44 -1000 -1100 200 R 50 50 1 1 B
+X VCCIO1 45 0 2400 200 D 50 50 1 1 W
+X GNDIO 46 0 -2400 200 U 50 50 1 1 W
+X IO1_47 47 -1000 -1200 200 R 50 50 1 1 B
+X IO1_48 48 -1000 -1300 200 R 50 50 1 1 B
+X IO1_49 49 -1000 -1400 200 R 50 50 1 1 B
+X IO1_5 5 -1000 1800 200 R 50 50 1 1 B
+X IO1_50 50 -1000 -1500 200 R 50 50 1 1 B
+X IO1_51 51 -1000 -1600 200 R 50 50 1 1 B
+X IO2_52 52 1000 2000 200 L 50 50 1 1 B
+X IO2_53 53 1000 1900 200 L 50 50 1 1 B
+X IO2_54 54 1000 1800 200 L 50 50 1 1 B
+X IO2_55 55 1000 1700 200 L 50 50 1 1 B
+X IO2_56 56 1000 1600 200 L 50 50 1 1 B
+X IO2_57 57 1000 1500 200 L 50 50 1 1 B
+X IO2_58 58 1000 1400 200 L 50 50 1 1 B
+X VCCIO2 59 100 2400 200 D 50 50 1 1 W
+X IO1_6 6 -1000 1700 200 R 50 50 1 1 B
+X GNDIO 60 100 -2400 200 U 50 50 1 1 W
+X IO2_61 61 1000 1300 200 L 50 50 1 1 B
+X IO2_62/GCLK2 62 1000 1200 200 L 50 50 1 1 B C
+X VCCINT 63 -300 2400 200 D 50 50 1 1 W
+X IO2_64/GCLK3 64 1000 1100 200 L 50 50 1 1 B C
+X GNDINT 65 -300 -2400 200 U 50 50 1 1 W
+X IO2_66 66 1000 1000 200 L 50 50 1 1 B
+X IO2_67 67 1000 900 200 L 50 50 1 1 B
+X IO2_68 68 1000 800 200 L 50 50 1 1 B
+X IO2_69 69 1000 700 200 L 50 50 1 1 B
+X IO1_7 7 -1000 1600 200 R 50 50 1 1 B
+X IO2_70 70 1000 600 200 L 50 50 1 1 B
+X IO2_71 71 1000 500 200 L 50 50 1 1 B
+X IO2_72 72 1000 400 200 L 50 50 1 1 B
+X IO2_73 73 1000 300 200 L 50 50 1 1 B
+X IO2_74 74 1000 200 200 L 50 50 1 1 B
+X IO2_75 75 1000 100 200 L 50 50 1 1 B
+X IO2_76 76 1000 0 200 L 50 50 1 1 B
+X IO2_77 77 1000 -100 200 L 50 50 1 1 B
+X IO2_78 78 1000 -200 200 L 50 50 1 1 B
+X GNDIO 79 200 -2400 200 U 50 50 1 1 W
+X IO1_8 8 -1000 1500 200 R 50 50 1 1 B
+X VCCIO2 80 200 2400 200 D 50 50 1 1 W
+X IO2_81 81 1000 -300 200 L 50 50 1 1 B
+X IO2_82 82 1000 -400 200 L 50 50 1 1 B
+X IO2_83 83 1000 -500 200 L 50 50 1 1 B
+X IO2_84 84 1000 -600 200 L 50 50 1 1 B
+X IO2_85 85 1000 -700 200 L 50 50 1 1 B
+X IO2_86 86 1000 -800 200 L 50 50 1 1 B
+X IO2_87 87 1000 -900 200 L 50 50 1 1 B
+X IO2_88 88 1000 -1000 200 L 50 50 1 1 B
+X IO2_89 89 1000 -1100 200 L 50 50 1 1 B
+X VCCIO1 9 -200 2400 200 D 50 50 1 1 W
+X IO2_90 90 1000 -1200 200 L 50 50 1 1 B
+X IO2_91 91 1000 -1300 200 L 50 50 1 1 B
+X IO2_92 92 1000 -1400 200 L 50 50 1 1 B
+X GNDIO 93 300 -2400 200 U 50 50 1 1 W
+X VCCIO2 94 300 2400 200 D 50 50 1 1 W
+X IO2_95 95 1000 -1500 200 L 50 50 1 1 B
+X IO2_96 96 1000 -1600 200 L 50 50 1 1 B
+X IO2_97 97 1000 -1700 200 L 50 50 1 1 B
+X IO2_98 98 1000 -1800 200 L 50 50 1 1 B
+X IO2_99 99 1000 -1900 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# GW_Power_AP2125
+#
+DEF GW_Power_AP2125 U 0 40 Y Y 1 F N
+F0 "U" 0 250 50 H V C CNN
+F1 "GW_Power_AP2125" 0 -250 50 H V C CNN
+F2 "stdpads:SOT-23" 0 -300 50 H I C TNN
+F3 "" 0 -100 60 H I C CNN
+DRAW
+S -250 200 250 -200 0 1 10 f
+X GND 1 -450 -100 200 R 50 50 1 1 W
+X Vout 2 450 100 200 L 50 50 1 1 w
+X Vin 3 -450 100 200 R 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# GW_RAM_SDRAM-16Mx16-TSOP2-54
+#
+DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
+F0 "U" 0 1150 50 H V C CNN
+F1 "GW_RAM_SDRAM-16Mx16-TSOP2-54" 0 0 50 V V C CNN
+F2 "stdpads:Winbond_TSOPII-54" 0 -1650 50 H I C CIN
+F3 "" 0 -250 50 H I C CNN
+DRAW
+S -300 1100 300 -1400 0 1 10 f
+X VDD 1 -500 1000 200 R 50 50 1 1 W
+X DQ5 10 500 500 200 L 50 50 1 1 B
+X DQ6 11 500 400 200 L 50 50 1 1 B
+X VSSQ 12 -500 -1300 200 R 50 50 1 1 W N
+X DQ7 13 500 300 200 L 50 50 1 1 B
+X VDD 14 -500 1000 200 R 50 50 1 1 W N
+X DQML 15 500 -600 200 L 50 50 1 1 I
+X ~WE~ 16 500 -1100 200 L 50 50 1 1 I
+X ~CAS~ 17 500 -1200 200 L 50 50 1 1 I
+X ~RAS~ 18 500 -1300 200 L 50 50 1 1 I
+X ~CS~ 19 500 -1000 200 L 50 50 1 1 I
+X DQ0 2 500 1000 200 L 50 50 1 1 B
+X BA0 20 -500 -600 200 R 50 50 1 1 I
+X BA1 21 -500 -700 200 R 50 50 1 1 I
+X A10 22 -500 -300 200 R 50 50 1 1 I
+X A0 23 -500 700 200 R 50 50 1 1 I
+X A1 24 -500 600 200 R 50 50 1 1 I
+X A2 25 -500 500 200 R 50 50 1 1 I
+X A3 26 -500 400 200 R 50 50 1 1 I
+X VDD 27 -500 1000 200 R 50 50 1 1 W N
+X VSS 28 -500 -1200 200 R 50 50 1 1 W
+X A4 29 -500 300 200 R 50 50 1 1 I
+X VDDQ 3 -500 900 200 R 50 50 1 1 W
+X A5 30 -500 200 200 R 50 50 1 1 I
+X A6 31 -500 100 200 R 50 50 1 1 I
+X A7 32 -500 0 200 R 50 50 1 1 I
+X A8 33 -500 -100 200 R 50 50 1 1 I
+X A9 34 -500 -200 200 R 50 50 1 1 I
+X A11 35 -500 -400 200 R 50 50 1 1 I
+X A12 36 -500 -500 200 R 50 50 1 1 I
+X CKE 37 -500 -900 200 R 50 50 1 1 I
+X CLK 38 -500 -1000 200 R 50 50 1 1 I
+X DQMH 39 500 -700 200 L 50 50 1 1 I
+X DQ1 4 500 900 200 L 50 50 1 1 B
+X VSS 41 -500 -1200 200 R 50 50 1 1 W N
+X DQ8 42 500 200 200 L 50 50 1 1 B
+X VDDQ 43 -500 900 200 R 50 50 1 1 W N
+X DQ9 44 500 100 200 L 50 50 1 1 B
+X DQ10 45 500 0 200 L 50 50 1 1 B
+X VSSQ 46 -500 -1300 200 R 50 50 1 1 W N
+X DQ11 47 500 -100 200 L 50 50 1 1 B
+X DQ12 48 500 -200 200 L 50 50 1 1 B
+X VDDQ 49 -500 900 200 R 50 50 1 1 W N
+X DQ2 5 500 800 200 L 50 50 1 1 B
+X DQ13 50 500 -300 200 L 50 50 1 1 B
+X DQ14 51 500 -400 200 L 50 50 1 1 B
+X VSSQ 52 -500 -1300 200 R 50 50 1 1 W N
+X DQ15 53 500 -500 200 L 50 50 1 1 B
+X VSS 54 -500 -1200 200 R 50 50 1 1 W N
+X VSSQ 6 -500 -1300 200 R 50 50 1 1 W
+X DQ3 7 500 700 200 L 50 50 1 1 B
+X DQ4 8 500 600 200 L 50 50 1 1 B
+X VDDQ 9 -500 900 200 R 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# GW_RAM_SPIFlash-SO-8
+#
+DEF GW_RAM_SPIFlash-SO-8 U 0 40 Y Y 1 F N
+F0 "U" 0 350 50 H V C CNN
+F1 "GW_RAM_SPIFlash-SO-8" 0 -250 50 H V C CNN
+F2 "stdpads:Hybrid_SPIFlash_SOIC-8_SOIC-16" 0 -300 50 H I C TNN
+F3 "" 0 0 50 H I C TNN
+DRAW
+S -350 300 350 -200 0 1 10 f
+X ~CS~ 1 -550 200 200 R 50 50 1 1 I
+X DO/IO1 2 -550 100 200 R 50 50 1 1 B
+X ~WP~/IO2 3 -550 0 200 R 50 50 1 1 B
+X GND 4 -550 -100 200 R 50 50 1 1 W
+X DI/IO0 5 550 -100 200 L 50 50 1 1 B
+X CLK 6 550 0 200 L 50 50 1 1 I
+X ~HLD~/IO3 7 550 100 200 L 50 50 1 1 B
+X Vcc 8 550 200 200 L 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# Mechanical_Fiducial
+#
+DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
+F0 "FID" 0 200 50 H V C CNN
+F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Fiducial*
+$ENDFPLIST
+DRAW
+C 0 0 50 0 1 20 f
+ENDDRAW
+ENDDEF
+#
 # Mechanical_MountingHole
 #
 DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
@@ -220,6 +548,31 @@ X 1 1 0 -100 100 U 50 50 1 1 I
 ENDDRAW
 ENDDEF
 #
+# Switch_SW_DIP_x02
+#
+DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
+F0 "SW" 0 250 50 H V C CNN
+F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ SW?DIP?x2*
+$ENDFPLIST
+DRAW
+C -80 0 20 0 0 0 N
+C -80 100 20 0 0 0 N
+C 80 0 20 0 0 0 N
+C 80 100 20 0 0 0 N
+S -150 200 150 -100 0 1 10 f
+P 2 0 0 0 -60 5 93 46 N
+P 2 0 0 0 -60 105 93 146 N
+X ~ 1 -300 100 200 R 50 50 1 1 P
+X ~ 2 -300 0 200 R 50 50 1 1 P
+X ~ 3 300 0 200 L 50 50 1 1 P
+X ~ 4 300 100 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # power_+12V
 #
 DEF power_+12V #PWR 0 0 Y Y 1 F P
@@ -235,6 +588,22 @@ X +12V 1 0 0 0 U 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
+# power_+3V3
+#
+DEF power_+3V3 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+3V3" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
 # power_+5V
 #
 DEF power_+5V #PWR 0 0 Y Y 1 F P
@@ -289,194 +658,4 @@ X GND 1 0 0 0 D 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
-# stdparts_39F040
-#
-DEF stdparts_39F040 U 0 20 Y Y 1 F N
-F0 "U" 0 1050 50 H V C CNN
-F1 "stdparts_39F040" 0 0 50 V V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-S -300 1000 300 -1000 0 1 10 f
-X GND 16 500 -900 200 L 50 50 0 0 W
-X VCC 32 500 900 200 L 50 50 0 0 W
-X A18 1 -500 -900 200 R 50 50 1 1 I
-X A2 10 -500 700 200 R 50 50 1 1 I
-X A1 11 -500 800 200 R 50 50 1 1 I
-X A0 12 -500 900 200 R 50 50 1 1 I
-X D0 13 500 700 200 L 50 50 1 1 T
-X D1 14 500 600 200 L 50 50 1 1 T
-X D2 15 500 500 200 L 50 50 1 1 T
-X D3 17 500 400 200 L 50 50 1 1 T
-X D4 18 500 300 200 L 50 50 1 1 T
-X D5 19 500 200 200 L 50 50 1 1 T
-X A16 2 -500 -700 200 R 50 50 1 1 I
-X D6 20 500 100 200 L 50 50 1 1 T
-X D7 21 500 0 200 L 50 50 1 1 T
-X ~CS~ 22 500 -400 200 L 50 50 1 1 I L
-X A10 23 -500 -100 200 R 50 50 1 1 I
-X ~OE~ 24 500 -600 200 L 50 50 1 1 I L
-X A11 25 -500 -200 200 R 50 50 1 1 I
-X A9 26 -500 0 200 R 50 50 1 1 I
-X A8 27 -500 100 200 R 50 50 1 1 I
-X A13 28 -500 -400 200 R 50 50 1 1 I
-X A14 29 -500 -500 200 R 50 50 1 1 I
-X A15 3 -500 -600 200 R 50 50 1 1 I
-X A17 30 -500 -800 200 R 50 50 1 1 I
-X ~WE~ 31 500 -500 200 L 50 50 1 1 I L
-X A12 4 -500 -300 200 R 50 50 1 1 I
-X A7 5 -500 200 200 R 50 50 1 1 I
-X A6 6 -500 300 200 R 50 50 1 1 I
-X A5 7 -500 400 200 R 50 50 1 1 I
-X A4 8 -500 500 200 R 50 50 1 1 I
-X A3 9 -500 600 200 R 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# stdparts_AS4C4M4
-#
-DEF stdparts_AS4C4M4 U 0 20 Y Y 1 F N
-F0 "U" 0 800 50 H V C CNN
-F1 "stdparts_AS4C4M4" 0 0 50 V V C CNN
-F2 "Package_SO:TSOP-II-44_10.16x18.41mm_P0.8mm" 0 -900 50 H I C CNN
-F3 "" 0 -450 50 H I C CNN
-$FPLIST
- SOJ*10.16x23.49mm*P1.27mm*
-$ENDFPLIST
-DRAW
-S -300 750 300 -850 0 1 10 f
-X A4 1 -400 250 100 R 50 50 1 1 I
-X I/O2 11 400 250 100 L 50 50 1 1 B
-X VDD 11 400 650 100 L 50 50 1 1 W
-X GND 12 -400 -750 100 R 50 50 1 1 P N
-X I/O3 12 400 150 100 L 50 50 1 1 B
-X NC 15 -400 -550 100 R 50 50 1 1 N N
-X NC 16 -400 -550 100 R 50 50 1 1 N N
-X ~WE~ 17 400 -650 100 L 50 50 1 1 I
-X A3 2 -400 350 100 R 50 50 1 1 I
-X I/O4 25 400 50 100 L 50 50 1 1 B
-X I/O5 26 400 -50 100 L 50 50 1 1 B
-X A10 27 -400 -350 100 R 50 50 1 1 I
-X A9 28 -400 -250 100 R 50 50 1 1 I
-X I/O6 29 400 -150 100 L 50 50 1 1 B
-X NC 29 -400 -550 100 R 50 50 1 1 N N
-X A2 3 -400 450 100 R 50 50 1 1 I
-X I/O7 30 400 -250 100 L 50 50 1 1 B
-X NC 30 -400 -550 100 R 50 50 1 1 N N
-X VDD 33 400 650 100 L 50 50 1 1 W N
-X GND 34 -400 -750 100 R 50 50 1 1 W
-X NC 37 -400 -550 100 R 50 50 1 1 N N
-X NC 38 -400 -550 100 R 50 50 1 1 N N
-X A8 39 -400 -150 100 R 50 50 1 1 I
-X A1 4 -400 550 100 R 50 50 1 1 I
-X ~RAS~ 40 400 -550 100 L 50 50 1 1 I
-X ~OE~ 41 400 -750 100 L 50 50 1 1 I
-X A7 42 -400 -50 100 R 50 50 1 1 I
-X A6 43 -400 50 100 R 50 50 1 1 I
-X A5 44 -400 150 100 R 50 50 1 1 I
-X A0 5 -400 650 100 R 50 50 1 1 I
-X ~CAS~ 6 400 -450 100 L 50 50 1 1 I
-X I/O0 7 400 450 100 L 50 50 1 1 B
-X NC 7 -400 -550 100 R 50 50 1 1 N N
-X I/O1 8 400 350 100 L 50 50 1 1 B
-X NC 8 -400 -550 100 R 50 50 1 1 N N
-ENDDRAW
-ENDDEF
-#
-# stdparts_EPM7128SL84
-#
-DEF stdparts_EPM7128SL84 U 0 40 Y Y 1 F N
-F0 "U" 0 50 50 H V C CNN
-F1 "stdparts_EPM7128SL84" 0 -50 50 H V C CNN
-F2 "" -150 200 50 H I C CNN
-F3 "" -150 200 50 H I C CNN
-DRAW
-S -600 -1950 600 1850 0 1 10 f
-X ~GClr~ 1 750 900 150 L 50 50 1 1 I
-X I/O 10 750 1600 150 L 50 50 1 1 B
-X I/O 11 750 1700 150 L 50 50 1 1 B
-X I/O 12 -750 1700 150 R 50 50 1 1 B
-X VccIO 13 -350 2000 150 D 50 50 1 1 W
-X TDI 14 -750 1600 150 R 50 50 1 1 B
-X I/O 15 -750 1500 150 R 50 50 1 1 B
-X I/O 16 -750 1400 150 R 50 50 1 1 B
-X I/O 17 -750 1300 150 R 50 50 1 1 B
-X I/O 18 -750 1200 150 R 50 50 1 1 B
-X GND 19 -350 -2100 150 U 50 50 1 1 W
-X OE2/GClk2 2 750 1000 150 L 50 50 1 1 I
-X I/O 20 -750 1100 150 R 50 50 1 1 B
-X I/O 21 -750 1000 150 R 50 50 1 1 B
-X I/O 22 -750 900 150 R 50 50 1 1 B
-X TMS 23 -750 800 150 R 50 50 1 1 B
-X I/O 24 -750 700 150 R 50 50 1 1 B
-X I/O 25 -750 600 150 R 50 50 1 1 B
-X VccIO 26 -250 2000 150 D 50 50 1 1 W
-X I/O 27 -750 500 150 R 50 50 1 1 W
-X I/O 28 -750 400 150 R 50 50 1 1 B
-X I/O 29 -750 300 150 R 50 50 1 1 B
-X VccINT 3 350 2000 150 D 50 50 1 1 W
-X I/O 30 -750 200 150 R 50 50 1 1 B
-X I/O 31 -750 100 150 R 50 50 1 1 B
-X GND 32 -250 -2100 150 U 50 50 1 1 W
-X I/O 33 -750 -100 150 R 50 50 1 1 B
-X I/O 34 -750 -200 150 R 50 50 1 1 B
-X I/O 35 -750 -300 150 R 50 50 1 1 B
-X I/O 36 -750 -400 150 R 50 50 1 1 B
-X I/O 37 -750 -500 150 R 50 50 1 1 B
-X VccIO 38 -150 2000 150 D 50 50 1 1 W
-X I/O/NC 39 -750 -600 150 R 50 50 1 1 B
-X I/O 4 750 1100 150 L 50 50 1 1 B
-X I/O 40 -750 -700 150 R 50 50 1 1 B
-X I/O 41 -750 -800 150 R 50 50 1 1 B
-X GND 42 -150 -2100 150 U 50 50 1 1 W
-X VccINT 43 250 2000 150 D 50 50 1 1 W
-X I/O 44 -750 -900 150 R 50 50 1 1 B
-X I/O 45 -750 -1000 150 R 50 50 1 1 B
-X I/O/NC 46 -750 -1100 150 R 50 50 1 1 B
-X GND 47 -50 -2100 150 U 50 50 1 1 W
-X I/O 48 -750 -1200 150 R 50 50 1 1 B
-X I/O 49 -750 -1300 150 R 50 50 1 1 B
-X I/O 5 750 1200 150 L 50 50 1 1 B
-X I/O 50 -750 -1400 150 R 50 50 1 1 B
-X I/O 51 -750 -1500 150 R 50 50 1 1 B
-X I/O 52 -750 -1600 150 R 50 50 1 1 B
-X VccIO 53 -50 2000 150 D 50 50 1 1 W
-X I/O 54 750 -1800 150 L 50 50 1 1 B
-X I/O 55 750 -1700 150 L 50 50 1 1 B
-X I/O 56 750 -1600 150 L 50 50 1 1 B
-X I/O 57 750 -1500 150 L 50 50 1 1 B
-X I/O 58 750 -1400 150 L 50 50 1 1 B
-X GND 59 50 -2100 150 U 50 50 1 1 W
-X I/O/NC 6 750 1300 150 L 50 50 1 1 B
-X I/O 60 750 -1300 150 L 50 50 1 1 B
-X I/O 61 750 -1200 150 L 50 50 1 1 B
-X TCK 62 750 -1100 150 L 50 50 1 1 B
-X I/O 63 750 -1000 150 L 50 50 1 1 B
-X I/O 64 750 -900 150 L 50 50 1 1 B
-X I/O 65 750 -800 150 L 50 50 1 1 B
-X VccIO 66 50 2000 150 D 50 50 1 1 W
-X I/O 67 750 -700 150 L 50 50 1 1 B
-X I/O 68 750 -600 150 L 50 50 1 1 B
-X I/O 69 750 -500 150 L 50 50 1 1 B
-X GND 7 350 -2100 150 U 50 50 1 1 W
-X I/O 70 750 -400 150 L 50 50 1 1 B
-X TDO 71 750 -300 150 L 50 50 1 1 B
-X GND 72 150 -2100 150 U 50 50 1 1 W
-X I/O 73 750 -200 150 L 50 50 1 1 B
-X I/O 74 750 -100 150 L 50 50 1 1 B
-X I/O 75 750 100 150 L 50 50 1 1 B
-X I/O 76 750 200 150 L 50 50 1 1 B
-X I/O 77 750 300 150 L 50 50 1 1 B
-X VccIO 78 150 2000 150 D 50 50 1 1 W
-X I/O/NC 79 750 400 150 L 50 50 1 1 B
-X I/O 8 750 1400 150 L 50 50 1 1 B
-X I/O 80 750 500 150 L 50 50 1 1 B
-X I/O 81 750 600 150 L 50 50 1 1 B
-X GND 82 250 -2100 150 U 50 50 1 1 W
-X GClk1 83 750 700 150 L 50 50 1 1 I
-X OE1 84 750 800 150 L 50 50 1 1 I
-X I/O 9 750 1500 150 L 50 50 1 1 B
-ENDDRAW
-ENDDEF
-#
 #End Library

GR8RAM.kicad_prl

@@ -0,0 +1,75 @@
+{
+  "board": {
+    "active_layer": 31,
+    "active_layer_preset": "All Layers",
+    "auto_track_width": true,
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "ratsnest_display_mode": 0,
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      8,
+      9,
+      10,
+      11,
+      12,
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+      18,
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+      27,
+      28,
+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 0
+  },
+  "meta": {
+    "filename": "GR8RAM.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}

GR8RAM.kicad_pro

@@ -0,0 +1,481 @@
+{
+  "board": {
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.15,
+        "copper_line_width": 0.15,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.09999999999999999,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.0,
+          "height": 0.4,
+          "width": 0.65
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.15239999999999998
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_copper_edge_clearance": 0.075,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.19999999999999998,
+        "min_track_width": 0.15,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.5,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0,
+        0.2,
+        0.25,
+        0.3,
+        0.35,
+        0.4,
+        0.45,
+        0.5,
+        0.6,
+        0.762,
+        0.8,
+        1.0,
+        1.27,
+        1.524
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        },
+        {
+          "diameter": 0.6,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.8,
+          "drill": 0.4
+        },
+        {
+          "diameter": 1.0,
+          "drill": 0.5
+        },
+        {
+          "diameter": 1.524,
+          "drill": 0.762
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
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+        1,
+        0,
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+        1,
+        0,
+        2,
+        2,
+        2,
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+      ],
+      [
+        0,
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+        0,
+        0,
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+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
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+      ],
+      [
+        0,
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+        0,
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+        1,
+        2,
+        1,
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+      ],
+      [
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+      ],
+      [
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+        0,
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+        0,
+        0,
+        0,
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+      ],
+      [
+        1,
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+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
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+      ],
+      [
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+      ],
+      [
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+      ],
+      [
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+        0,
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+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "GR8RAM.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.15,
+        "via_diameter": 0.5,
+        "via_drill": 0.2,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "GR8RAM.net",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "Pcbnew",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "a29f8df0-3fae-4edf-8d9c-bd5a875b13e3",
+      ""
+    ],
+    [
+      "5d5cfbc1-a859-408c-aee8-9a6703975d80",
+      "BODMenu"
+    ],
+    [
+      "42756051-0be2-4880-864b-fa79351a044a",
+      "RAM"
+    ],
+    [
+      "c2580631-96cd-4aba-83d1-d73c0d0a7eb8",
+      "Flash"
+    ],
+    [
+      "b0ddb503-a391-46dd-bf77-8b8b2cf30231",
+      "Bus"
+    ],
+    [
+      "f81ef440-950e-4d05-b370-6421f2c33ca7",
+      "Prog"
+    ],
+    [
+      "b30763ef-424b-4a57-9138-82e38c28db28",
+      "Control"
+    ]
+  ],
+  "text_variables": {}
+}

GR8RAM.pro

@@ -1,256 +0,0 @@
-update=Monday, June 10, 2019 at 02:27:25 PM
-version=1
-last_client=kicad
-[general]
-version=1
-RootSch=
-BoardNm=
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
-[pcbnew]
-version=1
-PageLayoutDescrFile=
-LastNetListRead=GR8RAM.net
-CopperLayerCount=4
-BoardThickness=1.6
-AllowMicroVias=0
-AllowBlindVias=0
-RequireCourtyardDefinitions=0
-ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.1524
-MinViaDiameter=0.4
-MinViaDrill=0.3
-MinMicroViaDiameter=0.2
-MinMicroViaDrill=0.09999999999999999
-MinHoleToHole=0.25
-TrackWidth1=0.1524
-TrackWidth2=0.2
-TrackWidth3=0.254
-TrackWidth4=0.508
-TrackWidth5=0.762
-TrackWidth6=1.27
-TrackWidth7=1.524
-ViaDiameter1=0.8
-ViaDrill1=0.4
-ViaDiameter2=1.524
-ViaDrill2=0.762
-dPairWidth1=0.2
-dPairGap1=0.25
-dPairViaGap1=0.25
-SilkLineWidth=0.15
-SilkTextSizeV=1
-SilkTextSizeH=1
-SilkTextSizeThickness=0.15
-SilkTextItalic=0
-SilkTextUpright=1
-CopperLineWidth=0.1524
-CopperTextSizeV=1.5
-CopperTextSizeH=1.5
-CopperTextThickness=0.3
-CopperTextItalic=0
-CopperTextUpright=1
-EdgeCutLineWidth=0.15
-CourtyardLineWidth=0.05
-OthersLineWidth=0.15
-OthersTextSizeV=1
-OthersTextSizeH=1
-OthersTextSizeThickness=0.15
-OthersTextItalic=0
-OthersTextUpright=1
-SolderMaskClearance=0.07619999999999999
-SolderMaskMinWidth=0.1524
-SolderPasteClearance=-0.05
-SolderPasteRatio=0
-[pcbnew/Layer.F.Cu]
-Name=F.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.In1.Cu]
-Name=In1.Cu
-Type=1
-Enabled=1
-[pcbnew/Layer.In2.Cu]
-Name=In2.Cu
-Type=1
-Enabled=1
-[pcbnew/Layer.In3.Cu]
-Name=In3.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In4.Cu]
-Name=In4.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In5.Cu]
-Name=In5.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In6.Cu]
-Name=In6.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In7.Cu]
-Name=In7.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In8.Cu]
-Name=In8.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In9.Cu]
-Name=In9.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In10.Cu]
-Name=In10.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In11.Cu]
-Name=In11.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In12.Cu]
-Name=In12.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In13.Cu]
-Name=In13.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In14.Cu]
-Name=In14.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In15.Cu]
-Name=In15.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In16.Cu]
-Name=In16.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In17.Cu]
-Name=In17.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In18.Cu]
-Name=In18.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In19.Cu]
-Name=In19.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In20.Cu]
-Name=In20.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In21.Cu]
-Name=In21.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In22.Cu]
-Name=In22.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In23.Cu]
-Name=In23.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In24.Cu]
-Name=In24.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In25.Cu]
-Name=In25.Cu
-Type=0
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LICENSE

@@ -0,0 +1,20 @@
+Copyright (c) Garrett's Workshop
+
+Rationale
+----------------------------------------
+We at Garrett's Workshop create our products and release their source in
+hopes of encouraging others to contribute and build their own "clones,"
+even selling them and competing with us. One day, GW will be defunct,
+and it would be a shame if our hardware and software die along with GW.
+At the same time, however, we seek to protect our trademark and ensure
+that clones and derivative products do not masquerade as genuine
+Garrett's Workshop products.
+
+License Terms
+----------------------------------------
+This project may be licensed under one of two licenses:
+
+1. You may elect to license this project under CC BY-NC-SA 4.0.
+
+2. You may elect to license this project under CC BY-SA 4.0 ONLY IF
+   you remove all "Garrett's Workshop" trademarks from the project.

Power.kicad_sch

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+(kicad_sch (version 20211123) (generator eeschema)
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RAM.kicad_sch

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cpld/GR8RAM.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:41:40  March 15, 2021
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "13:41:40  March 15, 2021"
+
+# Revisions
+
+PROJECT_REVISION = "GR8RAM"

cpld/GR8RAM.qsf

@@ -0,0 +1,272 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:41:40  March 15, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		GR8RAM_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM240T100C5
+set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40  MARCH 15, 2021"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name SAFE_STATE_MACHINE OFF
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
+set_global_assignment -name AUTO_RESOURCE_SHARING ON
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
+set_global_assignment -name MUX_RESTRUCTURE ON
+set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
+set_global_assignment -name SYNTHESIS_SEED 123
+set_global_assignment -name SEED 235
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
+set_global_assignment -name VERILOG_FILE GR8RAM.v
+set_location_assignment PIN_1 -to RA[4]
+set_location_assignment PIN_2 -to RA[5]
+set_location_assignment PIN_3 -to RA[6]
+set_location_assignment PIN_4 -to RA[3]
+set_location_assignment PIN_5 -to nFCS
+set_location_assignment PIN_6 -to RA[7]
+set_location_assignment PIN_7 -to RA[8]
+set_location_assignment PIN_8 -to RA[9]
+set_location_assignment PIN_12 -to FCK
+set_location_assignment PIN_14 -to RA[10]
+set_location_assignment PIN_15 -to MOSI
+set_location_assignment PIN_16 -to MISO
+set_location_assignment PIN_30 -to nRESout
+set_location_assignment PIN_34 -to RA[11]
+set_location_assignment PIN_35 -to RA[12]
+set_location_assignment PIN_36 -to RA[13]
+set_location_assignment PIN_37 -to RA[14]
+set_location_assignment PIN_38 -to RA[15]
+set_location_assignment PIN_39 -to nIOSEL
+set_location_assignment PIN_42 -to nIOSTRB
+set_location_assignment PIN_40 -to nDEVSEL
+set_location_assignment PIN_41 -to PHI0
+set_location_assignment PIN_43 -to nWE
+set_location_assignment PIN_44 -to nRES
+set_location_assignment PIN_47 -to SD[1]
+set_location_assignment PIN_50 -to SD[0]
+set_location_assignment PIN_51 -to SD[4]
+set_location_assignment PIN_100 -to RA[0]
+set_location_assignment PIN_99 -to RD[7]
+set_location_assignment PIN_52 -to SD[5]
+set_location_assignment PIN_54 -to SD[7]
+set_location_assignment PIN_55 -to SD[3]
+set_location_assignment PIN_56 -to SD[2]
+set_location_assignment PIN_53 -to SD[6]
+set_location_assignment PIN_57 -to DQMH
+set_location_assignment PIN_58 -to nSWE
+set_location_assignment PIN_62 -to nRAS
+set_location_assignment PIN_61 -to nCAS
+set_location_assignment PIN_64 -to C25M
+set_location_assignment PIN_66 -to RCKE
+set_location_assignment PIN_67 -to nRCS
+set_location_assignment PIN_68 -to SA[12]
+set_location_assignment PIN_69 -to SBA[0]
+set_location_assignment PIN_70 -to SA[11]
+set_location_assignment PIN_71 -to SBA[1]
+set_location_assignment PIN_72 -to SA[9]
+set_location_assignment PIN_73 -to SA[10]
+set_location_assignment PIN_74 -to SA[8]
+set_location_assignment PIN_75 -to SA[0]
+set_location_assignment PIN_76 -to SA[4]
+set_location_assignment PIN_77 -to SA[6]
+set_location_assignment PIN_78 -to SA[7]
+set_location_assignment PIN_81 -to SA[1]
+set_location_assignment PIN_82 -to SA[2]
+set_location_assignment PIN_83 -to SA[5]
+set_location_assignment PIN_84 -to SA[3]
+set_location_assignment PIN_85 -to DQML
+set_location_assignment PIN_86 -to RD[0]
+set_location_assignment PIN_87 -to RD[1]
+set_location_assignment PIN_88 -to RD[2]
+set_location_assignment PIN_89 -to RD[3]
+set_location_assignment PIN_90 -to RD[4]
+set_location_assignment PIN_91 -to RD[5]
+set_location_assignment PIN_92 -to RD[6]
+set_location_assignment PIN_97 -to RA[2]
+set_location_assignment PIN_98 -to RA[1]
+set_location_assignment PIN_96 -to SetFW[0]
+set_location_assignment PIN_95 -to SetFW[1]
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nFCS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nFCS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to FCK
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO
+set_location_assignment PIN_21 -to nDMAout
+set_location_assignment PIN_19 -to RAdir
+set_location_assignment PIN_20 -to INTout
+set_location_assignment PIN_26 -to nNMIout
+set_location_assignment PIN_27 -to nINHout
+set_location_assignment PIN_28 -to nRDYout
+set_location_assignment PIN_29 -to nIRQout
+set_location_assignment PIN_33 -to RWout
+set_location_assignment PIN_48 -to DMAin
+set_location_assignment PIN_49 -to INTin
+set_location_assignment PIN_17 -to RDdir
+set_location_assignment PIN_18 -to DMAout
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAdir
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RAdir
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RAdir
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RAdir
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAdir
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RDdir
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RDdir
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RDdir
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RDdir
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RDdir
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to PHI0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI0
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to PHI0
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nWE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nWE
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nDEVSEL
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDEVSEL
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDEVSEL
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSEL
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSEL
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSEL
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSTRB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSTRB
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSTRB
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nRES
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRES
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRES
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRESout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRESout
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRESout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRESout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRESout
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nFCS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nFCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nFCS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FCK
+set_instance_assignment -name SLOW_SLEW_RATE ON -to FCK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to FCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MOSI
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MOSI
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to C25M
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C25M
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to C25M
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRCS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRCS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRCS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRAS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRAS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCAS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nCAS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSWE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nSWE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nSWE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nSWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSWE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RCKE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCKE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCKE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQMH
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQMH
+set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQML
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQML
+set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD
+set_global_assignment -name SDC_FILE GR8RAM.sdc

cpld/GR8RAM.sdc

@@ -0,0 +1,3 @@
+create_clock -period 40 [get_ports C25M]
+create_clock -period 978 [get_ports PHI0]
+set_clock_groups -asynchronous -group C25M -group PHI0

cpld/GR8RAM.v

@@ -0,0 +1,568 @@
+module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
+			  INTin, INTout, DMAin, DMAout, 
+			  nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
+			  RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
+			  SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
+			  nFCS, FCK, MISO, MOSI);
+
+	/* Clock signals */
+	input C25M, PHI0;
+	reg PHI0r1, PHI0r2;
+	always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
+	
+	/* Reset filter */
+	input nRES;
+	reg [3:0] nRESf = 0;
+	reg nRESr = 0;
+	always @(posedge C25M) begin 
+		nRESf[3:0] <= { nRESf[2:0], nRES };
+		nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
+	end
+
+	/* Firmware select */
+	input [1:0] SetFW;
+	reg [1:0] SetFWr;
+	reg SetFWLoaded = 0;
+	always @(posedge C25M) begin
+		if (~SetFWLoaded) begin
+			SetFWLoaded <= 1;
+			SetFWr[1:0] <= SetFW[1:0];
+		end
+	end
+	wire [1:0] SetROM = ~SetFWr[1:0];
+	wire SetEN16MB = SetROM[1:0]==2'b11;
+	wire SetEN24bit = SetROM[1];
+
+	/* State counter from PHI0 rising edge */
+	reg [3:0] PS = 0;
+	wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
+	always @(posedge C25M) begin
+		if (PSStart) PS <= 1;
+		else if (PS==0) PS <= 0;
+		else PS <= PS+1;
+	end
+
+	/* Long state counter: counts from 0 to $3FFF */
+	reg [13:0] LS = 0;
+	always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
+
+	/* Init state */
+	output reg nRESout = 0;
+	reg [2:0] IS = 0;
+	always @(posedge C25M) begin
+		if (IS==7) nRESout <= 1;
+		else if (PS==15) begin
+			if (LS==14'h1FCE) IS <= 1; // PC all + load mode
+			else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
+			else if (LS==14'h1FFA) IS <= 5; // SPI flash command
+			else if (LS==14'h1FFF) IS <= 6; // Flash load driver
+			else if (LS==14'h3FFF) IS <= 7; // Operating mode
+		end
+	end
+
+	/* Apple IO area select signals */
+	input nIOSEL, nDEVSEL, nIOSTRB;
+
+	/* Apple address bus */
+	input [15:0] RA; input nWE;
+	reg   [11:0] RAr; reg nWEr;
+	reg CXXXr;
+	always @(posedge PHI0) begin
+		CXXXr <= RA[15:12]==4'hC;
+		RAr[11:0] <= RA[11:0];
+		nWEr <= nWE;
+	end
+
+	/* Apple select signals */
+	wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
+	wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
+	wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
+	wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
+	wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
+	wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
+	wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
+	wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
+	wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
+	wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL;
+	wire RAMSEL = ~nDEVSEL && RAMSpecSEL;
+	wire RAMWR = RAMSEL && ~nWEr;
+	wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
+	wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
+	wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
+	
+	/* IOROMEN and REGEN control */
+	reg IOROMEN = 0;
+	reg REGEN = 0;
+	reg nIOSTRBr;
+	wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr;
+	always @(posedge C25M, negedge nRESr) begin
+		if (~nRESr) REGEN <= 0;
+		else if (PS==8 && ~nIOSEL) REGEN <= 1;
+	end
+	always @(posedge C25M) begin
+		nIOSTRBr <= nIOSTRB;
+		if (~nRESr) IOROMEN <= 0;
+		else if (PS==8 && IOROMRES) IOROMEN <= 0;
+		else if (PS==8 && ~nIOSEL) IOROMEN <= 1;
+	end
+
+	/* Apple data bus */
+	inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
+	reg [7:0] RDD;
+	output RDdir = ~(PHI0r2 && nWE && PHI0 &&
+		(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
+
+	/* Slinky address registers */
+	reg [23:0] Addr = 0;
+	reg AddrIncL = 0;
+	reg AddrIncM = 0;
+	reg AddrIncH = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (~nRESr) begin
+			Addr[23:0] <= 24'h000000;
+			AddrIncL <= 0;
+			AddrIncM <= 0;
+			AddrIncH <= 0;
+		end else begin
+			if (PS==8 && RAMRegSEL) AddrIncL <= 1;
+			else AddrIncL <= 0;
+
+			if (PS==8 && AddrLSEL && ~nWEr) begin
+				Addr[7:0] <= RD[7:0];
+				AddrIncM <= Addr[7] && ~RD[7];
+			end else if (AddrIncL) begin
+				Addr[7:0] <= Addr[7:0]+1;
+				AddrIncM <= Addr[7:0]==8'hFF;
+			end else AddrIncM <= 0;
+
+			if (PS==8 && AddrMSEL && ~nWEr) begin
+				Addr[15:8] <= RD[7:0];
+				AddrIncH <= Addr[15] && ~RD[7];
+			end else if (AddrIncM) begin
+				Addr[15:8] <= Addr[15:8]+1;
+				AddrIncH <= Addr[15:8]==8'hFF;
+			end else AddrIncH <= 0;
+
+			if (PS==8 && AddrHSEL && ~nWEr) begin
+				Addr[23:16] <= RD[7:0];
+			end else if (AddrIncH) begin
+				Addr[23:16] <= Addr[23:16]+1;
+			end
+		end
+	end
+
+	/* ROM bank register */
+	reg Bank = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (~nRESr) Bank <= 0;
+		else if (PS==8 && BankSEL && ~nWEr) begin
+			Bank <= RD[0];
+		end
+	end
+
+	/* SPI flash control signals */
+	output nFCS = FCKOE ? ~FCS : 1'bZ;
+	reg FCS = 0;
+	output FCK = FCKOE ? FCKout : 1'bZ;
+	reg FCKOE = 0;
+	reg FCKout = 0;
+	inout MOSI = MOSIOE ? MOSIout : 1'bZ;
+	reg MOSIOE = 0;
+	input MISO;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 1: begin // ACT
+				FCKout <= ~(IS==5 || IS==6);
+			end 2: begin // RD
+				FCKout <= 1'b1;
+			end 3: begin // NOP CKE
+				FCKout <= ~(IS==5 || IS==6);
+			end 4: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 5: begin // NOP CKE
+				FCKout <= ~(IS==5 || IS==6);
+			end 6: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 7: begin // NOP CKE
+				FCKout <= ~(IS==5 || IS==6);
+			end 8: begin // WR AP
+				FCKout <= 1'b1;
+			end 9: begin // NOP CKE
+				FCKout <= ~(IS==5);
+			end 10: begin // PC all
+				FCKout <= 1'b1;
+			end 11: begin // AREF
+				FCKout <= ~(IS==5);
+			end 12: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 13: begin // NOP CKE
+				FCKout <= ~(IS==5);
+			end 14: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 15: begin // NOP CKE
+				FCKout <= ~(IS==5);
+			end
+		endcase
+		FCS <= IS==4 || IS==5 || IS==6;
+		MOSIOE <= IS==5;
+		FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
+	end
+
+	/* SPI flash MOSI control */
+	reg MOSIout = 0;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			1: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 7
+					3'h4: MOSIout <= 1'b0; // Address bit 23
+					3'h5: MOSIout <= 1'b0; // Address bit 15
+					3'h6: MOSIout <= 1'b0; // Address bit 7
+					default MOSIout <= 1'b0;
+				endcase
+			end 3: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 6
+					3'h4: MOSIout <= 1'b0; // Address bit 22
+					3'h5: MOSIout <= SetROM[1]; // Address bit 14
+					3'h6: MOSIout <= 1'b0; // Address bit 6
+					default MOSIout <= 1'b0;
+				endcase
+			end 5: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 5
+					3'h4: MOSIout <= 1'b0; // Address bit 21
+					3'h5: MOSIout <= SetROM[0]; // Address bit 13
+					3'h6: MOSIout <= 1'b0; // Address bit 5
+					default MOSIout <= 1'b0;
+				endcase
+			end 7: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 4
+					3'h4: MOSIout <= 1'b0; // Address bit 20
+					3'h5: MOSIout <= 1'b0; // Address bit 12
+					3'h6: MOSIout <= 1'b0; // Address bit 4
+					default MOSIout <= 1'b0;
+				endcase
+			end 9: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 3
+					3'h4: MOSIout <= 1'b0; // Address bit 19
+					3'h5: MOSIout <= 1'b0; // Address bit 11
+					3'h6: MOSIout <= 1'b0; // Address bit 3
+					default MOSIout <= 1'b0;
+				endcase
+			end 11: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 2
+					3'h4: MOSIout <= 1'b0; // Address bit 18
+					3'h5: MOSIout <= 1'b0; // Address bit 10
+					3'h6: MOSIout <= 1'b0; // Address bit 2
+					default MOSIout <= 1'b0;
+				endcase
+			end 13: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 1
+					3'h4: MOSIout <= 1'b0; // Address bit 16
+					3'h5: MOSIout <= 1'b0; // Address bit 9
+					3'h6: MOSIout <= 1'b0; // Address bit 1
+					default MOSIout <= 1'b0;
+				endcase
+			end 15: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 0
+					3'h4: MOSIout <= 1'b0; // Address bit 15
+					3'h5: MOSIout <= 1'b0; // Address bit 7
+					3'h6: MOSIout <= 1'b0; // Address bit 0
+					default MOSIout <= 1'b0;
+				endcase
+			end 
+		endcase
+	end
+
+	/* SDRAM data bus */
+	inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
+	reg [7:0] WRD;
+	reg SDOE = 0;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 1: begin // ACT
+			end 2: begin // RD
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 3: begin // NOP CKE
+			end 4: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 5: begin // NOP CKE
+			end 6: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 7: begin // NOP CKE
+			end 8: begin // WR AP
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 9: begin // NOP CKE
+			end 10: begin // PC all
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 11: begin // AREF
+			end 12: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 13: begin // NOP CKE
+			end 14: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 15: begin // NOP CKE
+			end
+		endcase
+	end
+
+	/* Apple data bus from SDRAM */
+	always @(negedge C25M) begin
+		if (PS==5) begin
+			if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
+			else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
+			else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
+			else RDD[7:0] <= SD[7:0];
+		end
+	end
+
+	/* SDRAM command */
+	output reg RCKE = 1;
+	output reg nRCS = 1;
+	output reg nRAS = 1;
+	output reg nCAS = 1;
+	output reg nSWE = 1;
+	wire RefReqd = LS[1:0] == 2'b11;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE / NOP CKD
+				RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 1: begin // ACT CKE / NOP CKD (ACT)
+				RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
+				nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
+				nRAS <= 0;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 2: begin // RD CKE / NOP CKD (RD)
+				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
+				nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
+				nRAS <= 1;
+				nCAS <= 0;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 3: begin // NOP CKE / CKD
+				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 4: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 5: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 6: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 7: begin // NOP CKE / CKD
+				RCKE <= IS==6 || (RAMWR && IS==7);
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 8: begin // WR AP CKE / NOP CKD (WR AP)
+				RCKE <= IS==6 || (RAMWR && IS==7);
+				nRCS <= ~(IS==6 || (RAMWR && IS==7));
+				nRAS <= 1;
+				nCAS <= 0;
+				nSWE <= 0;
+				SDOE <= IS==6 || (RAMWR && IS==7);
+			end 9: begin // NOP CKE / NOP CKD
+				RCKE <= 1;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 10: begin // PC all CKE / PC all CKD
+				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
+				nRCS <= 0;
+				nRAS <= 0;
+				nCAS <= 1;
+				nSWE <= 0;
+				SDOE <= 0;
+			end 11: begin // LDM CKE / AREF CKE / NOP CKD
+				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
+				nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
+				nRAS <= 0;
+				nCAS <= 0;
+				nSWE <= ~(IS==1);
+				SDOE <= 0;
+			end default: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end
+		endcase
+	end
+
+	/* SDRAM address */
+	output reg DQML = 1;
+	output reg DQMH = 1;
+	output reg [1:0] SBA;
+	output reg [12:0] SA;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 1: begin // ACT
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				if (IS==6) begin
+					SBA[1:0] <= { 2'b10 };
+					SA[12:0] <= { 10'b0011000100, LS[12:10] };
+				end else if (RAMSpecSEL) begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
+					SA[9:0] <= Addr[19:10];
+				end else begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
+				end
+			end 2: begin // RD
+				if (RAMSpecSEL) begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:0] <= { 4'b0011, Addr[9:1] };
+					DQML <= Addr[0];
+					DQMH <= ~Addr[0];
+				end else begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 4'b0011, RAr[9:1]};
+					DQML <= RAr[0];
+					DQMH <= ~RAr[0];
+				end
+			end 3: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 4: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 5: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 6: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 7: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 8: begin // WR AP
+				if (IS==6) begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 4'b0011, LS[9:1] };
+					DQML <= LS[0];
+					DQMH <= ~LS[0];
+				end else begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:0] <= { 4'b0011, Addr[9:1] };
+					DQML <= Addr[0];
+					DQMH <= ~Addr[0];
+				end
+			end 9: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 10: begin // PC all
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 11: begin // AREF / load mode
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0001000100000;
+			end 12: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 13: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 14: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 15: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end
+		endcase
+	end
+
+	/* DMA/INT in/out */
+	input INTin, DMAin;
+	output INTout = INTin;
+	output DMAout = DMAin;
+
+	/* Unused Pins */
+	output RAdir = 1;
+	output nDMAout = 1;
+	output nNMIout = 1;
+	output nINHout = 1;
+	output nRDYout = 1;
+	output nIRQout = 1;
+	output RWout = 1;
+endmodule

cpld/UFM.qip

@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]

cpld/db/GR8RAM.asm.qmsg

@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597731746 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:31 2021 " "Processing started: Tue Sep 14 01:35:31 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1631597731986 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1631597731986 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing ended: Tue Sep 14 01:35:32 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1631597732146 ""}

cpld/db/GR8RAM.cbx.xml

@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="GR8RAM">
+	</PROJECT>
+</LOG_ROOT>

cpld/db/GR8RAM.cmp.logdb

@@ -0,0 +1 @@
+v1

cpld/db/GR8RAM.fit.qmsg

@@ -0,0 +1,38 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1631597728526 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1631597728536 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1631597728726 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1631597728736 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1631597728876 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1631597729026 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1631597729036 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000         C25M " "  40.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000         PHI0 " " 978.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1631597729036 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729046 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
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+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
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+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1631597729086 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1631597729116 ""}
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+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729186 ""}
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+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730096 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1631597730126 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1631597730346 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1631597730346 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730656 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1631597730666 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730666 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1631597730716 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1631597730776 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "544 " "Peak virtual memory: 544 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:30 2021 " "Processing ended: Tue Sep 14 01:35:30 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1631597730806 ""}

cpld/db/GR8RAM.hier_info

@@ -0,0 +1,220 @@
+|GR8RAM
+C25M => SA[0]~reg0.CLK
+C25M => SA[1]~reg0.CLK
+C25M => SA[2]~reg0.CLK
+C25M => SA[3]~reg0.CLK
+C25M => SA[4]~reg0.CLK
+C25M => SA[5]~reg0.CLK
+C25M => SA[6]~reg0.CLK
+C25M => SA[7]~reg0.CLK
+C25M => SA[8]~reg0.CLK
+C25M => SA[9]~reg0.CLK
+C25M => SA[10]~reg0.CLK
+C25M => SA[11]~reg0.CLK
+C25M => SA[12]~reg0.CLK
+C25M => SBA[0]~reg0.CLK
+C25M => SBA[1]~reg0.CLK
+C25M => DQMH~reg0.CLK
+C25M => DQML~reg0.CLK
+C25M => SDOE.CLK
+C25M => nSWE~reg0.CLK
+C25M => nCAS~reg0.CLK
+C25M => nRAS~reg0.CLK
+C25M => nRCS~reg0.CLK
+C25M => RCKE~reg0.CLK
+C25M => WRD[0].CLK
+C25M => WRD[1].CLK
+C25M => WRD[2].CLK
+C25M => WRD[3].CLK
+C25M => WRD[4].CLK
+C25M => WRD[5].CLK
+C25M => WRD[6].CLK
+C25M => WRD[7].CLK
+C25M => MOSIout.CLK
+C25M => FCKOE.CLK
+C25M => MOSIOE.CLK
+C25M => FCS.CLK
+C25M => FCKout.CLK
+C25M => Bank.CLK
+C25M => AddrIncH.CLK
+C25M => AddrIncM.CLK
+C25M => AddrIncL.CLK
+C25M => Addr[0].CLK
+C25M => Addr[1].CLK
+C25M => Addr[2].CLK
+C25M => Addr[3].CLK
+C25M => Addr[4].CLK
+C25M => Addr[5].CLK
+C25M => Addr[6].CLK
+C25M => Addr[7].CLK
+C25M => Addr[8].CLK
+C25M => Addr[9].CLK
+C25M => Addr[10].CLK
+C25M => Addr[11].CLK
+C25M => Addr[12].CLK
+C25M => Addr[13].CLK
+C25M => Addr[14].CLK
+C25M => Addr[15].CLK
+C25M => Addr[16].CLK
+C25M => Addr[17].CLK
+C25M => Addr[18].CLK
+C25M => Addr[19].CLK
+C25M => Addr[20].CLK
+C25M => Addr[21].CLK
+C25M => Addr[22].CLK
+C25M => Addr[23].CLK
+C25M => IOROMEN.CLK
+C25M => nIOSTRBr.CLK
+C25M => REGEN.CLK
+C25M => nRESout~reg0.CLK
+C25M => LS[0].CLK
+C25M => LS[1].CLK
+C25M => LS[2].CLK
+C25M => LS[3].CLK
+C25M => LS[4].CLK
+C25M => LS[5].CLK
+C25M => LS[6].CLK
+C25M => LS[7].CLK
+C25M => LS[8].CLK
+C25M => LS[9].CLK
+C25M => LS[10].CLK
+C25M => LS[11].CLK
+C25M => LS[12].CLK
+C25M => LS[13].CLK
+C25M => PS[0].CLK
+C25M => PS[1].CLK
+C25M => PS[2].CLK
+C25M => PS[3].CLK
+C25M => SetFWr[0].CLK
+C25M => SetFWr[1].CLK
+C25M => SetFWLoaded.CLK
+C25M => nRESr.CLK
+C25M => nRESf[0].CLK
+C25M => nRESf[1].CLK
+C25M => nRESf[2].CLK
+C25M => nRESf[3].CLK
+C25M => PHI0r2.CLK
+C25M => PHI0r1.CLK
+C25M => IS~7.DATAIN
+C25M => RDD[0].CLK
+C25M => RDD[1].CLK
+C25M => RDD[2].CLK
+C25M => RDD[3].CLK
+C25M => RDD[4].CLK
+C25M => RDD[5].CLK
+C25M => RDD[6].CLK
+C25M => RDD[7].CLK
+PHI0 => comb.IN1
+PHI0 => nWEr.CLK
+PHI0 => RAr[0].CLK
+PHI0 => RAr[1].CLK
+PHI0 => RAr[2].CLK
+PHI0 => RAr[3].CLK
+PHI0 => RAr[4].CLK
+PHI0 => RAr[5].CLK
+PHI0 => RAr[6].CLK
+PHI0 => RAr[7].CLK
+PHI0 => RAr[8].CLK
+PHI0 => RAr[9].CLK
+PHI0 => RAr[10].CLK
+PHI0 => RAr[11].CLK
+PHI0 => CXXXr.CLK
+PHI0 => PHI0r1.DATAIN
+nRES => nRESf[0].DATAIN
+nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SetFW[0] => SetFWr[0].DATAIN
+SetFW[1] => SetFWr[1].DATAIN
+INTin => INTout.DATAIN
+INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
+DMAin => DMAout.DATAIN
+DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
+nNMIout <= <VCC>
+nIRQout <= <VCC>
+nRDYout <= <VCC>
+nINHout <= <VCC>
+RWout <= <VCC>
+nDMAout <= <VCC>
+RA[0] => RAr[0].DATAIN
+RA[0] => Equal16.IN10
+RA[1] => RAr[1].DATAIN
+RA[1] => Equal16.IN9
+RA[2] => RAr[2].DATAIN
+RA[2] => Equal16.IN8
+RA[3] => RAr[3].DATAIN
+RA[3] => Equal16.IN7
+RA[4] => RAr[4].DATAIN
+RA[4] => Equal16.IN6
+RA[5] => RAr[5].DATAIN
+RA[5] => Equal16.IN5
+RA[6] => RAr[6].DATAIN
+RA[6] => Equal16.IN4
+RA[7] => RAr[7].DATAIN
+RA[7] => Equal16.IN3
+RA[8] => RAr[8].DATAIN
+RA[8] => Equal16.IN2
+RA[9] => RAr[9].DATAIN
+RA[9] => Equal16.IN1
+RA[10] => RAr[10].DATAIN
+RA[10] => Equal16.IN0
+RA[11] => RAr[11].DATAIN
+RA[12] => Equal8.IN1
+RA[13] => Equal8.IN0
+RA[14] => Equal8.IN3
+RA[15] => Equal8.IN2
+nWE => comb.IN1
+nWE => nWEr.DATAIN
+RD[0] <> RD[0]
+RD[1] <> RD[1]
+RD[2] <> RD[2]
+RD[3] <> RD[3]
+RD[4] <> RD[4]
+RD[5] <> RD[5]
+RD[6] <> RD[6]
+RD[7] <> RD[7]
+RAdir <= <VCC>
+RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
+nIOSEL => comb.IN0
+nIOSEL => always7.IN1
+nDEVSEL => comb.IN1
+nDEVSEL => RAMSEL.IN1
+nDEVSEL => comb.IN1
+nDEVSEL => RAMRegSEL.IN1
+nIOSTRB => nIOSTRBr.DATAIN
+nIOSTRB => comb.IN1
+nIOSTRB => comb.IN1
+SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SD[0] <> SD[0]
+SD[1] <> SD[1]
+SD[2] <> SD[2]
+SD[3] <> SD[3]
+SD[4] <> SD[4]
+SD[5] <> SD[5]
+SD[6] <> SD[6]
+SD[7] <> SD[7]
+nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
+FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
+MISO => WRD.DATAB
+MOSI <> MOSI
+
+

cpld/db/GR8RAM.lpc.html

@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>

cpld/db/GR8RAM.lpc.txt

@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

cpld/db/GR8RAM.map.logdb

@@ -0,0 +1 @@
+v1

cpld/db/GR8RAM.map.qmsg

@@ -0,0 +1,19 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597725836 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:25 2021 " "Processing started: Tue Sep 14 01:35:25 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597726126 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 110 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 286 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1631597726256 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1631597726806 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RAdir"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1631597726986 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1631597727226 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1631597727256 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1631597727256 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1631597727336 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "422 " "Peak virtual memory: 422 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:27 2021 " "Processing ended: Tue Sep 14 01:35:27 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""}

cpld/db/GR8RAM.smart_action.txt

@@ -0,0 +1 @@
+DONE

cpld/db/GR8RAM.smp_dump.txt

@@ -0,0 +1,9 @@
+
+State Machine - |GR8RAM|IS
+Name IS.state_bit_2 IS.state_bit_1 IS.state_bit_0 
+IS.000 0 0 0 
+IS.001 0 0 1 
+IS.100 1 0 0 
+IS.101 1 0 1 
+IS.110 0 1 0 
+IS.111 0 1 1 

cpld/db/GR8RAM.sta.qmsg

@@ -0,0 +1,20 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597733226 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing started: Tue Sep 14 01:35:32 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1631597733306 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597733426 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1631597733536 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1631597733876 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1631597733926 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1631597733926 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   12.419         0.000 C25M  " "   12.419         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.393         0.000 C25M  " "    1.393         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   33.300         0.000 C25M  " "   33.300         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.146         0.000 C25M  " "    6.146         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.734         0.000 C25M  " "   19.734         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  488.734         0.000 PHI0  " "  488.734         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1631597733996 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:34 2021 " "Processing ended: Tue Sep 14 01:35:34 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""}

cpld/db/prev_cmp_GR8RAM.qmsg

@@ -0,0 +1,91 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049425619 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:05 2021 " "Processing started: Wed Apr 21 19:57:05 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049425635 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049427276 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 286 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1619049427557 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427589 "|GR8RAM"}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1619049429167 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RAdir"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1619049429543 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1619049430027 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1619049430074 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1619049430074 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1619049430324 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:10 2021 " "Processing ended: Wed Apr 21 19:57:10 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049433591 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:12 2021 " "Processing started: Wed Apr 21 19:57:12 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1619049433810 ""}
+{ "Info" "0" "" "Project  = GR8RAM" {  } {  } 0 0 "Project  = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
+{ "Info" "0" "" "Revision = GR8RAM" {  } {  } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619049434576 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619049434607 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1619049435826 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619049435873 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619049436217 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1619049436389 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1619049436436 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000         C25M " "  40.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000         PHI0 " " 978.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1619049436451 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436467 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 419 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1619049436514 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1619049436529 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1619049436592 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436654 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436670 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1619049436670 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619049436670 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049436701 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619049436967 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049437342 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619049437373 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619049438593 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049438593 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619049438686 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1619049439186 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619049439186 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439702 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1619049439718 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439718 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1619049439765 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619049440124 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:20 2021 " "Processing ended: Wed Apr 21 19:57:20 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619049440312 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1619049443282 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:22 2021 " "Processing started: Wed Apr 21 19:57:22 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619049444797 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619049444985 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:26 2021 " "Processing ended: Wed Apr 21 19:57:26 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619049446001 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1619049446923 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1619049449251 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:27 2021 " "Processing started: Wed Apr 21 19:57:27 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1619049449455 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049450502 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1619049450877 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1619049451408 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1619049451564 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1619049451627 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   12.419         0.000 C25M  " "   12.419         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.393         0.000 C25M  " "    1.393         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   33.300         0.000 C25M  " "   33.300         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.146         0.000 C25M  " "    6.146         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.734         0.000 C25M  " "   19.734         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  488.734         0.000 PHI0  " "  488.734         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1619049451861 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451924 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451939 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:32 2021 " "Processing ended: Wed Apr 21 19:57:32 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049453283 ""}

cpld/greybox_tmp/cbx_args.txt

@@ -0,0 +1,25 @@
+ERASE_TIME=500000000
+INTENDED_DEVICE_FAMILY="MAX II"
+LPM_FILE=UNUSED
+LPM_HINT=UNUSED
+LPM_TYPE=altufm_none
+OSC_FREQUENCY=180000
+PORT_ARCLKENA=PORT_UNUSED
+PORT_DRCLKENA=PORT_UNUSED
+PROGRAM_TIME=1600000
+WIDTH_UFM_ADDRESS=9
+DEVICE_FAMILY="MAX II"
+CBX_AUTO_BLACKBOX=ALL
+arclk
+ardin
+arshft
+busy
+drclk
+drdin
+drdout
+drshft
+erase
+osc
+oscena
+program
+rtpbusy

cpld/incremental_db/README

@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+

cpld/incremental_db/compiled_partitions/GR8RAM.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Thu Mar 18 03:51:58 2021

cpld/output_files/GR8RAM.asm.rpt

@@ -0,0 +1,114 @@
+Assembler report for GR8RAM
+Tue Sep 14 01:35:32 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Sep 14 01:35:32 2021 ;
+; Revision Name         ; GR8RAM                                ;
+; Top-level Entity Name ; GR8RAM                                ;
+; Family                ; MAX II                                ;
+; Device                ; EPM240T100C5                          ;
++-----------------------+---------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                      ;
++-----------------------------------------------------------------------------+-----------+---------------+
+; Option                                                                      ; Setting   ; Default Value ;
++-----------------------------------------------------------------------------+-----------+---------------+
+; Use smart compilation                                                       ; Off       ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On        ; On            ;
+; Enable compact report table                                                 ; Off       ; Off           ;
+; Compression mode                                                            ; Off       ; Off           ;
+; Clock source for configuration device                                       ; Internal  ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ    ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1         ; 1             ;
+; Auto user code                                                              ; On        ; On            ;
+; Security bit                                                                ; Off       ; Off           ;
+; Use configuration device                                                    ; On        ; On            ;
+; Configuration device                                                        ; Auto      ; Auto          ;
+; Configuration device auto user code                                         ; Off       ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off       ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off       ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off       ; Off           ;
+; Hexadecimal Output File start address                                       ; 0         ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up        ; Up            ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off       ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off       ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off       ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On        ; On            ;
+; In-System Programming Default Clamp State                                   ; Tri-state ; Tri-state     ;
++-----------------------------------------------------------------------------+-----------+---------------+
+
+
++-------------------------------------------------------------------+
+; Assembler Generated Files                                         ;
++-------------------------------------------------------------------+
+; File Name                                                         ;
++-------------------------------------------------------------------+
+; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
++-------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
++----------------+----------------------------------------------------------------------------+
+; Option         ; Setting                                                                    ;
++----------------+----------------------------------------------------------------------------+
+; Device         ; EPM240T100C5                                                               ;
+; JTAG usercode  ; 0x00161CF0                                                                 ;
+; Checksum       ; 0x001620E8                                                                 ;
++----------------+----------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Tue Sep 14 01:35:31 2021
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 381 megabytes
+    Info: Processing ended: Tue Sep 14 01:35:32 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+

cpld/output_files/GR8RAM.cdf

@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Vfy)
+		Device PartName(EPM240T100) Path("C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(2) SEC_Device(EPM240T100) Child_OpMask(2 2 2));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;

cpld/output_files/GR8RAM.done

@@ -0,0 +1 @@
+Tue Sep 14 01:35:34 2021

cpld/output_files/GR8RAM.fit.smsg

@@ -0,0 +1,4 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176244): Moving registers into LUTs to improve timing and density
+Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00

cpld/output_files/GR8RAM.fit.summary

@@ -0,0 +1,11 @@
+Fitter Status : Successful - Tue Sep 14 01:35:30 2021
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : GR8RAM
+Top-level Entity Name : GR8RAM
+Family : MAX II
+Device : EPM240T100C5
+Timing Models : Final
+Total logic elements : 234 / 240 ( 98 % )
+Total pins : 80 / 80 ( 100 % )
+Total virtual pins : 0
+UFM blocks : 0 / 1 ( 0 % )

cpld/output_files/GR8RAM.flow.rpt

@@ -0,0 +1,134 @@
+Flow report for GR8RAM
+Tue Sep 14 01:35:34 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------+
+; Flow Summary                                                                ;
++---------------------------+-------------------------------------------------+
+; Flow Status               ; Successful - Tue Sep 14 01:35:32 2021           ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name             ; GR8RAM                                          ;
+; Top-level Entity Name     ; GR8RAM                                          ;
+; Family                    ; MAX II                                          ;
+; Device                    ; EPM240T100C5                                    ;
+; Timing Models             ; Final                                           ;
+; Total logic elements      ; 234 / 240 ( 98 % )                              ;
+; Total pins                ; 80 / 80 ( 100 % )                               ;
+; Total virtual pins        ; 0                                               ;
+; UFM blocks                ; 0 / 1 ( 0 % )                                   ;
++---------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 09/14/2021 01:35:26 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; GR8RAM              ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                          ;
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
+; Assignment Name                                 ; Value                        ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
+; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP             ; On                           ; Off           ; --          ; --         ;
+; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always                       ; Auto          ; --          ; --         ;
+; ALM_REGISTER_PACKING_EFFORT                     ; High                         ; Medium        ; --          ; --         ;
+; AUTO_PACKED_REGISTERS_MAXII                     ; Minimize Area                ; Auto          ; --          ; --         ;
+; AUTO_RESOURCE_SHARING                           ; On                           ; Off           ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                           ; 962837114763.163159772501756 ; --            ; --          ; --         ;
+; FINAL_PLACEMENT_OPTIMIZATION                    ; Always                       ; Automatically ; --          ; --         ;
+; FITTER_EFFORT                                   ; Standard Fit                 ; Auto Fit      ; --          ; --         ;
+; IOBANK_VCCIO                                    ; 3.3V                         ; --            ; --          ; 1          ;
+; IOBANK_VCCIO                                    ; 3.3V                         ; --            ; --          ; 2          ;
+; MAXII_OPTIMIZATION_TECHNIQUE                    ; Area                         ; Balanced      ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                          ; 85                           ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                          ; 0                            ; --            ; --          ; --         ;
+; MUX_RESTRUCTURE                                 ; On                           ; Auto          ; --          ; --         ;
+; PLACEMENT_EFFORT_MULTIPLIER                     ; 2.0                          ; 1.0           ; --          ; --         ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR           ; 3.3V                         ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY                        ; output_files                 ; --            ; --          ; --         ;
+; REMOVE_REDUNDANT_LOGIC_CELLS                    ; On                           ; Off           ; --          ; --         ;
+; ROUTER_EFFORT_MULTIPLIER                        ; 2.0                          ; 1.0           ; --          ; --         ;
+; ROUTER_REGISTER_DUPLICATION                     ; Off                          ; Auto          ; --          ; --         ;
+; SEED                                            ; 235                          ; 1             ; --          ; --         ;
+; STATE_MACHINE_PROCESSING                        ; Minimal Bits                 ; Auto          ; --          ; --         ;
+; SYNTHESIS_SEED                                  ; 123                          ; 1             ; --          ; --         ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS                   ; Off                          ; --            ; --          ; --         ;
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 422 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:02     ; 1.0                     ; 544 MB              ; 00:00:02                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 381 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 374 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:07     ; --                      ; --                  ; 00:00:05                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
+quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+quartus_sta GR8RAM -c GR8RAM
+
+
+

cpld/output_files/GR8RAM.jdi

@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="5cae6640443712869b47"/>
+  </project>
+  <file_info>
+    <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>