Add GW4203A files

This commit is contained in:
Zane Kaminski 2020-07-25 04:36:59 -04:00
parent c8fc6df937
commit d4ddf63d99
115 changed files with 109356 additions and 0 deletions

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EESchema Schematic File Version 4
LIBS:RAM2E-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 2
Title "RAM2E"
Date "2019-10-13"
Rev "0.9"
Comp "Garrett's Workshop"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 3600 2250 2 50 ~ 0
nPRAS
Wire Wire Line
8250 2550 7400 2550
Wire Wire Line
7100 2400 8250 2400
Wire Wire Line
6200 2450 7350 2450
Wire Wire Line
6200 2300 7050 2300
Wire Wire Line
5000 2400 6150 2400
Wire Wire Line
5300 2550 6150 2550
Wire Wire Line
6200 2450 6150 2550
Wire Wire Line
6150 2400 6200 2300
Wire Wire Line
8300 2450 8750 2450
Wire Wire Line
8300 2300 8750 2300
Wire Wire Line
8250 2550 8300 2450
Wire Wire Line
8250 2400 8300 2300
Wire Wire Line
7950 2250 8000 2150
Wire Wire Line
7350 2450 7400 2550
Wire Wire Line
7050 2300 7100 2400
Text Notes 3600 2550 2 50 ~ 0
Q3
Wire Wire Line
4950 2300 5000 2400
Wire Wire Line
5250 2450 5300 2550
Text Notes 3600 2400 2 50 ~ 0
nPCAS
Wire Wire Line
5900 2150 6450 2150
Wire Wire Line
4400 2250 5850 2250
Wire Wire Line
5850 2250 5900 2150
Wire Wire Line
4350 2150 4400 2250
Wire Wire Line
3700 2400 4050 2400
Wire Wire Line
4050 2400 4100 2300
Wire Wire Line
4100 2300 4950 2300
Wire Wire Line
5250 2450 4100 2450
Wire Wire Line
4100 2450 4050 2550
Text Notes 4600 1300 0 104 ~ 0
Video Access
Text Notes 6600 1300 0 100 ~ 0
6502 CPU Access
Text Notes 8400 1800 0 40 ~ 0
E
Text Notes 3850 1800 0 40 ~ 0
D/F
Wire Wire Line
3800 1800 4050 1800
Wire Wire Line
3750 1700 3700 1700
Wire Wire Line
3800 1800 3750 1700
Wire Wire Line
3900 1400 3900 1500
Wire Wire Line
3900 1500 4050 1500
Wire Wire Line
3900 1400 3750 1400
Wire Wire Line
3750 1400 3750 1500
Wire Wire Line
3750 1500 3700 1500
Text Notes 8100 1800 0 40 ~ 0
D
Text Notes 7800 1800 0 40 ~ 0
C
Text Notes 7500 1800 0 40 ~ 0
B
Wire Wire Line
5550 1700 5600 1800
Text Notes 3600 1800 2 50 ~ 0
C7M
Wire Wire Line
4050 1800 4100 1700
Wire Wire Line
4100 1700 4350 1700
Wire Wire Line
4350 1700 4400 1800
Wire Wire Line
4400 1800 4650 1800
Wire Wire Line
4650 1800 4700 1700
Wire Wire Line
4700 1700 4950 1700
Wire Wire Line
4950 1700 5000 1800
Wire Wire Line
5000 1800 5250 1800
Wire Wire Line
5250 1800 5300 1700
Wire Wire Line
5300 1700 5550 1700
Wire Wire Line
5600 1800 5850 1800
Wire Wire Line
5850 1800 5900 1700
Wire Wire Line
5900 1700 6150 1700
Wire Wire Line
6150 1700 6200 1800
Wire Wire Line
6200 1800 6450 1800
Wire Wire Line
6450 1800 6500 1700
Wire Wire Line
6500 1700 6750 1700
Wire Wire Line
6750 1700 6800 1800
Wire Wire Line
6800 1800 7050 1800
Wire Wire Line
7050 1800 7100 1700
Wire Wire Line
7100 1700 7350 1700
Wire Wire Line
7350 1700 7400 1800
Wire Wire Line
7400 1800 7650 1800
Wire Wire Line
7650 1800 7700 1700
Wire Wire Line
7700 1700 7950 1700
Wire Wire Line
7950 1700 8000 1800
Wire Wire Line
8000 1800 8250 1800
Wire Wire Line
8250 1800 8300 1700
Wire Wire Line
8300 1700 8550 1700
Wire Wire Line
8550 1700 8600 1800
Wire Wire Line
8600 1800 8750 1800
Text Notes 6000 1800 0 40 ~ 0
6
Text Notes 5700 1800 0 40 ~ 0
5
Text Notes 5400 1800 0 40 ~ 0
4
Text Notes 5100 1800 0 40 ~ 0
3
Text Notes 4800 1800 0 40 ~ 0
2
Text Notes 4200 1800 0 40 ~ 0
E/F
Text Notes 6300 1800 0 40 ~ 0
7
Text Notes 6600 1800 0 40 ~ 0
8
Wire Wire Line
8300 1650 8750 1650
Wire Wire Line
6150 1650 6200 1550
Wire Wire Line
4100 1650 6150 1650
Text Notes 3600 1650 2 50 ~ 0
PHI0
Wire Wire Line
8700 1500 8750 1500
Wire Wire Line
8700 1400 8700 1500
Wire Wire Line
8400 1500 8550 1500
Wire Wire Line
8550 1500 8550 1400
Wire Wire Line
8400 1400 8400 1500
Wire Wire Line
8250 1400 8400 1400
Wire Wire Line
8550 1400 8700 1400
Text Notes 3600 1500 2 50 ~ 0
C14M
Wire Wire Line
8100 1500 8250 1500
Wire Wire Line
8250 1500 8250 1400
Wire Wire Line
8100 1400 8100 1500
Wire Wire Line
7950 1400 8100 1400
Wire Wire Line
7800 1400 7800 1500
Wire Wire Line
7950 1500 7950 1400
Wire Wire Line
7800 1500 7950 1500
Wire Wire Line
7650 1400 7800 1400
Wire Wire Line
7650 1500 7650 1400
Wire Wire Line
7500 1500 7650 1500
Wire Wire Line
6900 1500 7050 1500
Wire Wire Line
6900 1400 6900 1500
Wire Wire Line
7200 1500 7350 1500
Wire Wire Line
7350 1500 7350 1400
Wire Wire Line
7200 1400 7200 1500
Wire Wire Line
7050 1400 7200 1400
Wire Wire Line
7350 1400 7500 1400
Wire Wire Line
6750 1400 6900 1400
Wire Wire Line
6600 1400 6600 1500
Wire Wire Line
6600 1500 6750 1500
Wire Wire Line
6450 1400 6600 1400
Wire Wire Line
6300 1400 6300 1500
Wire Wire Line
6450 1500 6450 1400
Wire Wire Line
6300 1500 6450 1500
Wire Wire Line
5700 1500 5850 1500
Wire Wire Line
5850 1500 5850 1400
Wire Wire Line
5700 1400 5700 1500
Wire Wire Line
6000 1500 6150 1500
Wire Wire Line
6150 1500 6150 1400
Wire Wire Line
6000 1400 6000 1500
Wire Wire Line
5850 1400 6000 1400
Wire Wire Line
6150 1400 6300 1400
Wire Wire Line
5550 1400 5700 1400
Wire Wire Line
5400 1400 5400 1500
Wire Wire Line
5550 1500 5550 1400
Wire Wire Line
5400 1500 5550 1500
Wire Wire Line
5250 1400 5400 1400
Wire Wire Line
5100 1400 5100 1500
Wire Wire Line
5250 1500 5250 1400
Wire Wire Line
4500 1500 4650 1500
Wire Wire Line
4650 1500 4650 1400
Wire Wire Line
4500 1400 4500 1500
Wire Wire Line
4800 1500 4950 1500
Wire Wire Line
4950 1500 4950 1400
Wire Wire Line
4800 1400 4800 1500
Wire Wire Line
4650 1400 4800 1400
Wire Wire Line
4950 1400 5100 1400
Wire Wire Line
4350 1400 4500 1400
Wire Wire Line
4200 1400 4200 1500
Wire Wire Line
4350 1500 4350 1400
Wire Wire Line
4200 1500 4350 1500
Wire Wire Line
4050 1400 4200 1400
Wire Wire Line
4050 1500 4050 1400
Wire Wire Line
6750 1500 6750 1400
Text Notes 3650 2750 2 50 ~ 0
nRAS
Text Notes 3650 2900 2 50 ~ 0
nCAS
Wire Wire Line
3950 2800 3900 2900
Text Notes 3600 1950 2 50 ~ 0
RA[7:0]
Wire Wire Line
4400 1850 4450 1950
Wire Wire Line
4400 1950 4450 1850
Wire Wire Line
5900 1850 5950 1950
Wire Wire Line
5900 1950 5950 1850
Wire Wire Line
4450 1850 5900 1850
Wire Wire Line
4450 1950 5900 1950
Wire Wire Line
6500 1850 6550 1950
Wire Wire Line
6500 1950 6550 1850
Wire Wire Line
5950 1950 6500 1950
Wire Wire Line
6500 1850 5950 1850
Wire Wire Line
8000 1850 8050 1950
Wire Wire Line
8000 1950 8050 1850
Wire Wire Line
8050 1950 8600 1950
Wire Wire Line
8600 1850 8050 1850
Wire Wire Line
8600 1850 8650 1950
Wire Wire Line
8600 1950 8650 1850
Wire Wire Line
3800 1850 3850 1950
Wire Wire Line
3800 1950 3850 1850
Wire Wire Line
3850 1850 4400 1850
Wire Wire Line
4400 1950 3850 1950
Wire Wire Line
4350 2150 3800 2150
Wire Wire Line
3800 2150 3750 2250
Wire Wire Line
3750 2250 3700 2250
Wire Wire Line
8000 2150 8550 2150
Wire Wire Line
8550 2150 8600 2250
Wire Wire Line
8600 2250 8750 2250
Wire Wire Line
6450 2150 6500 2250
Wire Wire Line
6500 2250 7950 2250
Wire Wire Line
4050 2550 3700 2550
Wire Bus Line
4100 1350 4100 2950
Text Notes 3600 2100 2 50 ~ 0
RA[11:8]
Wire Wire Line
6150 2100 6200 2000
Wire Wire Line
6200 2000 6750 2000
Wire Wire Line
6750 2000 6800 2100
Wire Wire Line
6750 2100 6800 2000
Wire Wire Line
7350 2000 7400 2100
Wire Wire Line
8250 1550 8300 1650
Wire Wire Line
3700 1550 4050 1550
Wire Wire Line
4050 1550 4100 1650
Wire Wire Line
8650 1850 8750 1850
Wire Wire Line
8650 1950 8750 1950
Wire Wire Line
3800 1850 3700 1850
Wire Wire Line
3800 1950 3700 1950
Text Notes 6900 1800 0 40 ~ 0
9
Text Notes 7200 1800 0 40 ~ 0
A
Wire Wire Line
7500 1400 7500 1500
Text Notes 3650 4000 0 200 ~ 0
Information may be out of date,\nsuperseded by ./cpld/RAM2E.v
Wire Wire Line
3900 2900 3700 2900
Wire Bus Line
3300 2600 8800 2600
Wire Wire Line
3950 2800 4950 2800
Wire Wire Line
3700 2650 4350 2650
Wire Wire Line
4400 2750 5250 2750
Wire Wire Line
4350 2650 4400 2750
Wire Wire Line
5250 2750 5300 2650
Wire Wire Line
5900 2650 5850 2750
Wire Wire Line
6450 2650 6500 2750
Wire Wire Line
7950 2900 8000 2800
Wire Wire Line
7350 2800 7400 2900
Wire Wire Line
5900 2800 5850 2900
Wire Wire Line
4950 2800 5000 2900
Wire Bus Line
6200 1350 6200 2950
Wire Wire Line
6550 1950 8000 1950
Wire Wire Line
6550 1850 8000 1850
Wire Wire Line
7650 2750 7700 2650
Wire Wire Line
6500 2750 7650 2750
Wire Wire Line
3700 2100 6750 2100
Wire Wire Line
5600 2750 5850 2750
Wire Wire Line
5600 2750 5550 2650
Wire Wire Line
7700 2650 8750 2650
Wire Wire Line
6200 1550 8250 1550
Wire Wire Line
7050 1500 7050 1400
Wire Wire Line
6800 2000 7350 2000
Wire Wire Line
6800 2100 8750 2100
Text Notes 5600 3300 0 50 ~ 0
State = { PHI0, C7M, nPRAS, nPCAS, Q3 }
Wire Bus Line
8300 1350 8300 2950
Text Notes 4500 1800 0 40 ~ 0
1
Wire Wire Line
5900 2650 6450 2650
Wire Wire Line
5000 2900 5850 2900
Wire Wire Line
5300 2650 5550 2650
Wire Wire Line
5900 2800 7350 2800
Wire Wire Line
5100 1500 5250 1500
Wire Wire Line
7400 2900 7950 2900
Wire Wire Line
8000 2800 8750 2800
$EndSCHEMATC

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x30_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x30_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 1500 50 H V C CNN
F1 "Connector_Generic_Conn_02x30_Counter_Clockwise" 50 -1600 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1495 0 -1505 1 1 6 N
S -50 -1395 0 -1405 1 1 6 N
S -50 -1295 0 -1305 1 1 6 N
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1305 0 1295 1 1 6 N
S -50 1405 0 1395 1 1 6 N
S -50 1450 150 -1550 1 1 10 f
S 150 -1495 100 -1505 1 1 6 N
S 150 -1395 100 -1405 1 1 6 N
S 150 -1295 100 -1305 1 1 6 N
S 150 -1195 100 -1205 1 1 6 N
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
S 150 1005 100 995 1 1 6 N
S 150 1105 100 1095 1 1 6 N
S 150 1205 100 1195 1 1 6 N
S 150 1305 100 1295 1 1 6 N
S 150 1405 100 1395 1 1 6 N
X Pin_1 1 -200 1400 150 R 50 50 1 1 P
X Pin_10 10 -200 500 150 R 50 50 1 1 P
X Pin_11 11 -200 400 150 R 50 50 1 1 P
X Pin_12 12 -200 300 150 R 50 50 1 1 P
X Pin_13 13 -200 200 150 R 50 50 1 1 P
X Pin_14 14 -200 100 150 R 50 50 1 1 P
X Pin_15 15 -200 0 150 R 50 50 1 1 P
X Pin_16 16 -200 -100 150 R 50 50 1 1 P
X Pin_17 17 -200 -200 150 R 50 50 1 1 P
X Pin_18 18 -200 -300 150 R 50 50 1 1 P
X Pin_19 19 -200 -400 150 R 50 50 1 1 P
X Pin_2 2 -200 1300 150 R 50 50 1 1 P
X Pin_20 20 -200 -500 150 R 50 50 1 1 P
X Pin_21 21 -200 -600 150 R 50 50 1 1 P
X Pin_22 22 -200 -700 150 R 50 50 1 1 P
X Pin_23 23 -200 -800 150 R 50 50 1 1 P
X Pin_24 24 -200 -900 150 R 50 50 1 1 P
X Pin_25 25 -200 -1000 150 R 50 50 1 1 P
X Pin_26 26 -200 -1100 150 R 50 50 1 1 P
X Pin_27 27 -200 -1200 150 R 50 50 1 1 P
X Pin_28 28 -200 -1300 150 R 50 50 1 1 P
X Pin_29 29 -200 -1400 150 R 50 50 1 1 P
X Pin_3 3 -200 1200 150 R 50 50 1 1 P
X Pin_30 30 -200 -1500 150 R 50 50 1 1 P
X Pin_31 31 300 -1500 150 L 50 50 1 1 P
X Pin_32 32 300 -1400 150 L 50 50 1 1 P
X Pin_33 33 300 -1300 150 L 50 50 1 1 P
X Pin_34 34 300 -1200 150 L 50 50 1 1 P
X Pin_35 35 300 -1100 150 L 50 50 1 1 P
X Pin_36 36 300 -1000 150 L 50 50 1 1 P
X Pin_37 37 300 -900 150 L 50 50 1 1 P
X Pin_38 38 300 -800 150 L 50 50 1 1 P
X Pin_39 39 300 -700 150 L 50 50 1 1 P
X Pin_4 4 -200 1100 150 R 50 50 1 1 P
X Pin_40 40 300 -600 150 L 50 50 1 1 P
X Pin_41 41 300 -500 150 L 50 50 1 1 P
X Pin_42 42 300 -400 150 L 50 50 1 1 P
X Pin_43 43 300 -300 150 L 50 50 1 1 P
X Pin_44 44 300 -200 150 L 50 50 1 1 P
X Pin_45 45 300 -100 150 L 50 50 1 1 P
X Pin_46 46 300 0 150 L 50 50 1 1 P
X Pin_47 47 300 100 150 L 50 50 1 1 P
X Pin_48 48 300 200 150 L 50 50 1 1 P
X Pin_49 49 300 300 150 L 50 50 1 1 P
X Pin_5 5 -200 1000 150 R 50 50 1 1 P
X Pin_50 50 300 400 150 L 50 50 1 1 P
X Pin_51 51 300 500 150 L 50 50 1 1 P
X Pin_52 52 300 600 150 L 50 50 1 1 P
X Pin_53 53 300 700 150 L 50 50 1 1 P
X Pin_54 54 300 800 150 L 50 50 1 1 P
X Pin_55 55 300 900 150 L 50 50 1 1 P
X Pin_56 56 300 1000 150 L 50 50 1 1 P
X Pin_57 57 300 1100 150 L 50 50 1 1 P
X Pin_58 58 300 1200 150 L 50 50 1 1 P
X Pin_59 59 300 1300 150 L 50 50 1 1 P
X Pin_6 6 -200 900 150 R 50 50 1 1 P
X Pin_60 60 300 1400 150 L 50 50 1 1 P
X Pin_7 7 -200 800 150 R 50 50 1 1 P
X Pin_8 8 -200 700 150 R 50 50 1 1 P
X Pin_9 9 -200 600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_PLD.lib_EPM7128SL84
#
DEF GW_PLD.lib_EPM7128SL84 U 0 40 Y Y 1 F N
F0 "U" 0 150 50 H V C BNN
F1 "GW_PLD.lib_EPM7128SL84" 0 100 50 H V C CNN
F2 "stdpads:PLCC-84_SMDSocket" 0 0 40 H I C CNN
F3 "" -150 200 50 H I C CNN
DRAW
S -600 -1950 600 1850 0 1 10 f
X ~GClr~ 1 750 900 150 L 50 50 1 1 I
X I/O 10 750 1600 150 L 50 50 1 1 B
X I/O 11 750 1700 150 L 50 50 1 1 B
X I/O 12 -750 1700 150 R 50 50 1 1 B
X VccIO 13 -350 2000 150 D 50 50 1 1 W
X TDI 14 -750 1600 150 R 50 50 1 1 B
X I/O 15 -750 1500 150 R 50 50 1 1 B
X I/O 16 -750 1400 150 R 50 50 1 1 B
X I/O 17 -750 1300 150 R 50 50 1 1 B
X I/O 18 -750 1200 150 R 50 50 1 1 B
X GND 19 -350 -2100 150 U 50 50 1 1 W
X OE2/GClk2 2 750 1000 150 L 50 50 1 1 I
X I/O 20 -750 1100 150 R 50 50 1 1 B
X I/O 21 -750 1000 150 R 50 50 1 1 B
X I/O 22 -750 900 150 R 50 50 1 1 B
X TMS 23 -750 800 150 R 50 50 1 1 B
X I/O 24 -750 700 150 R 50 50 1 1 B
X I/O 25 -750 600 150 R 50 50 1 1 B
X VccIO 26 -250 2000 150 D 50 50 1 1 W
X I/O 27 -750 500 150 R 50 50 1 1 W
X I/O 28 -750 400 150 R 50 50 1 1 B
X I/O 29 -750 300 150 R 50 50 1 1 B
X VccINT 3 350 2000 150 D 50 50 1 1 W
X I/O 30 -750 200 150 R 50 50 1 1 B
X I/O 31 -750 100 150 R 50 50 1 1 B
X GND 32 -250 -2100 150 U 50 50 1 1 W
X I/O 33 -750 -100 150 R 50 50 1 1 B
X I/O 34 -750 -200 150 R 50 50 1 1 B
X I/O 35 -750 -300 150 R 50 50 1 1 B
X I/O 36 -750 -400 150 R 50 50 1 1 B
X I/O 37 -750 -500 150 R 50 50 1 1 B
X VccIO 38 -150 2000 150 D 50 50 1 1 W
X I/O/NC 39 -750 -600 150 R 50 50 1 1 B
X I/O 4 750 1100 150 L 50 50 1 1 B
X I/O 40 -750 -700 150 R 50 50 1 1 B
X I/O 41 -750 -800 150 R 50 50 1 1 B
X GND 42 -150 -2100 150 U 50 50 1 1 W
X VccINT 43 250 2000 150 D 50 50 1 1 W
X I/O 44 -750 -900 150 R 50 50 1 1 B
X I/O 45 -750 -1000 150 R 50 50 1 1 B
X I/O/NC 46 -750 -1100 150 R 50 50 1 1 B
X GND 47 -50 -2100 150 U 50 50 1 1 W
X I/O 48 -750 -1200 150 R 50 50 1 1 B
X I/O 49 -750 -1300 150 R 50 50 1 1 B
X I/O 5 750 1200 150 L 50 50 1 1 B
X I/O 50 -750 -1400 150 R 50 50 1 1 B
X I/O 51 -750 -1500 150 R 50 50 1 1 B
X I/O 52 -750 -1600 150 R 50 50 1 1 B
X VccIO 53 -50 2000 150 D 50 50 1 1 W
X I/O 54 750 -1800 150 L 50 50 1 1 B
X I/O 55 750 -1700 150 L 50 50 1 1 B
X I/O 56 750 -1600 150 L 50 50 1 1 B
X I/O 57 750 -1500 150 L 50 50 1 1 B
X I/O 58 750 -1400 150 L 50 50 1 1 B
X GND 59 50 -2100 150 U 50 50 1 1 W
X I/O/NC 6 750 1300 150 L 50 50 1 1 B
X I/O 60 750 -1300 150 L 50 50 1 1 B
X I/O 61 750 -1200 150 L 50 50 1 1 B
X TCK 62 750 -1100 150 L 50 50 1 1 B
X I/O 63 750 -1000 150 L 50 50 1 1 B
X I/O 64 750 -900 150 L 50 50 1 1 B
X I/O 65 750 -800 150 L 50 50 1 1 B
X VccIO 66 50 2000 150 D 50 50 1 1 W
X I/O 67 750 -700 150 L 50 50 1 1 B
X I/O 68 750 -600 150 L 50 50 1 1 B
X I/O 69 750 -500 150 L 50 50 1 1 B
X GND 7 350 -2100 150 U 50 50 1 1 W
X I/O 70 750 -400 150 L 50 50 1 1 B
X TDO 71 750 -300 150 L 50 50 1 1 B
X GND 72 150 -2100 150 U 50 50 1 1 W
X I/O 73 750 -200 150 L 50 50 1 1 B
X I/O 74 750 -100 150 L 50 50 1 1 B
X I/O 75 750 100 150 L 50 50 1 1 B
X I/O 76 750 200 150 L 50 50 1 1 B
X I/O 77 750 300 150 L 50 50 1 1 B
X VccIO 78 150 2000 150 D 50 50 1 1 W
X I/O/NC 79 750 400 150 L 50 50 1 1 B
X I/O 8 750 1400 150 L 50 50 1 1 B
X I/O 80 750 500 150 L 50 50 1 1 B
X I/O 81 750 600 150 L 50 50 1 1 B
X GND 82 250 -2100 150 U 50 50 1 1 W
X GClk1 83 750 700 150 L 50 50 1 1 I
X OE1 84 750 800 150 L 50 50 1 1 I
X I/O 9 750 1500 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_RAM.lib_DRAM-2Mx8-SOP-28
#
DEF GW_RAM.lib_DRAM-2Mx8-SOP-28 U 0 20 Y Y 1 F N
F0 "U" 0 750 50 H V C CNN
F1 "GW_RAM.lib_DRAM-2Mx8-SOP-28" 0 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -850 50 H I C CNN
F3 "" 0 -550 50 H I C CNN
DRAW
S -300 700 300 -700 0 1 10 f
X VDD 1 400 600 100 L 50 50 1 1 W
X A0 10 -400 600 100 R 50 50 1 1 I
X A1 11 -400 500 100 R 50 50 1 1 I
X A2 12 -400 400 100 R 50 50 1 1 I
X A3 13 -400 300 100 R 50 50 1 1 I
X VDD 14 400 600 100 L 50 50 1 1 W N
X GND 15 -400 -600 100 R 50 50 1 1 W N
X A4 16 -400 200 100 R 50 50 1 1 I
X A5 17 -400 100 100 R 50 50 1 1 I
X A6 18 -400 0 100 R 50 50 1 1 I
X A7 19 -400 -100 100 R 50 50 1 1 I
X I/O0 2 400 500 100 L 50 50 1 1 B
X A8 20 -400 -200 100 R 50 50 1 1 I
X A9 21 -400 -300 100 R 50 50 1 1 I
X ~OE~ 22 400 -600 100 L 50 50 1 1 I
X ~CAS~ 23 400 -300 100 L 50 50 1 1 I
X I/O4 24 400 100 100 L 50 50 1 1 B
X I/O5 25 400 0 100 L 50 50 1 1 B
X I/O6 26 400 -100 100 L 50 50 1 1 B
X I/O7 27 400 -200 100 L 50 50 1 1 B
X GND 28 -400 -600 100 R 50 50 1 1 W
X I/O1 3 400 400 100 L 50 50 1 1 B
X I/O2 4 400 300 100 L 50 50 1 1 B
X I/O3 5 400 200 100 L 50 50 1 1 B
X ~WE~ 6 400 -500 100 L 50 50 1 1 I
X ~RAS~ 7 400 -400 100 L 50 50 1 1 I
X A11/NC 8 -400 -500 100 R 50 50 1 1 I
X A10 9 -400 -400 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Mechanical_Fiducial
#
DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
F0 "FID" 0 200 50 H V C CNN
F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Fiducial*
$ENDFPLIST
DRAW
C 0 0 50 0 1 20 f
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 17:58:45 August 04, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "17:58:45 August 04, 2019"
# Revisions
PROJECT_REVISION = "RAM2E"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 17:58:45 August 04, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# RAM2E_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:58:45 AUGUST 04, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_2 -to Q3
set_location_assignment PIN_5 -to nWE
set_location_assignment PIN_6 -to nC07X
set_location_assignment PIN_8 -to nPRAS
set_location_assignment PIN_9 -to C7M
set_location_assignment PIN_1 -to Q3_2
set_location_assignment PIN_24 -to RA[10]
set_location_assignment PIN_25 -to RA[11]
set_location_assignment PIN_27 -to nCAS
set_location_assignment PIN_28 -to RD[4]
set_location_assignment PIN_29 -to RD[5]
set_location_assignment PIN_30 -to RD[6]
set_location_assignment PIN_31 -to RD[7]
set_location_assignment PIN_33 -to RD[0]
set_location_assignment PIN_34 -to RD[1]
set_location_assignment PIN_35 -to RD[2]
set_location_assignment PIN_36 -to RD[3]
set_location_assignment PIN_37 -to nRWE
set_location_assignment PIN_39 -to nRAS
set_location_assignment PIN_40 -to RA[9]
set_location_assignment PIN_41 -to RA[8]
set_location_assignment PIN_54 -to VD[7]
set_location_assignment PIN_55 -to MD[7]
set_location_assignment PIN_56 -to VD[0]
set_location_assignment PIN_57 -to MD[0]
set_location_assignment PIN_58 -to MD[6]
set_location_assignment PIN_60 -to VD[6]
set_location_assignment PIN_61 -to MD[1]
set_location_assignment PIN_63 -to VD[1]
set_location_assignment PIN_64 -to VD[5]
set_location_assignment PIN_65 -to MD[5]
set_location_assignment PIN_67 -to VD[2]
set_location_assignment PIN_68 -to MD[2]
set_location_assignment PIN_69 -to MD[4]
set_location_assignment PIN_70 -to VD[4]
set_location_assignment PIN_73 -to MD[3]
set_location_assignment PIN_74 -to VD[3]
set_location_assignment PIN_75 -to PHI0
set_location_assignment PIN_76 -to nEN80
set_location_assignment PIN_79 -to PHI1
set_location_assignment PIN_77 -to nCASEN
set_location_assignment PIN_80 -to nWE80
set_location_assignment PIN_81 -to nPCAS
set_location_assignment PIN_83 -to C14M
set_location_assignment PIN_84 -to C14M_2
set_location_assignment PIN_44 -to MA[7]
set_location_assignment PIN_45 -to MA[0]
set_location_assignment PIN_46 -to MA[1]
set_location_assignment PIN_48 -to MA[2]
set_location_assignment PIN_49 -to MA[3]
set_location_assignment PIN_50 -to MA[4]
set_location_assignment PIN_51 -to MA[5]
set_location_assignment PIN_52 -to MA[6]
set_location_assignment PIN_10 -to C3M58
set_location_assignment PIN_4 -to AN3
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_location_assignment PIN_15 -to DelayIn[1]
set_location_assignment PIN_16 -to DelayOut[1]
set_location_assignment PIN_12 -to DelayOut[0]
set_location_assignment PIN_11 -to DelayIn[0]
set_location_assignment PIN_17 -to DelayIn[2]
set_location_assignment PIN_18 -to DelayOut[2]
set_location_assignment PIN_20 -to DelayIn[3]
set_location_assignment PIN_21 -to DelayOut[3]
set_global_assignment -name MAX7000S_JTAG_USER_CODE 7A2E
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE RAM2E.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Simulation.vwf
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "Z:/Repos/RAM2E/cpld/Simulation.vwf"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_global_assignment -name AUTO_PARALLEL_EXPANDERS OFF
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name SLOW_SLEW_RATE ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
set_global_assignment -name POWER_USE_PVA OFF
set_global_assignment -name AUTO_TURBO_BIT OFF
set_location_assignment PIN_22 -to C073SEL
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayOut[1]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayOut[2]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayIn[2]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayIn[3]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayIn[1]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayOut[3]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to MDBEN

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module RAM2E(C14M, C14M_2, C7M, Q3, PHI0, PHI1,
nPRAS, nPCAS, nWE, nWE80, nEN80,
nRAS, nCAS, nRWE,
VD, MD, RD, nC07X, MA, RA,
Q3_2, C3M58, AN3, nCASEN, C073SEL,
DelayIn, DelayOut);
// Control inputs
input C14M, PHI1, C7M;
input nWE, nWE80, nEN80, nC07X;
// Unused inputs
input C14M_2, Q3_2, C3M58, Q3, PHI0;
input nPRAS, nPCAS, nCASEN, AN3;
// Delay
input [3:0] DelayIn;
output [3:0] DelayOut;
assign DelayOut[0] = 0; // RC delay unused
assign DelayOut[1] = ~nEN80;
assign DelayOut[2] = DelayIn[1];
assign DelayOut[3] = 0; // 3rd delay unused
wire EN80 = DelayIn[2]; // 2 * 15 ns delay max
reg MDBEN = 0;
// DRAM control
output reg nRAS = 1;
output reg nCAS = 1;
output nRWE = nWE80;
// Address bus and bank address registers
input [7:0] MA; // Low-order multiplexed DRAM address (input, output by Apple II)
output reg [11:8] RA = 4'h0;
reg [5:0] BA = 0; // Bank address
wire [4:0] BAS = {BA[4], BA[4] ? BA[5] : BA[3], BA[2:0]};
output reg C073SEL = 0; // Bank register select
// Video data bus
inout [7:0] VD = VDOE ? VDR[7:0] : 8'bZ;
reg [7:0] VDR; // Registered video data
wire VDOE = ~PHI1;
// 6502 data bus
inout [7:0] MD = MDOE ? MDR[7:0] : 8'bZ;
reg [7:0] MDR; // Registered DRAM read data
wire MDOE = EN80 & nWE & MDBEN;
// DRAM data bus
inout [7:0] RD = RDOE ? MD[7:0] : 8'bZ;
wire RDOE = EN80 & ~nWE;
/* State Counters */
reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
reg PHI0seen = 0; // Have we seen PHI0 since reset?
reg [3:0] S = 0; // State counter
reg [3:0] Ref = 0; // Refresh skip counter
always @(posedge C14M) begin
// Refresh counter allows DRAM refresh once every 13 cycles
if (S==4'h1) Ref <= (Ref[3:2]==2'b11) ? 4'h0 : Ref+1;
// Synchronize state counter to S1 when just entering PHI1
PHI1reg <= PHI1; // Save old PHI1
if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0
S <= (PHI1 & ~PHI1reg & PHI0seen) ? 4'h1 :
S==4'h0 ? 4'h0 :
S==4'hF ? 4'hF : S+1;
// DRAM RAS
nRAS <= ~((PHI1 & ~PHI1reg & PHI0seen) | S==4'h1 | S==4'h2 |
(S==4'h4 & Ref==0) |
S==4'h7 | S==4'h8 | S==4'h9 | S==4'hA);
// DRAM address multiplexing
RA[11:8] <=
(S==4'h6 | S==4'h7) ? {1'b0, BAS[4], BAS[3], BAS[2]} :
(S==4'h8 | S==4'h9 | S==4'hA | S==4'hB) ? {1'b0, 1'b0, BAS[1], BAS[0]} : 4'b0;
// DRAM CAS
nCAS <= ~(S==4'h2 | S==4'h3 | (S==4'h4 & Ref==0) |
S==4'hA | S==4'hB);
// Memory data bus gating (only active from S11-S15)
MDBEN <= S==4'hB | S==4'hC | S==4'hD | S==4'hE | S==4'hF;
// Latch 80-column video data at end of S3
if (S==4'h3) VDR[7:0] <= RD[7:0];
// Latch bank select at end of S7 and S8
if (S==4'h0 | S==4'h1) C073SEL <= 0;
if (S==4'h7) C073SEL <= (MA[3:0]==4'h1 | MA[3:0]==4'h3 | MA[3:0]==4'h5 | MA[3:0]==4'h7);
if (S==4'h8) C073SEL <= C073SEL & ~nC07X & ~nWE;
// Set bank register at end of S11
if (S==4'hB & C073SEL) BA[5:0] <= MD[5:0];
// Latch DRAM read data at end of S11
if (S==4'hB) MDR[7:0] <= RD[7:0];
end
endmodule

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581910344521 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581910344521 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 22:32:24 2020 " "Processing started: Sun Feb 16 22:32:24 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581910344521 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1581910344521 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1581910344521 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1581910344634 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581910344801 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 22:32:24 2020 " "Processing ended: Sun Feb 16 22:32:24 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581910344801 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581910344801 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581910344801 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1581910344801 ""}

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cpld/db/RAM2E.atom.rvd Executable file

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cpld/db/RAM2E.cmp 2.hdb Executable file

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cpld/db/RAM2E.cmp 2.rdb Executable file

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cpld/db/RAM2E.cmp 3.rdb Executable file

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cpld/db/RAM2E.cmp.logdb Executable file
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v1

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cpld/db/RAM2E.cmp0.ddb Executable file

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cpld/db/RAM2E.db_info Executable file
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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Sun Feb 16 22:19:19 2020

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cpld/db/RAM2E.eco.cdb Executable file

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cpld/db/RAM2E.eda.qmsg Executable file
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581910347194 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581910347194 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 22:32:27 2020 " "Processing started: Sun Feb 16 22:32:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581910347194 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581910347194 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_eda --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581910347194 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "RAM2E.vo C:/Users/Zane/Documents/GitHub/RAM2E/cpld/simulation/modelsim/ simulation " "Generated file RAM2E.vo in folder \"C:/Users/Zane/Documents/GitHub/RAM2E/cpld/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1581910347315 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4505 " "Peak virtual memory: 4505 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581910347350 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 22:32:27 2020 " "Processing ended: Sun Feb 16 22:32:27 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581910347350 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581910347350 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581910347350 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581910347350 ""}

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cpld/db/RAM2E.fit.qmsg Executable file
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{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1581910343507 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1581910343509 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4697 " "Peak virtual memory: 4697 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581910343685 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 22:32:23 2020 " "Processing ended: Sun Feb 16 22:32:23 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581910343685 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581910343685 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581910343685 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1581910343685 ""}

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cpld/db/RAM2E.hier_info Executable file
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|RAM2E
C14M => MDR[0].CLK
C14M => MDR[1].CLK
C14M => MDR[2].CLK
C14M => MDR[3].CLK
C14M => MDR[4].CLK
C14M => MDR[5].CLK
C14M => MDR[6].CLK
C14M => MDR[7].CLK
C14M => BA[0].CLK
C14M => BA[1].CLK
C14M => BA[2].CLK
C14M => BA[3].CLK
C14M => BA[4].CLK
C14M => BA[5].CLK
C14M => C073SEL~reg0.CLK
C14M => VDR[0].CLK
C14M => VDR[1].CLK
C14M => VDR[2].CLK
C14M => VDR[3].CLK
C14M => VDR[4].CLK
C14M => VDR[5].CLK
C14M => VDR[6].CLK
C14M => VDR[7].CLK
C14M => MDBEN.CLK
C14M => nCAS~reg0.CLK
C14M => RA[8]~reg0.CLK
C14M => RA[9]~reg0.CLK
C14M => RA[10]~reg0.CLK
C14M => RA[11]~reg0.CLK
C14M => nRAS~reg0.CLK
C14M => S[0].CLK
C14M => S[1].CLK
C14M => S[2].CLK
C14M => S[3].CLK
C14M => PHI0seen.CLK
C14M => PHI1reg.CLK
C14M => Ref[0].CLK
C14M => Ref[1].CLK
C14M => Ref[2].CLK
C14M => Ref[3].CLK
C14M_2 => ~NO_FANOUT~
C7M => ~NO_FANOUT~
Q3 => ~NO_FANOUT~
PHI0 => ~NO_FANOUT~
PHI1 => VDOE.IN0
PHI1 => nRAS.IN1
PHI1 => PHI1reg.DATAIN
PHI1 => PHI0seen.OUTPUTSELECT
nPRAS => ~NO_FANOUT~
nPCAS => ~NO_FANOUT~
nWE => comb.IN0
nWE => comb.IN0
nWE80 => nRWE.DATAIN
nEN80 => DelayOut.IN0
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRWE <= nWE80.DB_MAX_OUTPUT_PORT_TYPE
VD[0] <> VD[0]
VD[1] <> VD[1]
VD[2] <> VD[2]
VD[3] <> VD[3]
VD[4] <> VD[4]
VD[5] <> VD[5]
VD[6] <> VD[6]
VD[7] <> VD[7]
MD[0] <> MD[0]
MD[1] <> MD[1]
MD[2] <> MD[2]
MD[3] <> MD[3]
MD[4] <> MD[4]
MD[5] <> MD[5]
MD[6] <> MD[6]
MD[7] <> MD[7]
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
RD[3] <> RD[3]
RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
nC07X => C073SEL.IN0
MA[0] => Equal17.IN7
MA[0] => Equal18.IN7
MA[0] => Equal19.IN7
MA[0] => Equal20.IN7
MA[1] => Equal17.IN6
MA[1] => Equal18.IN6
MA[1] => Equal19.IN6
MA[1] => Equal20.IN6
MA[2] => Equal17.IN5
MA[2] => Equal18.IN5
MA[2] => Equal19.IN5
MA[2] => Equal20.IN5
MA[3] => Equal17.IN4
MA[3] => Equal18.IN4
MA[3] => Equal19.IN4
MA[3] => Equal20.IN4
MA[4] => ~NO_FANOUT~
MA[5] => ~NO_FANOUT~
MA[6] => ~NO_FANOUT~
MA[7] => ~NO_FANOUT~
RA[8] <= RA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[9] <= RA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE