Apple-2-HW
/
RAM2E
mirror of https://github.com/garrettsworkshop/RAM2E.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add GW4203A files

This commit is contained in:
Zane Kaminski 2020-07-25 04:36:59 -04:00
parent c8fc6df937
commit d4ddf63d99
115 changed files with 109356 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

493
Docs.sch Normal file
View File

@ -0,0 +1,493 @@
EESchema Schematic File Version 4
LIBS:RAM2E-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 2
Title "RAM2E"
Date "2019-10-13"
Rev "0.9"
Comp "Garrett's Workshop"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 3600 2250 2 50 ~ 0
nPRAS
Wire Wire Line
8250 2550 7400 2550
Wire Wire Line
7100 2400 8250 2400
Wire Wire Line
6200 2450 7350 2450
Wire Wire Line
6200 2300 7050 2300
Wire Wire Line
5000 2400 6150 2400
Wire Wire Line
5300 2550 6150 2550
Wire Wire Line
6200 2450 6150 2550
Wire Wire Line
6150 2400 6200 2300
Wire Wire Line
8300 2450 8750 2450
Wire Wire Line
8300 2300 8750 2300
Wire Wire Line
8250 2550 8300 2450
Wire Wire Line
8250 2400 8300 2300
Wire Wire Line
7950 2250 8000 2150
Wire Wire Line
7350 2450 7400 2550
Wire Wire Line
7050 2300 7100 2400
Text Notes 3600 2550 2 50 ~ 0
Q3
Wire Wire Line
4950 2300 5000 2400
Wire Wire Line
5250 2450 5300 2550
Text Notes 3600 2400 2 50 ~ 0
nPCAS
Wire Wire Line
5900 2150 6450 2150
Wire Wire Line
4400 2250 5850 2250
Wire Wire Line
5850 2250 5900 2150
Wire Wire Line
4350 2150 4400 2250
Wire Wire Line
3700 2400 4050 2400
Wire Wire Line
4050 2400 4100 2300
Wire Wire Line
4100 2300 4950 2300
Wire Wire Line
5250 2450 4100 2450
Wire Wire Line
4100 2450 4050 2550
Text Notes 4600 1300 0 104 ~ 0
Video Access
Text Notes 6600 1300 0 100 ~ 0
6502 CPU Access
Text Notes 8400 1800 0 40 ~ 0
E
Text Notes 3850 1800 0 40 ~ 0
D/F
Wire Wire Line
3800 1800 4050 1800
Wire Wire Line
3750 1700 3700 1700
Wire Wire Line
3800 1800 3750 1700
Wire Wire Line
3900 1400 3900 1500
Wire Wire Line
3900 1500 4050 1500
Wire Wire Line
3900 1400 3750 1400
Wire Wire Line
3750 1400 3750 1500
Wire Wire Line
3750 1500 3700 1500
Text Notes 8100 1800 0 40 ~ 0
D
Text Notes 7800 1800 0 40 ~ 0
C
Text Notes 7500 1800 0 40 ~ 0
B
Wire Wire Line
5550 1700 5600 1800
Text Notes 3600 1800 2 50 ~ 0
C7M
Wire Wire Line
4050 1800 4100 1700
Wire Wire Line
4100 1700 4350 1700
Wire Wire Line
4350 1700 4400 1800
Wire Wire Line
4400 1800 4650 1800
Wire Wire Line
4650 1800 4700 1700
Wire Wire Line
4700 1700 4950 1700
Wire Wire Line
4950 1700 5000 1800
Wire Wire Line
5000 1800 5250 1800
Wire Wire Line
5250 1800 5300 1700
Wire Wire Line
5300 1700 5550 1700
Wire Wire Line
5600 1800 5850 1800
Wire Wire Line
5850 1800 5900 1700
Wire Wire Line
5900 1700 6150 1700
Wire Wire Line
6150 1700 6200 1800
Wire Wire Line
6200 1800 6450 1800
Wire Wire Line
6450 1800 6500 1700
Wire Wire Line
6500 1700 6750 1700
Wire Wire Line
6750 1700 6800 1800
Wire Wire Line
6800 1800 7050 1800
Wire Wire Line
7050 1800 7100 1700
Wire Wire Line
7100 1700 7350 1700
Wire Wire Line
7350 1700 7400 1800
Wire Wire Line
7400 1800 7650 1800
Wire Wire Line
7650 1800 7700 1700
Wire Wire Line
7700 1700 7950 1700
Wire Wire Line
7950 1700 8000 1800
Wire Wire Line
8000 1800 8250 1800
Wire Wire Line
8250 1800 8300 1700
Wire Wire Line
8300 1700 8550 1700
Wire Wire Line
8550 1700 8600 1800
Wire Wire Line
8600 1800 8750 1800
Text Notes 6000 1800 0 40 ~ 0
6
Text Notes 5700 1800 0 40 ~ 0
5
Text Notes 5400 1800 0 40 ~ 0
4
Text Notes 5100 1800 0 40 ~ 0
3
Text Notes 4800 1800 0 40 ~ 0
2
Text Notes 4200 1800 0 40 ~ 0
E/F
Text Notes 6300 1800 0 40 ~ 0
7
Text Notes 6600 1800 0 40 ~ 0
8
Wire Wire Line
8300 1650 8750 1650
Wire Wire Line
6150 1650 6200 1550
Wire Wire Line
4100 1650 6150 1650
Text Notes 3600 1650 2 50 ~ 0
PHI0
Wire Wire Line
8700 1500 8750 1500
Wire Wire Line
8700 1400 8700 1500
Wire Wire Line
8400 1500 8550 1500
Wire Wire Line
8550 1500 8550 1400
Wire Wire Line
8400 1400 8400 1500
Wire Wire Line
8250 1400 8400 1400
Wire Wire Line
8550 1400 8700 1400
Text Notes 3600 1500 2 50 ~ 0
C14M
Wire Wire Line
8100 1500 8250 1500
Wire Wire Line
8250 1500 8250 1400
Wire Wire Line
8100 1400 8100 1500
Wire Wire Line
7950 1400 8100 1400
Wire Wire Line
7800 1400 7800 1500
Wire Wire Line
7950 1500 7950 1400
Wire Wire Line
7800 1500 7950 1500
Wire Wire Line
7650 1400 7800 1400
Wire Wire Line
7650 1500 7650 1400
Wire Wire Line
7500 1500 7650 1500
Wire Wire Line
6900 1500 7050 1500
Wire Wire Line
6900 1400 6900 1500
Wire Wire Line
7200 1500 7350 1500
Wire Wire Line
7350 1500 7350 1400
Wire Wire Line
7200 1400 7200 1500
Wire Wire Line
7050 1400 7200 1400
Wire Wire Line
7350 1400 7500 1400
Wire Wire Line
6750 1400 6900 1400
Wire Wire Line
6600 1400 6600 1500
Wire Wire Line
6600 1500 6750 1500
Wire Wire Line
6450 1400 6600 1400
Wire Wire Line
6300 1400 6300 1500
Wire Wire Line
6450 1500 6450 1400
Wire Wire Line
6300 1500 6450 1500
Wire Wire Line
5700 1500 5850 1500
Wire Wire Line
5850 1500 5850 1400
Wire Wire Line
5700 1400 5700 1500
Wire Wire Line
6000 1500 6150 1500
Wire Wire Line
6150 1500 6150 1400
Wire Wire Line
6000 1400 6000 1500
Wire Wire Line
5850 1400 6000 1400
Wire Wire Line
6150 1400 6300 1400
Wire Wire Line
5550 1400 5700 1400
Wire Wire Line
5400 1400 5400 1500
Wire Wire Line
5550 1500 5550 1400
Wire Wire Line
5400 1500 5550 1500
Wire Wire Line
5250 1400 5400 1400
Wire Wire Line
5100 1400 5100 1500
Wire Wire Line
5250 1500 5250 1400
Wire Wire Line
4500 1500 4650 1500
Wire Wire Line
4650 1500 4650 1400
Wire Wire Line
4500 1400 4500 1500
Wire Wire Line
4800 1500 4950 1500
Wire Wire Line
4950 1500 4950 1400
Wire Wire Line
4800 1400 4800 1500
Wire Wire Line
4650 1400 4800 1400
Wire Wire Line
4950 1400 5100 1400
Wire Wire Line
4350 1400 4500 1400
Wire Wire Line
4200 1400 4200 1500
Wire Wire Line
4350 1500 4350 1400
Wire Wire Line
4200 1500 4350 1500
Wire Wire Line
4050 1400 4200 1400
Wire Wire Line
4050 1500 4050 1400
Wire Wire Line
6750 1500 6750 1400
Text Notes 3650 2750 2 50 ~ 0
nRAS
Text Notes 3650 2900 2 50 ~ 0
nCAS
Wire Wire Line
3950 2800 3900 2900
Text Notes 3600 1950 2 50 ~ 0
RA[7:0]
Wire Wire Line
4400 1850 4450 1950
Wire Wire Line
4400 1950 4450 1850
Wire Wire Line
5900 1850 5950 1950
Wire Wire Line
5900 1950 5950 1850
Wire Wire Line
4450 1850 5900 1850
Wire Wire Line
4450 1950 5900 1950
Wire Wire Line
6500 1850 6550 1950
Wire Wire Line
6500 1950 6550 1850
Wire Wire Line
5950 1950 6500 1950
Wire Wire Line
6500 1850 5950 1850
Wire Wire Line
8000 1850 8050 1950
Wire Wire Line
8000 1950 8050 1850
Wire Wire Line
8050 1950 8600 1950
Wire Wire Line
8600 1850 8050 1850
Wire Wire Line
8600 1850 8650 1950
Wire Wire Line
8600 1950 8650 1850
Wire Wire Line
3800 1850 3850 1950
Wire Wire Line
3800 1950 3850 1850
Wire Wire Line
3850 1850 4400 1850
Wire Wire Line
4400 1950 3850 1950
Wire Wire Line
4350 2150 3800 2150
Wire Wire Line
3800 2150 3750 2250
Wire Wire Line
3750 2250 3700 2250
Wire Wire Line
8000 2150 8550 2150
Wire Wire Line
8550 2150 8600 2250
Wire Wire Line
8600 2250 8750 2250
Wire Wire Line
6450 2150 6500 2250
Wire Wire Line
6500 2250 7950 2250
Wire Wire Line
4050 2550 3700 2550
Wire Bus Line
4100 1350 4100 2950
Text Notes 3600 2100 2 50 ~ 0
RA[11:8]
Wire Wire Line
6150 2100 6200 2000
Wire Wire Line
6200 2000 6750 2000
Wire Wire Line
6750 2000 6800 2100
Wire Wire Line
6750 2100 6800 2000
Wire Wire Line
7350 2000 7400 2100
Wire Wire Line
8250 1550 8300 1650
Wire Wire Line
3700 1550 4050 1550
Wire Wire Line
4050 1550 4100 1650
Wire Wire Line
8650 1850 8750 1850
Wire Wire Line
8650 1950 8750 1950
Wire Wire Line
3800 1850 3700 1850
Wire Wire Line
3800 1950 3700 1950
Text Notes 6900 1800 0 40 ~ 0
9
Text Notes 7200 1800 0 40 ~ 0
A
Wire Wire Line
7500 1400 7500 1500
Text Notes 3650 4000 0 200 ~ 0
Information may be out of date,\nsuperseded by ./cpld/RAM2E.v
Wire Wire Line
3900 2900 3700 2900
Wire Bus Line
3300 2600 8800 2600
Wire Wire Line
3950 2800 4950 2800
Wire Wire Line
3700 2650 4350 2650
Wire Wire Line
4400 2750 5250 2750
Wire Wire Line
4350 2650 4400 2750
Wire Wire Line
5250 2750 5300 2650
Wire Wire Line
5900 2650 5850 2750
Wire Wire Line
6450 2650 6500 2750
Wire Wire Line
7950 2900 8000 2800
Wire Wire Line
7350 2800 7400 2900
Wire Wire Line
5900 2800 5850 2900
Wire Wire Line
4950 2800 5000 2900
Wire Bus Line
6200 1350 6200 2950
Wire Wire Line
6550 1950 8000 1950
Wire Wire Line
6550 1850 8000 1850
Wire Wire Line
7650 2750 7700 2650
Wire Wire Line
6500 2750 7650 2750
Wire Wire Line
3700 2100 6750 2100
Wire Wire Line
5600 2750 5850 2750
Wire Wire Line
5600 2750 5550 2650
Wire Wire Line
7700 2650 8750 2650
Wire Wire Line
6200 1550 8250 1550
Wire Wire Line
7050 1500 7050 1400
Wire Wire Line
6800 2000 7350 2000
Wire Wire Line
6800 2100 8750 2100
Text Notes 5600 3300 0 50 ~ 0
State = { PHI0, C7M, nPRAS, nPCAS, Q3 }
Wire Bus Line
8300 1350 8300 2950
Text Notes 4500 1800 0 40 ~ 0
1
Wire Wire Line
5900 2650 6450 2650
Wire Wire Line
5000 2900 5850 2900
Wire Wire Line
5300 2650 5550 2650
Wire Wire Line
5900 2800 7350 2800
Wire Wire Line
5100 1500 5250 1500
Wire Wire Line
7400 2900 7950 2900
Wire Wire Line
8000 2800 8750 2800
$EndSCHEMATC

BIN
Documentation/GW4203A Instructions.docx Normal file
View File

Binary file not shown.

BIN
Documentation/GW4203A Instructions.pdf Normal file
View File

Binary file not shown.

BIN
Documentation/RAM2E Label Cropped.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 80 KiB

5684
Documentation/RAM2E Label.ai Normal file
View File

File diff suppressed because one or more lines are too long

BIN
Documentation/RAM2E Label.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 45 KiB

BIN
Documentation/RAM2E-rendering.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 265 KiB

BIN
Documentation/RAM2E.pdf Normal file
View File

Binary file not shown.

369
RAM2E-cache.lib Normal file
View File

@ -0,0 +1,369 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x30_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x30_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 1500 50 H V C CNN
F1 "Connector_Generic_Conn_02x30_Counter_Clockwise" 50 -1600 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1495 0 -1505 1 1 6 N
S -50 -1395 0 -1405 1 1 6 N
S -50 -1295 0 -1305 1 1 6 N
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1305 0 1295 1 1 6 N
S -50 1405 0 1395 1 1 6 N
S -50 1450 150 -1550 1 1 10 f
S 150 -1495 100 -1505 1 1 6 N
S 150 -1395 100 -1405 1 1 6 N
S 150 -1295 100 -1305 1 1 6 N
S 150 -1195 100 -1205 1 1 6 N
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
S 150 1005 100 995 1 1 6 N
S 150 1105 100 1095 1 1 6 N
S 150 1205 100 1195 1 1 6 N
S 150 1305 100 1295 1 1 6 N
S 150 1405 100 1395 1 1 6 N
X Pin_1 1 -200 1400 150 R 50 50 1 1 P
X Pin_10 10 -200 500 150 R 50 50 1 1 P
X Pin_11 11 -200 400 150 R 50 50 1 1 P
X Pin_12 12 -200 300 150 R 50 50 1 1 P
X Pin_13 13 -200 200 150 R 50 50 1 1 P
X Pin_14 14 -200 100 150 R 50 50 1 1 P
X Pin_15 15 -200 0 150 R 50 50 1 1 P
X Pin_16 16 -200 -100 150 R 50 50 1 1 P
X Pin_17 17 -200 -200 150 R 50 50 1 1 P
X Pin_18 18 -200 -300 150 R 50 50 1 1 P
X Pin_19 19 -200 -400 150 R 50 50 1 1 P
X Pin_2 2 -200 1300 150 R 50 50 1 1 P
X Pin_20 20 -200 -500 150 R 50 50 1 1 P
X Pin_21 21 -200 -600 150 R 50 50 1 1 P
X Pin_22 22 -200 -700 150 R 50 50 1 1 P
X Pin_23 23 -200 -800 150 R 50 50 1 1 P
X Pin_24 24 -200 -900 150 R 50 50 1 1 P
X Pin_25 25 -200 -1000 150 R 50 50 1 1 P
X Pin_26 26 -200 -1100 150 R 50 50 1 1 P
X Pin_27 27 -200 -1200 150 R 50 50 1 1 P
X Pin_28 28 -200 -1300 150 R 50 50 1 1 P
X Pin_29 29 -200 -1400 150 R 50 50 1 1 P
X Pin_3 3 -200 1200 150 R 50 50 1 1 P
X Pin_30 30 -200 -1500 150 R 50 50 1 1 P
X Pin_31 31 300 -1500 150 L 50 50 1 1 P
X Pin_32 32 300 -1400 150 L 50 50 1 1 P
X Pin_33 33 300 -1300 150 L 50 50 1 1 P
X Pin_34 34 300 -1200 150 L 50 50 1 1 P
X Pin_35 35 300 -1100 150 L 50 50 1 1 P
X Pin_36 36 300 -1000 150 L 50 50 1 1 P
X Pin_37 37 300 -900 150 L 50 50 1 1 P
X Pin_38 38 300 -800 150 L 50 50 1 1 P
X Pin_39 39 300 -700 150 L 50 50 1 1 P
X Pin_4 4 -200 1100 150 R 50 50 1 1 P
X Pin_40 40 300 -600 150 L 50 50 1 1 P
X Pin_41 41 300 -500 150 L 50 50 1 1 P
X Pin_42 42 300 -400 150 L 50 50 1 1 P
X Pin_43 43 300 -300 150 L 50 50 1 1 P
X Pin_44 44 300 -200 150 L 50 50 1 1 P
X Pin_45 45 300 -100 150 L 50 50 1 1 P
X Pin_46 46 300 0 150 L 50 50 1 1 P
X Pin_47 47 300 100 150 L 50 50 1 1 P
X Pin_48 48 300 200 150 L 50 50 1 1 P
X Pin_49 49 300 300 150 L 50 50 1 1 P
X Pin_5 5 -200 1000 150 R 50 50 1 1 P
X Pin_50 50 300 400 150 L 50 50 1 1 P
X Pin_51 51 300 500 150 L 50 50 1 1 P
X Pin_52 52 300 600 150 L 50 50 1 1 P
X Pin_53 53 300 700 150 L 50 50 1 1 P
X Pin_54 54 300 800 150 L 50 50 1 1 P
X Pin_55 55 300 900 150 L 50 50 1 1 P
X Pin_56 56 300 1000 150 L 50 50 1 1 P
X Pin_57 57 300 1100 150 L 50 50 1 1 P
X Pin_58 58 300 1200 150 L 50 50 1 1 P
X Pin_59 59 300 1300 150 L 50 50 1 1 P
X Pin_6 6 -200 900 150 R 50 50 1 1 P
X Pin_60 60 300 1400 150 L 50 50 1 1 P
X Pin_7 7 -200 800 150 R 50 50 1 1 P
X Pin_8 8 -200 700 150 R 50 50 1 1 P
X Pin_9 9 -200 600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_PLD.lib_EPM7128SL84
#
DEF GW_PLD.lib_EPM7128SL84 U 0 40 Y Y 1 F N
F0 "U" 0 150 50 H V C BNN
F1 "GW_PLD.lib_EPM7128SL84" 0 100 50 H V C CNN
F2 "stdpads:PLCC-84_SMDSocket" 0 0 40 H I C CNN
F3 "" -150 200 50 H I C CNN
DRAW
S -600 -1950 600 1850 0 1 10 f
X ~GClr~ 1 750 900 150 L 50 50 1 1 I
X I/O 10 750 1600 150 L 50 50 1 1 B
X I/O 11 750 1700 150 L 50 50 1 1 B
X I/O 12 -750 1700 150 R 50 50 1 1 B
X VccIO 13 -350 2000 150 D 50 50 1 1 W
X TDI 14 -750 1600 150 R 50 50 1 1 B
X I/O 15 -750 1500 150 R 50 50 1 1 B
X I/O 16 -750 1400 150 R 50 50 1 1 B
X I/O 17 -750 1300 150 R 50 50 1 1 B
X I/O 18 -750 1200 150 R 50 50 1 1 B
X GND 19 -350 -2100 150 U 50 50 1 1 W
X OE2/GClk2 2 750 1000 150 L 50 50 1 1 I
X I/O 20 -750 1100 150 R 50 50 1 1 B
X I/O 21 -750 1000 150 R 50 50 1 1 B
X I/O 22 -750 900 150 R 50 50 1 1 B
X TMS 23 -750 800 150 R 50 50 1 1 B
X I/O 24 -750 700 150 R 50 50 1 1 B
X I/O 25 -750 600 150 R 50 50 1 1 B
X VccIO 26 -250 2000 150 D 50 50 1 1 W
X I/O 27 -750 500 150 R 50 50 1 1 W
X I/O 28 -750 400 150 R 50 50 1 1 B
X I/O 29 -750 300 150 R 50 50 1 1 B
X VccINT 3 350 2000 150 D 50 50 1 1 W
X I/O 30 -750 200 150 R 50 50 1 1 B
X I/O 31 -750 100 150 R 50 50 1 1 B
X GND 32 -250 -2100 150 U 50 50 1 1 W
X I/O 33 -750 -100 150 R 50 50 1 1 B
X I/O 34 -750 -200 150 R 50 50 1 1 B
X I/O 35 -750 -300 150 R 50 50 1 1 B
X I/O 36 -750 -400 150 R 50 50 1 1 B
X I/O 37 -750 -500 150 R 50 50 1 1 B
X VccIO 38 -150 2000 150 D 50 50 1 1 W
X I/O/NC 39 -750 -600 150 R 50 50 1 1 B
X I/O 4 750 1100 150 L 50 50 1 1 B
X I/O 40 -750 -700 150 R 50 50 1 1 B
X I/O 41 -750 -800 150 R 50 50 1 1 B
X GND 42 -150 -2100 150 U 50 50 1 1 W
X VccINT 43 250 2000 150 D 50 50 1 1 W
X I/O 44 -750 -900 150 R 50 50 1 1 B
X I/O 45 -750 -1000 150 R 50 50 1 1 B
X I/O/NC 46 -750 -1100 150 R 50 50 1 1 B
X GND 47 -50 -2100 150 U 50 50 1 1 W
X I/O 48 -750 -1200 150 R 50 50 1 1 B
X I/O 49 -750 -1300 150 R 50 50 1 1 B
X I/O 5 750 1200 150 L 50 50 1 1 B
X I/O 50 -750 -1400 150 R 50 50 1 1 B
X I/O 51 -750 -1500 150 R 50 50 1 1 B
X I/O 52 -750 -1600 150 R 50 50 1 1 B
X VccIO 53 -50 2000 150 D 50 50 1 1 W
X I/O 54 750 -1800 150 L 50 50 1 1 B
X I/O 55 750 -1700 150 L 50 50 1 1 B
X I/O 56 750 -1600 150 L 50 50 1 1 B
X I/O 57 750 -1500 150 L 50 50 1 1 B
X I/O 58 750 -1400 150 L 50 50 1 1 B
X GND 59 50 -2100 150 U 50 50 1 1 W
X I/O/NC 6 750 1300 150 L 50 50 1 1 B
X I/O 60 750 -1300 150 L 50 50 1 1 B
X I/O 61 750 -1200 150 L 50 50 1 1 B
X TCK 62 750 -1100 150 L 50 50 1 1 B
X I/O 63 750 -1000 150 L 50 50 1 1 B
X I/O 64 750 -900 150 L 50 50 1 1 B
X I/O 65 750 -800 150 L 50 50 1 1 B
X VccIO 66 50 2000 150 D 50 50 1 1 W
X I/O 67 750 -700 150 L 50 50 1 1 B
X I/O 68 750 -600 150 L 50 50 1 1 B
X I/O 69 750 -500 150 L 50 50 1 1 B
X GND 7 350 -2100 150 U 50 50 1 1 W
X I/O 70 750 -400 150 L 50 50 1 1 B
X TDO 71 750 -300 150 L 50 50 1 1 B
X GND 72 150 -2100 150 U 50 50 1 1 W
X I/O 73 750 -200 150 L 50 50 1 1 B
X I/O 74 750 -100 150 L 50 50 1 1 B
X I/O 75 750 100 150 L 50 50 1 1 B
X I/O 76 750 200 150 L 50 50 1 1 B
X I/O 77 750 300 150 L 50 50 1 1 B
X VccIO 78 150 2000 150 D 50 50 1 1 W
X I/O/NC 79 750 400 150 L 50 50 1 1 B
X I/O 8 750 1400 150 L 50 50 1 1 B
X I/O 80 750 500 150 L 50 50 1 1 B
X I/O 81 750 600 150 L 50 50 1 1 B
X GND 82 250 -2100 150 U 50 50 1 1 W
X GClk1 83 750 700 150 L 50 50 1 1 I
X OE1 84 750 800 150 L 50 50 1 1 I
X I/O 9 750 1500 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_RAM.lib_DRAM-2Mx8-SOP-28
#
DEF GW_RAM.lib_DRAM-2Mx8-SOP-28 U 0 20 Y Y 1 F N
F0 "U" 0 750 50 H V C CNN
F1 "GW_RAM.lib_DRAM-2Mx8-SOP-28" 0 0 50 V V C CNN
F2 "stdpads:SOP-24-26-300mil" 0 -850 50 H I C CNN
F3 "" 0 -550 50 H I C CNN
DRAW
S -300 700 300 -700 0 1 10 f
X VDD 1 400 600 100 L 50 50 1 1 W
X A0 10 -400 600 100 R 50 50 1 1 I
X A1 11 -400 500 100 R 50 50 1 1 I
X A2 12 -400 400 100 R 50 50 1 1 I
X A3 13 -400 300 100 R 50 50 1 1 I
X VDD 14 400 600 100 L 50 50 1 1 W N
X GND 15 -400 -600 100 R 50 50 1 1 W N
X A4 16 -400 200 100 R 50 50 1 1 I
X A5 17 -400 100 100 R 50 50 1 1 I
X A6 18 -400 0 100 R 50 50 1 1 I
X A7 19 -400 -100 100 R 50 50 1 1 I
X I/O0 2 400 500 100 L 50 50 1 1 B
X A8 20 -400 -200 100 R 50 50 1 1 I
X A9 21 -400 -300 100 R 50 50 1 1 I
X ~OE~ 22 400 -600 100 L 50 50 1 1 I
X ~CAS~ 23 400 -300 100 L 50 50 1 1 I
X I/O4 24 400 100 100 L 50 50 1 1 B
X I/O5 25 400 0 100 L 50 50 1 1 B
X I/O6 26 400 -100 100 L 50 50 1 1 B
X I/O7 27 400 -200 100 L 50 50 1 1 B
X GND 28 -400 -600 100 R 50 50 1 1 W
X I/O1 3 400 400 100 L 50 50 1 1 B
X I/O2 4 400 300 100 L 50 50 1 1 B
X I/O3 5 400 200 100 L 50 50 1 1 B
X ~WE~ 6 400 -500 100 L 50 50 1 1 I
X ~RAS~ 7 400 -400 100 L 50 50 1 1 I
X A11/NC 8 -400 -500 100 R 50 50 1 1 I
X A10 9 -400 -400 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Mechanical_Fiducial
#
DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
F0 "FID" 0 200 50 H V C CNN
F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Fiducial*
$ENDFPLIST
DRAW
C 0 0 50 0 1 20 f
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

BIN
RAM2E-gerber.zip Normal file
View File

Binary file not shown.

4889
RAM2E.kicad_pcb Normal file
View File

File diff suppressed because it is too large Load Diff

260
RAM2E.pro Normal file
View File

@ -0,0 +1,260 @@
update=Monday, October 14, 2019 at 08:24:16 AM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=RAM2E.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.508
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.2
TrackWidth3=0.254
TrackWidth4=0.508
TrackWidth5=0.762
TrackWidth6=1.27
TrackWidth7=1.524
ViaDiameter1=0.6
ViaDrill1=0.3
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
ViaDiameter4=1.524
ViaDrill4=0.762
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.1524
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0.127
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

1239
RAM2E.sch Normal file
View File

File diff suppressed because it is too large Load Diff

30
cpld/RAM2E.qpf Executable file
View File

@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 17:58:45 August 04, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "17:58:45 August 04, 2019"
# Revisions
PROJECT_REVISION = "RAM2E"

148
cpld/RAM2E.qsf Executable file
View File

@ -0,0 +1,148 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 17:58:45 August 04, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# RAM2E_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:58:45 AUGUST 04, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_2 -to Q3
set_location_assignment PIN_5 -to nWE
set_location_assignment PIN_6 -to nC07X
set_location_assignment PIN_8 -to nPRAS
set_location_assignment PIN_9 -to C7M
set_location_assignment PIN_1 -to Q3_2
set_location_assignment PIN_24 -to RA[10]
set_location_assignment PIN_25 -to RA[11]
set_location_assignment PIN_27 -to nCAS
set_location_assignment PIN_28 -to RD[4]
set_location_assignment PIN_29 -to RD[5]
set_location_assignment PIN_30 -to RD[6]
set_location_assignment PIN_31 -to RD[7]
set_location_assignment PIN_33 -to RD[0]
set_location_assignment PIN_34 -to RD[1]
set_location_assignment PIN_35 -to RD[2]
set_location_assignment PIN_36 -to RD[3]
set_location_assignment PIN_37 -to nRWE
set_location_assignment PIN_39 -to nRAS
set_location_assignment PIN_40 -to RA[9]
set_location_assignment PIN_41 -to RA[8]
set_location_assignment PIN_54 -to VD[7]
set_location_assignment PIN_55 -to MD[7]
set_location_assignment PIN_56 -to VD[0]
set_location_assignment PIN_57 -to MD[0]
set_location_assignment PIN_58 -to MD[6]
set_location_assignment PIN_60 -to VD[6]
set_location_assignment PIN_61 -to MD[1]
set_location_assignment PIN_63 -to VD[1]
set_location_assignment PIN_64 -to VD[5]
set_location_assignment PIN_65 -to MD[5]
set_location_assignment PIN_67 -to VD[2]
set_location_assignment PIN_68 -to MD[2]
set_location_assignment PIN_69 -to MD[4]
set_location_assignment PIN_70 -to VD[4]
set_location_assignment PIN_73 -to MD[3]
set_location_assignment PIN_74 -to VD[3]
set_location_assignment PIN_75 -to PHI0
set_location_assignment PIN_76 -to nEN80
set_location_assignment PIN_79 -to PHI1
set_location_assignment PIN_77 -to nCASEN
set_location_assignment PIN_80 -to nWE80
set_location_assignment PIN_81 -to nPCAS
set_location_assignment PIN_83 -to C14M
set_location_assignment PIN_84 -to C14M_2
set_location_assignment PIN_44 -to MA[7]
set_location_assignment PIN_45 -to MA[0]
set_location_assignment PIN_46 -to MA[1]
set_location_assignment PIN_48 -to MA[2]
set_location_assignment PIN_49 -to MA[3]
set_location_assignment PIN_50 -to MA[4]
set_location_assignment PIN_51 -to MA[5]
set_location_assignment PIN_52 -to MA[6]
set_location_assignment PIN_10 -to C3M58
set_location_assignment PIN_4 -to AN3
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_location_assignment PIN_15 -to DelayIn[1]
set_location_assignment PIN_16 -to DelayOut[1]
set_location_assignment PIN_12 -to DelayOut[0]
set_location_assignment PIN_11 -to DelayIn[0]
set_location_assignment PIN_17 -to DelayIn[2]
set_location_assignment PIN_18 -to DelayOut[2]
set_location_assignment PIN_20 -to DelayIn[3]
set_location_assignment PIN_21 -to DelayOut[3]
set_global_assignment -name MAX7000S_JTAG_USER_CODE 7A2E
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE RAM2E.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Simulation.vwf
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "Z:/Repos/RAM2E/cpld/Simulation.vwf"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_global_assignment -name AUTO_PARALLEL_EXPANDERS OFF
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name SLOW_SLEW_RATE ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
set_global_assignment -name POWER_USE_PVA OFF
set_global_assignment -name AUTO_TURBO_BIT OFF
set_location_assignment PIN_22 -to C073SEL
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayOut[1]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayOut[2]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayIn[2]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayIn[3]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayIn[1]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to DelayOut[3]
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to MDBEN

BIN
cpld/RAM2E.qws Executable file
View File

Binary file not shown.

100
cpld/RAM2E.v Normal file
View File

@ -0,0 +1,100 @@
module RAM2E(C14M, C14M_2, C7M, Q3, PHI0, PHI1,
nPRAS, nPCAS, nWE, nWE80, nEN80,
nRAS, nCAS, nRWE,
VD, MD, RD, nC07X, MA, RA,
Q3_2, C3M58, AN3, nCASEN, C073SEL,
DelayIn, DelayOut);
// Control inputs
input C14M, PHI1, C7M;
input nWE, nWE80, nEN80, nC07X;
// Unused inputs
input C14M_2, Q3_2, C3M58, Q3, PHI0;
input nPRAS, nPCAS, nCASEN, AN3;
// Delay
input [3:0] DelayIn;
output [3:0] DelayOut;
assign DelayOut[0] = 0; // RC delay unused
assign DelayOut[1] = ~nEN80;
assign DelayOut[2] = DelayIn[1];
assign DelayOut[3] = 0; // 3rd delay unused
wire EN80 = DelayIn[2]; // 2 * 15 ns delay max
reg MDBEN = 0;
// DRAM control
output reg nRAS = 1;
output reg nCAS = 1;
output nRWE = nWE80;
// Address bus and bank address registers
input [7:0] MA; // Low-order multiplexed DRAM address (input, output by Apple II)
output reg [11:8] RA = 4'h0;
reg [5:0] BA = 0; // Bank address
wire [4:0] BAS = {BA[4], BA[4] ? BA[5] : BA[3], BA[2:0]};
output reg C073SEL = 0; // Bank register select
// Video data bus
inout [7:0] VD = VDOE ? VDR[7:0] : 8'bZ;
reg [7:0] VDR; // Registered video data
wire VDOE = ~PHI1;
// 6502 data bus
inout [7:0] MD = MDOE ? MDR[7:0] : 8'bZ;
reg [7:0] MDR; // Registered DRAM read data
wire MDOE = EN80 & nWE & MDBEN;
// DRAM data bus
inout [7:0] RD = RDOE ? MD[7:0] : 8'bZ;
wire RDOE = EN80 & ~nWE;
/* State Counters */
reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
reg PHI0seen = 0; // Have we seen PHI0 since reset?
reg [3:0] S = 0; // State counter
reg [3:0] Ref = 0; // Refresh skip counter
always @(posedge C14M) begin
// Refresh counter allows DRAM refresh once every 13 cycles
if (S==4'h1) Ref <= (Ref[3:2]==2'b11) ? 4'h0 : Ref+1;
// Synchronize state counter to S1 when just entering PHI1
PHI1reg <= PHI1; // Save old PHI1
if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0
S <= (PHI1 & ~PHI1reg & PHI0seen) ? 4'h1 :
S==4'h0 ? 4'h0 :
S==4'hF ? 4'hF : S+1;
// DRAM RAS
nRAS <= ~((PHI1 & ~PHI1reg & PHI0seen) | S==4'h1 | S==4'h2 |
(S==4'h4 & Ref==0) |
S==4'h7 | S==4'h8 | S==4'h9 | S==4'hA);
// DRAM address multiplexing
RA[11:8] <=
(S==4'h6 | S==4'h7) ? {1'b0, BAS[4], BAS[3], BAS[2]} :
(S==4'h8 | S==4'h9 | S==4'hA | S==4'hB) ? {1'b0, 1'b0, BAS[1], BAS[0]} : 4'b0;
// DRAM CAS
nCAS <= ~(S==4'h2 | S==4'h3 | (S==4'h4 & Ref==0) |
S==4'hA | S==4'hB);
// Memory data bus gating (only active from S11-S15)
MDBEN <= S==4'hB | S==4'hC | S==4'hD | S==4'hE | S==4'hF;
// Latch 80-column video data at end of S3
if (S==4'h3) VDR[7:0] <= RD[7:0];
// Latch bank select at end of S7 and S8
if (S==4'h0 | S==4'h1) C073SEL <= 0;
if (S==4'h7) C073SEL <= (MA[3:0]==4'h1 | MA[3:0]==4'h3 | MA[3:0]==4'h5 | MA[3:0]==4'h7);
if (S==4'h8) C073SEL <= C073SEL & ~nC07X & ~nWE;
// Set bank register at end of S11
if (S==4'hB & C073SEL) BA[5:0] <= MD[5:0];
// Latch DRAM read data at end of S11
if (S==4'hB) MDR[7:0] <= RD[7:0];
end
endmodule

1880
cpld/Simulation.vwf Executable file
View File

File diff suppressed because it is too large Load Diff

BIN
cpld/db/RAM2E.(0).cnf.cdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.(0).cnf.hdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.(1).cnf.cdb Normal file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.(1).cnf.hdb Normal file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.ace_cmp.cdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.ace_cmp.hdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.acvq.rdb Normal file
View File

Binary file not shown.

5
cpld/db/RAM2E.asm.qmsg Executable file
View File

@ -0,0 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581910344521 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581910344521 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 22:32:24 2020 " "Processing started: Sun Feb 16 22:32:24 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581910344521 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1581910344521 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1581910344521 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1581910344634 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581910344801 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 22:32:24 2020 " "Processing ended: Sun Feb 16 22:32:24 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581910344801 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581910344801 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581910344801 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1581910344801 ""}

BIN
cpld/db/RAM2E.asm.rdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.atom.rvd Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.cmp 2.hdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.cmp 2.rdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.cmp 3.rdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.cmp.cdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.cmp.hdb Executable file
View File

Binary file not shown.

1
cpld/db/RAM2E.cmp.logdb Executable file
View File

@ -0,0 +1 @@
v1

BIN
cpld/db/RAM2E.cmp.rdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.cmp0.ddb Executable file
View File

Binary file not shown.

3
cpld/db/RAM2E.db_info Executable file
View File

@ -0,0 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Sun Feb 16 22:19:19 2020

BIN
cpld/db/RAM2E.eco.cdb Executable file
View File

Binary file not shown.

5
cpld/db/RAM2E.eda.qmsg Executable file
View File

@ -0,0 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581910347194 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581910347194 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 22:32:27 2020 " "Processing started: Sun Feb 16 22:32:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581910347194 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581910347194 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_eda --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581910347194 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "RAM2E.vo C:/Users/Zane/Documents/GitHub/RAM2E/cpld/simulation/modelsim/ simulation " "Generated file RAM2E.vo in folder \"C:/Users/Zane/Documents/GitHub/RAM2E/cpld/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1581910347315 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4505 " "Peak virtual memory: 4505 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581910347350 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 22:32:27 2020 " "Processing ended: Sun Feb 16 22:32:27 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581910347350 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581910347350 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581910347350 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581910347350 ""}

3
cpld/db/RAM2E.fit.qmsg Executable file
View File

@ -0,0 +1,3 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1581910343507 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1581910343509 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4697 " "Peak virtual memory: 4697 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581910343685 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 22:32:23 2020 " "Processing ended: Sun Feb 16 22:32:23 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581910343685 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581910343685 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581910343685 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1581910343685 ""}

123
cpld/db/RAM2E.hier_info Executable file
View File

@ -0,0 +1,123 @@
|RAM2E
C14M => MDR[0].CLK
C14M => MDR[1].CLK
C14M => MDR[2].CLK
C14M => MDR[3].CLK
C14M => MDR[4].CLK
C14M => MDR[5].CLK
C14M => MDR[6].CLK
C14M => MDR[7].CLK
C14M => BA[0].CLK
C14M => BA[1].CLK
C14M => BA[2].CLK
C14M => BA[3].CLK
C14M => BA[4].CLK
C14M => BA[5].CLK
C14M => C073SEL~reg0.CLK
C14M => VDR[0].CLK
C14M => VDR[1].CLK
C14M => VDR[2].CLK
C14M => VDR[3].CLK
C14M => VDR[4].CLK
C14M => VDR[5].CLK
C14M => VDR[6].CLK
C14M => VDR[7].CLK
C14M => MDBEN.CLK
C14M => nCAS~reg0.CLK
C14M => RA[8]~reg0.CLK
C14M => RA[9]~reg0.CLK
C14M => RA[10]~reg0.CLK
C14M => RA[11]~reg0.CLK
C14M => nRAS~reg0.CLK
C14M => S[0].CLK
C14M => S[1].CLK
C14M => S[2].CLK
C14M => S[3].CLK
C14M => PHI0seen.CLK
C14M => PHI1reg.CLK
C14M => Ref[0].CLK
C14M => Ref[1].CLK
C14M => Ref[2].CLK
C14M => Ref[3].CLK
C14M_2 => ~NO_FANOUT~
C7M => ~NO_FANOUT~
Q3 => ~NO_FANOUT~
PHI0 => ~NO_FANOUT~
PHI1 => VDOE.IN0
PHI1 => nRAS.IN1
PHI1 => PHI1reg.DATAIN
PHI1 => PHI0seen.OUTPUTSELECT
nPRAS => ~NO_FANOUT~
nPCAS => ~NO_FANOUT~
nWE => comb.IN0
nWE => comb.IN0
nWE80 => nRWE.DATAIN
nEN80 => DelayOut.IN0
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRWE <= nWE80.DB_MAX_OUTPUT_PORT_TYPE
VD[0] <> VD[0]
VD[1] <> VD[1]
VD[2] <> VD[2]
VD[3] <> VD[3]
VD[4] <> VD[4]
VD[5] <> VD[5]
VD[6] <> VD[6]
VD[7] <> VD[7]
MD[0] <> MD[0]
MD[1] <> MD[1]
MD[2] <> MD[2]
MD[3] <> MD[3]
MD[4] <> MD[4]
MD[5] <> MD[5]
MD[6] <> MD[6]
MD[7] <> MD[7]
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
RD[3] <> RD[3]
RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
nC07X => C073SEL.IN0
MA[0] => Equal17.IN7
MA[0] => Equal18.IN7
MA[0] => Equal19.IN7
MA[0] => Equal20.IN7
MA[1] => Equal17.IN6
MA[1] => Equal18.IN6
MA[1] => Equal19.IN6
MA[1] => Equal20.IN6
MA[2] => Equal17.IN5
MA[2] => Equal18.IN5
MA[2] => Equal19.IN5
MA[2] => Equal20.IN5
MA[3] => Equal17.IN4
MA[3] => Equal18.IN4
MA[3] => Equal19.IN4
MA[3] => Equal20.IN4
MA[4] => ~NO_FANOUT~
MA[5] => ~NO_FANOUT~
MA[6] => ~NO_FANOUT~
MA[7] => ~NO_FANOUT~
RA[8] <= RA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[9] <= RA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[10] <= RA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[11] <= RA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q3_2 => ~NO_FANOUT~
C3M58 => ~NO_FANOUT~
AN3 => ~NO_FANOUT~
nCASEN => ~NO_FANOUT~
C073SEL <= C073SEL~reg0.DB_MAX_OUTPUT_PORT_TYPE
DelayIn[0] => ~NO_FANOUT~
DelayIn[1] => DelayOut[2].DATAIN
DelayIn[2] => comb.IN1
DelayIn[2] => RDOE.IN1
DelayIn[3] => ~NO_FANOUT~
DelayOut[0] <= <GND>
DelayOut[1] <= DelayOut.DB_MAX_OUTPUT_PORT_TYPE
DelayOut[2] <= DelayIn[1].DB_MAX_OUTPUT_PORT_TYPE
DelayOut[3] <= <GND>

BIN
cpld/db/RAM2E.hif Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.ipinfo Executable file
View File

Binary file not shown.

18
cpld/db/RAM2E.lpc.html Executable file
View File

@ -0,0 +1,18 @@
<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

BIN
cpld/db/RAM2E.lpc.rdb Executable file
View File

Binary file not shown.

5
cpld/db/RAM2E.lpc.txt Executable file
View File

@ -0,0 +1,5 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

BIN
cpld/db/RAM2E.map 2.hdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.map 2.rdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.map.cdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.map.hdb Executable file
View File

Binary file not shown.

1
cpld/db/RAM2E.map.logdb Executable file
View File

@ -0,0 +1 @@
v1

21
cpld/db/RAM2E.map.qmsg Executable file
View File

File diff suppressed because one or more lines are too long

BIN
cpld/db/RAM2E.map.rdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.pplq.rdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.pre_map.hdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.pti_db_list.ddb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.root_partition.map.reg_db.cdb Executable file
View File

Binary file not shown.

4
cpld/db/RAM2E.rpp.qmsg Executable file
View File

@ -0,0 +1,4 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1564962135442 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1564962135442 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 04 19:42:15 2019 " "Processing started: Sun Aug 04 19:42:15 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1564962135442 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1564962135442 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp RAM2E -c RAM2E --netlist_type=atom " "Command: quartus_rpp RAM2E -c RAM2E --netlist_type=atom" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1564962135442 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "201 " "Peak virtual memory: 201 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1564962135927 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 04 19:42:15 2019 " "Processing ended: Sun Aug 04 19:42:15 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1564962135927 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1564962135927 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1564962135927 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1564962135927 ""}

BIN
cpld/db/RAM2E.rtlv.hdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.rtlv_sg.cdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.rtlv_sg_swap.cdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.sgate.rvd Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.sgate_sm.rvd Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.sgdiff.cdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.sgdiff.hdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.sld_design_entry.sci Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.sld_design_entry_dsc.sci Executable file
View File

Binary file not shown.

1
cpld/db/RAM2E.smart_action.txt Executable file
View File

@ -0,0 +1 @@
DONE

BIN
cpld/db/RAM2E.sta 2.rdb Normal file
View File

Binary file not shown.

22
cpld/db/RAM2E.sta.qmsg Executable file
View File

@ -0,0 +1,22 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581910345759 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581910345759 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 22:32:25 2020 " "Processing started: Sun Feb 16 22:32:25 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581910345759 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581910345759 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581910345759 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1581910345819 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581910346121 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1581910346129 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1581910346130 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1581910346147 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2E.sdc " "Synopsys Design Constraints File file not found: 'RAM2E.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1581910346165 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1581910346166 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C14M C14M " "create_clock -period 1.000 -name C14M C14M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346166 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346166 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1581910346167 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1581910346176 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -46.000 " "Worst-case setup slack is -46.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -46.000 -954.000 C14M " " -46.000 -954.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346182 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581910346182 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346189 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346189 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C14M " " 5.000 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346189 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581910346189 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581910346196 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581910346202 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346210 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346210 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -351.000 C14M " " -4.500 -351.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581910346210 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581910346210 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1581910346248 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581910346269 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581910346269 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4525 " "Peak virtual memory: 4525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581910346337 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 22:32:26 2020 " "Processing ended: Sun Feb 16 22:32:26 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581910346337 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581910346337 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581910346337 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581910346337 ""}

BIN
cpld/db/RAM2E.sta.rdb Executable file
View File

Binary file not shown.

BIN
cpld/db/RAM2E.sta_cmp.15_slow.tdb Executable file
View File

Binary file not shown.

0
cpld/db/RAM2E.syn_hier_info Executable file
View File

BIN
cpld/db/RAM2E.tis_db_list.ddb Executable file
View File

Binary file not shown.

7
cpld/db/RAM2E.tmw_info Normal file
View File

@ -0,0 +1,7 @@
start_full_compilation:s:00:00:06
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:01-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation
start_eda_netlist_writer:s:00:00:01-start_full_compilation

0
cpld/db/logic_util_heursitic.dat Executable file
View File

64
cpld/db/prev_cmp_RAM2E.qmsg Executable file
View File

File diff suppressed because one or more lines are too long

11
cpld/incremental_db/README Executable file
View File

@ -0,0 +1,11 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
cpld/incremental_db/compiled_partitions/RAM2E.db_info Executable file
View File

@ -0,0 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Sun Aug 04 18:02:39 2019

BIN
cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt Executable file
View File

Binary file not shown.

111
cpld/output_files/RAM2E.asm.rpt Executable file
View File

@ -0,0 +1,111 @@
Assembler report for RAM2E
Sun Feb 16 22:32:24 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Feb 16 22:32:24 2020 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX7000S ;
; Device ; EPM7128SLC84-15 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Security bit ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+------------------------------------------------------------------+
; Assembler Generated Files ;
+------------------------------------------------------------------+
; File Name ;
+------------------------------------------------------------------+
; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof ;
+------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof ;
+----------------+---------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------------------------+
; Device ; EPM7128SLC84-15 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x0019C601 ;
+----------------+---------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Feb 16 22:32:24 2020
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4522 megabytes
Info: Processing ended: Sun Feb 16 22:32:24 2020
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

13
cpld/output_files/RAM2E.cdf Normal file
View File

@ -0,0 +1,13 @@
/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM7128SL84) Path("C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/") File("RAM2E.pof") MfrSpec(OpMask(3));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1
cpld/output_files/RAM2E.done Executable file
View File

@ -0,0 +1 @@
Sun Feb 16 22:32:27 2020

92
cpld/output_files/RAM2E.eda.rpt Executable file
View File

@ -0,0 +1,92 @@
EDA Netlist Writer report for RAM2E
Sun Feb 16 22:32:27 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sun Feb 16 22:32:27 2020 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX7000S ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only ; On ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+---------------------------+
+------------------------------------------------------------------------+
; Simulation Generated Files ;
+------------------------------------------------------------------------+
; Generated Files ;
+------------------------------------------------------------------------+
; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/simulation/modelsim/RAM2E.vo ;
+------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Feb 16 22:32:27 2020
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
Info (204019): Generated file RAM2E.vo in folder "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4505 megabytes
Info: Processing ended: Sun Feb 16 22:32:27 2020
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

627
cpld/output_files/RAM2E.fit.rpt Executable file
View File

@ -0,0 +1,627 @@
Fitter report for RAM2E
Sun Feb 16 22:32:23 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. Bidir Pins
10. All Package Pins
11. I/O Standard
12. Dedicated Inputs I/O
13. Output Pin Default Load For Reported TCO
14. Fitter Resource Utilization by Entity
15. Control Signals
16. Global & Other Fast Signals
17. Non-Global High Fan-Out Signals
18. Other Routing Usage Summary
19. LAB External Interconnect
20. LAB Macrocells
21. Shareable Expander
22. Logic Cell Interconnection
23. Fitter Device Options
24. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Sun Feb 16 22:32:23 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX7000S ;
; Device ; EPM7128SLC84-15 ;
; Timing Models ; Final ;
; Total macrocells ; 55 / 128 ( 43 % ) ;
; Total pins ; 68 / 68 ( 100 % ) ;
+---------------------------+-------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+----------------------------------------------------------------------------+-----------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+-----------------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Optimize Timing for ECOs ; On ; Off ;
; Regenerate full fit report during ECO compiles ; On ; Off ;
; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;
; Slow Slew Rate ; On ; Off ;
; Fitter Effort ; Standard Fit ; Auto Fit ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Optimize Multi-Corner Timing ; Off ; Off ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+----------------------------------------------------------------------------+-----------------------+---------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pin.
+--------------------------------------------------+
; Fitter Resource Usage Summary ;
+------------------------------+-------------------+
; Resource ; Usage ;
+------------------------------+-------------------+
; Logic cells ; 55 / 128 ( 43 % ) ;
; Registers ; 39 / 128 ( 30 % ) ;
; Number of pterms used ; 111 ;
; I/O pins ; 68 / 68 ( 100 % ) ;
; -- Clock pins ; 2 / 2 ( 100 % ) ;
; -- Dedicated input pins ; 2 / 2 ( 100 % ) ;
; ; ;
; Global signals ; 1 ;
; Shareable expanders ; 4 / 128 ( 3 % ) ;
; Parallel expanders ; 0 / 120 ( 0 % ) ;
; Cells using turbo bit ; 1 / 128 ( < 1 % ) ;
; Maximum fan-out ; 39 ;
; Highest non-global fan-out ; 39 ;
; Total fan-out ; 350 ;
; Average fan-out ; 2.76 ;
+------------------------------+-------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ;
+------------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; AN3 ; 4 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; C14M ; 83 ; -- ; -- ; 39 ; 0 ; yes ; no ; TTL ; User ;
; C14M_2 ; 84 ; -- ; -- ; 0 ; 0 ; no ; no ; TTL ; User ;
; C3M58 ; 10 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; C7M ; 9 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; DelayIn[0] ; 11 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; DelayIn[1] ; 15 ; -- ; 2 ; 1 ; 0 ; no ; no ; TTL ; User ;
; DelayIn[2] ; 17 ; -- ; 2 ; 2 ; 0 ; no ; no ; TTL ; User ;
; DelayIn[3] ; 20 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ;
; MA[0] ; 45 ; -- ; 5 ; 1 ; 0 ; no ; no ; TTL ; User ;
; MA[1] ; 46 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
; MA[2] ; 48 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
; MA[3] ; 49 ; -- ; 5 ; 1 ; 0 ; no ; no ; TTL ; User ;
; MA[4] ; 50 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
; MA[5] ; 51 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
; MA[6] ; 52 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
; MA[7] ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
; PHI0 ; 75 ; -- ; 8 ; 0 ; 0 ; no ; no ; TTL ; User ;
; PHI1 ; 79 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ;
; Q3 ; 2 ; -- ; -- ; 0 ; 0 ; no ; no ; TTL ; User ;
; Q3_2 ; 1 ; -- ; -- ; 0 ; 0 ; no ; no ; TTL ; User ;
; nC07X ; 6 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
; nCASEN ; 77 ; -- ; 8 ; 0 ; 0 ; no ; no ; TTL ; User ;
; nEN80 ; 76 ; -- ; 8 ; 1 ; 0 ; no ; no ; TTL ; User ;
; nPCAS ; 81 ; -- ; 8 ; 0 ; 0 ; no ; no ; TTL ; User ;
; nPRAS ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
; nWE ; 5 ; -- ; 1 ; 3 ; 0 ; no ; no ; TTL ; User ;
; nWE80 ; 80 ; -- ; 8 ; 1 ; 0 ; no ; no ; TTL ; User ;
+------------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+-------------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
; C073SEL ; 22 ; -- ; 2 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; DelayOut[0] ; 12 ; -- ; 1 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; DelayOut[1] ; 16 ; -- ; 2 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; DelayOut[2] ; 18 ; -- ; 2 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; DelayOut[3] ; 21 ; -- ; 2 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; RA[10] ; 24 ; -- ; 3 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; RA[11] ; 25 ; -- ; 3 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; RA[8] ; 41 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; RA[9] ; 40 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; nCAS ; 27 ; -- ; 3 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; nRAS ; 39 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
; nRWE ; 37 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ;
+-------------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins ;
+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Slow Slew Rate ; Open Drain ; I/O Standard ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+
; MD[0] ; 57 ; -- ; 6 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; MDOE~1 ; - ;
; MD[1] ; 61 ; -- ; 6 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; MDOE~1 ; - ;
; MD[2] ; 68 ; -- ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; MDOE~1 ; - ;
; MD[3] ; 73 ; -- ; 8 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; MDOE~1 ; - ;
; MD[4] ; 69 ; -- ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; MDOE~1 ; - ;
; MD[5] ; 65 ; -- ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; MDOE~1 ; - ;
; MD[6] ; 58 ; -- ; 6 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; MDOE~1 ; - ;
; MD[7] ; 55 ; -- ; 6 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; MDOE~1 ; - ;
; RD[0] ; 33 ; -- ; 4 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; RD[1] ; 34 ; -- ; 4 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; RD[2] ; 35 ; -- ; 4 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; RD[3] ; 36 ; -- ; 4 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; RD[4] ; 28 ; -- ; 3 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; RD[5] ; 29 ; -- ; 3 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; RD[6] ; 30 ; -- ; 3 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; RD[7] ; 31 ; -- ; 3 ; 2 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
; VD[0] ; 56 ; -- ; 6 ; 0 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; PHI1 (inverted) ; - ;
; VD[1] ; 63 ; -- ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; PHI1 (inverted) ; - ;
; VD[2] ; 67 ; -- ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; PHI1 (inverted) ; - ;
; VD[3] ; 74 ; -- ; 8 ; 0 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; PHI1 (inverted) ; - ;
; VD[4] ; 70 ; -- ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; PHI1 (inverted) ; - ;
; VD[5] ; 64 ; -- ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; PHI1 (inverted) ; - ;
; VD[6] ; 60 ; -- ; 6 ; 0 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; PHI1 (inverted) ; - ;
; VD[7] ; 54 ; -- ; 6 ; 0 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; PHI1 (inverted) ; - ;
+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+
+-------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; User Assignment ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
; 1 ; 0 ; -- ; Q3_2 ; input ; TTL ; ; Y ;
; 2 ; 1 ; -- ; Q3 ; input ; TTL ; ; Y ;
; 3 ; 2 ; -- ; VCCINT ; power ; ; 5.0V ; ;
; 4 ; 3 ; -- ; AN3 ; input ; TTL ; ; Y ;
; 5 ; 4 ; -- ; nWE ; input ; TTL ; ; Y ;
; 6 ; 5 ; -- ; nC07X ; input ; TTL ; ; Y ;
; 7 ; 6 ; -- ; GND ; gnd ; ; ; ;
; 8 ; 7 ; -- ; nPRAS ; input ; TTL ; ; Y ;
; 9 ; 8 ; -- ; C7M ; input ; TTL ; ; Y ;
; 10 ; 9 ; -- ; C3M58 ; input ; TTL ; ; Y ;
; 11 ; 10 ; -- ; DelayIn[0] ; input ; TTL ; ; Y ;
; 12 ; 11 ; -- ; DelayOut[0] ; output ; TTL ; ; Y ;
; 13 ; 12 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 14 ; 13 ; -- ; TDI ; input ; TTL ; ; N ;
; 15 ; 14 ; -- ; DelayIn[1] ; input ; TTL ; ; Y ;
; 16 ; 15 ; -- ; DelayOut[1] ; output ; TTL ; ; Y ;
; 17 ; 16 ; -- ; DelayIn[2] ; input ; TTL ; ; Y ;
; 18 ; 17 ; -- ; DelayOut[2] ; output ; TTL ; ; Y ;
; 19 ; 18 ; -- ; GND ; gnd ; ; ; ;
; 20 ; 19 ; -- ; DelayIn[3] ; input ; TTL ; ; Y ;
; 21 ; 20 ; -- ; DelayOut[3] ; output ; TTL ; ; Y ;
; 22 ; 21 ; -- ; C073SEL ; output ; TTL ; ; Y ;
; 23 ; 22 ; -- ; TMS ; input ; TTL ; ; N ;
; 24 ; 23 ; -- ; RA[10] ; output ; TTL ; ; Y ;
; 25 ; 24 ; -- ; RA[11] ; output ; TTL ; ; Y ;
; 26 ; 25 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 27 ; 26 ; -- ; nCAS ; output ; TTL ; ; Y ;
; 28 ; 27 ; -- ; RD[4] ; bidir ; TTL ; ; Y ;
; 29 ; 28 ; -- ; RD[5] ; bidir ; TTL ; ; Y ;
; 30 ; 29 ; -- ; RD[6] ; bidir ; TTL ; ; Y ;
; 31 ; 30 ; -- ; RD[7] ; bidir ; TTL ; ; Y ;
; 32 ; 31 ; -- ; GND ; gnd ; ; ; ;
; 33 ; 32 ; -- ; RD[0] ; bidir ; TTL ; ; Y ;
; 34 ; 33 ; -- ; RD[1] ; bidir ; TTL ; ; Y ;
; 35 ; 34 ; -- ; RD[2] ; bidir ; TTL ; ; Y ;
; 36 ; 35 ; -- ; RD[3] ; bidir ; TTL ; ; Y ;
; 37 ; 36 ; -- ; nRWE ; output ; TTL ; ; Y ;
; 38 ; 37 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 39 ; 38 ; -- ; nRAS ; output ; TTL ; ; Y ;
; 40 ; 39 ; -- ; RA[9] ; output ; TTL ; ; Y ;
; 41 ; 40 ; -- ; RA[8] ; output ; TTL ; ; Y ;
; 42 ; 41 ; -- ; GND ; gnd ; ; ; ;
; 43 ; 42 ; -- ; VCCINT ; power ; ; 5.0V ; ;
; 44 ; 43 ; -- ; MA[7] ; input ; TTL ; ; Y ;
; 45 ; 44 ; -- ; MA[0] ; input ; TTL ; ; Y ;
; 46 ; 45 ; -- ; MA[1] ; input ; TTL ; ; Y ;
; 47 ; 46 ; -- ; GND ; gnd ; ; ; ;
; 48 ; 47 ; -- ; MA[2] ; input ; TTL ; ; Y ;
; 49 ; 48 ; -- ; MA[3] ; input ; TTL ; ; Y ;
; 50 ; 49 ; -- ; MA[4] ; input ; TTL ; ; Y ;
; 51 ; 50 ; -- ; MA[5] ; input ; TTL ; ; Y ;
; 52 ; 51 ; -- ; MA[6] ; input ; TTL ; ; Y ;
; 53 ; 52 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 54 ; 53 ; -- ; VD[7] ; bidir ; TTL ; ; Y ;
; 55 ; 54 ; -- ; MD[7] ; bidir ; TTL ; ; Y ;
; 56 ; 55 ; -- ; VD[0] ; bidir ; TTL ; ; Y ;
; 57 ; 56 ; -- ; MD[0] ; bidir ; TTL ; ; Y ;
; 58 ; 57 ; -- ; MD[6] ; bidir ; TTL ; ; Y ;
; 59 ; 58 ; -- ; GND ; gnd ; ; ; ;
; 60 ; 59 ; -- ; VD[6] ; bidir ; TTL ; ; Y ;
; 61 ; 60 ; -- ; MD[1] ; bidir ; TTL ; ; Y ;
; 62 ; 61 ; -- ; TCK ; input ; TTL ; ; N ;
; 63 ; 62 ; -- ; VD[1] ; bidir ; TTL ; ; Y ;
; 64 ; 63 ; -- ; VD[5] ; bidir ; TTL ; ; Y ;
; 65 ; 64 ; -- ; MD[5] ; bidir ; TTL ; ; Y ;
; 66 ; 65 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 67 ; 66 ; -- ; VD[2] ; bidir ; TTL ; ; Y ;
; 68 ; 67 ; -- ; MD[2] ; bidir ; TTL ; ; Y ;
; 69 ; 68 ; -- ; MD[4] ; bidir ; TTL ; ; Y ;
; 70 ; 69 ; -- ; VD[4] ; bidir ; TTL ; ; Y ;
; 71 ; 70 ; -- ; TDO ; output ; TTL ; ; N ;
; 72 ; 71 ; -- ; GND ; gnd ; ; ; ;
; 73 ; 72 ; -- ; MD[3] ; bidir ; TTL ; ; Y ;
; 74 ; 73 ; -- ; VD[3] ; bidir ; TTL ; ; Y ;
; 75 ; 74 ; -- ; PHI0 ; input ; TTL ; ; Y ;
; 76 ; 75 ; -- ; nEN80 ; input ; TTL ; ; Y ;
; 77 ; 76 ; -- ; nCASEN ; input ; TTL ; ; Y ;
; 78 ; 77 ; -- ; VCCIO ; power ; ; 5.0V ; ;
; 79 ; 78 ; -- ; PHI1 ; input ; TTL ; ; Y ;
; 80 ; 79 ; -- ; nWE80 ; input ; TTL ; ; Y ;
; 81 ; 80 ; -- ; nPCAS ; input ; TTL ; ; Y ;
; 82 ; 81 ; -- ; GND ; gnd ; ; ; ;
; 83 ; 82 ; -- ; C14M ; input ; TTL ; ; Y ;
; 84 ; 83 ; -- ; C14M_2 ; input ; TTL ; ; Y ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+--------------------------------------------------------------------------------------------------+
; I/O Standard ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
; I/O Standard ; Input Vref ; Dedicated Input Pins ; Pins in I/O Bank1 ; Pins in I/O Bank2 ; Total ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
; TTL ; - ; 4 ; 0 ; 0 ; 4 ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
+----------------------------------------------------------------------+
; Dedicated Inputs I/O ;
+--------+-------+-------+-------+--------------+------------+---------+
; Name ; Pin # ; Type ; VCCIO ; I/O Standard ; Input Vref ; Current ;
+--------+-------+-------+-------+--------------+------------+---------+
; C14M ; 83 ; Input ; -- ; TTL ; - ; 0 mA ;
; C14M_2 ; 84 ; Input ; -- ; TTL ; - ; 0 mA ;
; Q3 ; 2 ; Input ; -- ; TTL ; - ; 0 mA ;
; Q3_2 ; 1 ; Input ; -- ; TTL ; - ; 0 mA ;
+--------+-------+-------+-------+--------------+------------+---------+
+-----------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+--------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+--------------+-------+------------------------+
; 3.3-V LVTTL ; 10 pF ; Not Available ;
; 3.3-V LVCMOS ; 10 pF ; Not Available ;
; TTL ; 10 pF ; Not Available ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+----------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+------------------------------+--------------+
; |RAM2E ; 55 ; 68 ; |RAM2E ; work ;
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |RAM2E|lpm_counter:Ref_rtl_0 ; work ;
+----------------------------+------------+------+------------------------------+--------------+
+-----------------------------------------------------------------------------------------------------+
; Control Signals ;
+--------------+----------+---------+--------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+--------------+----------+---------+--------------+--------+----------------------+------------------+
; C073SEL~reg0 ; LC17 ; 8 ; Clock enable ; no ; -- ; -- ;
; C14M ; PIN_83 ; 39 ; Clock ; yes ; On ; -- ;
; PHI1 ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ;
; S[0] ; LC52 ; 36 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC58 ; 38 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC50 ; 38 ; Clock enable ; no ; -- ; -- ;
; S[3] ; LC60 ; 39 ; Clock enable ; no ; -- ; -- ;
+--------------+----------+---------+--------------+--------+----------------------+------------------+
+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; C14M ; PIN_83 ; 39 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
+-----------------------------------------+
; Non-Global High Fan-Out Signals ;
+-------------------------------+---------+
; Name ; Fan-Out ;
+-------------------------------+---------+
; S[3] ; 39 ;
; S[1] ; 38 ;
; S[2] ; 38 ;
; S[0] ; 36 ;
; PHI1 ; 15 ;
; C073SEL~reg0 ; 8 ;
; RDOE~1 ; 8 ;
; MDOE~1 ; 8 ;
; lpm_counter:Ref_rtl_0|dffs[3] ; 6 ;
; lpm_counter:Ref_rtl_0|dffs[2] ; 6 ;
; lpm_counter:Ref_rtl_0|dffs[0] ; 6 ;
; lpm_counter:Ref_rtl_0|dffs[1] ; 5 ;
; PHI1reg ; 5 ;
; PHI0seen ; 5 ;
; nWE ; 3 ;
; RD[7]~7 ; 2 ;
; RD[6]~6 ; 2 ;
; RD[5]~5 ; 2 ;
; RD[4]~4 ; 2 ;
; RD[3]~3 ; 2 ;
; RD[2]~2 ; 2 ;
; RD[1]~1 ; 2 ;
; RD[0]~0 ; 2 ;
; MD[5]~5 ; 2 ;
; MD[4]~4 ; 2 ;
; MD[3]~3 ; 2 ;
; MD[2]~2 ; 2 ;
; MD[1]~1 ; 2 ;
; MD[0]~0 ; 2 ;
; DelayIn[2] ; 2 ;
; BA[4] ; 2 ;
; MD[7]~7 ; 1 ;
; MD[6]~6 ; 1 ;
; DelayIn[1] ; 1 ;
; MA[3] ; 1 ;
; MA[0] ; 1 ;
; nC07X ; 1 ;
; nEN80 ; 1 ;
; nWE80 ; 1 ;
; ~GND~2 ; 1 ;
; ~GND~1 ; 1 ;
; ~GND~0 ; 1 ;
; nRAS~reg0 ; 1 ;
; nRAS~8 ; 1 ;
; nCAS~reg0 ; 1 ;
; RA[9]~reg0 ; 1 ;
; RA[8]~reg0 ; 1 ;
; RA[10]~reg0 ; 1 ;
; BA[0] ; 1 ;
; BA[1] ; 1 ;
; BA[2] ; 1 ;
; BA[3] ; 1 ;
; BA[5] ; 1 ;
; C073SEL~9 ; 1 ;
; C073SEL~8 ; 1 ;
; C073SEL~7 ; 1 ;
; VDR[7] ; 1 ;
; VDR[6] ; 1 ;
; VDR[5] ; 1 ;
; VDR[4] ; 1 ;
; MDR[0] ; 1 ;
; MDR[1] ; 1 ;
; MDR[2] ; 1 ;
; MDR[3] ; 1 ;
; MDR[4] ; 1 ;
; MDR[5] ; 1 ;
; MDR[6] ; 1 ;
; MDR[7] ; 1 ;
; VDR[0] ; 1 ;
; VDR[1] ; 1 ;
; VDR[2] ; 1 ;
; VDR[3] ; 1 ;
; MDBEN ; 1 ;
; DelayIn[1]~1 ; 1 ;
; nEN80~1 ; 1 ;
; nWE80~1 ; 1 ;
; MD[7]~38 ; 1 ;
; MD[6]~36 ; 1 ;
; MD[5]~34 ; 1 ;
; MD[4]~32 ; 1 ;
; MD[3]~30 ; 1 ;
; MD[2]~28 ; 1 ;
; MD[1]~26 ; 1 ;
; MD[0]~24 ; 1 ;
+-------------------------------+---------+
+-------------------------------------------------+
; Other Routing Usage Summary ;
+-----------------------------+-------------------+
; Other Routing Resource Type ; Usage ;
+-----------------------------+-------------------+
; Output enables ; 3 / 6 ( 50 % ) ;
; PIA buffers ; 64 / 288 ( 22 % ) ;
; PIAs ; 72 / 288 ( 25 % ) ;
+-----------------------------+-------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 9.00) ; Number of LABs (Total = 6) ;
+----------------------------------------------+-----------------------------+
; 0 - 1 ; 2 ;
; 2 - 3 ; 0 ;
; 4 - 5 ; 1 ;
; 6 - 7 ; 0 ;
; 8 - 9 ; 2 ;
; 10 - 11 ; 0 ;
; 12 - 13 ; 1 ;
; 14 - 15 ; 1 ;
; 16 - 17 ; 0 ;
; 18 - 19 ; 0 ;
; 20 - 21 ; 0 ;
; 22 - 23 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 6.88) ; Number of LABs (Total = 7) ;
+----------------------------------------+-----------------------------+
; 0 ; 1 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 2 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.50) ; Number of LABs (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
+-------------------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC3 ; ; DelayOut[0] ;
; B ; LC32 ; MDBEN, nWE, DelayIn[2] ; MD[0], MD[1], MD[2], MD[3], MD[4], MD[5], MD[6], MD[7] ;
; B ; LC27 ; nEN80 ; DelayOut[1] ;
; B ; LC21 ; nWE, DelayIn[2] ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
; B ; LC19 ; ; DelayOut[3] ;
; B ; LC17 ; C14M, S[2], S[3], S[1], C073SEL~7, C073SEL~reg0, C073SEL~8, S[0], C073SEL~9 ; C073SEL~reg0, C073SEL, BA[5], BA[4], BA[3], BA[2], BA[1], BA[0] ;
; B ; LC24 ; DelayIn[1] ; DelayOut[2] ;
; C ; LC42 ; C14M, MD[4], C073SEL~reg0, S[0], S[1], S[2], S[3] ; RA[10]~reg0, RA[9]~reg0 ;
; C ; LC46 ; C14M, BA[4], S[1], S[2], S[3] ; RA[10] ;
; C ; LC43 ; C14M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[3], S[2], S[0], S[1] ; nCAS ;
; C ; LC45 ; ; RA[11] ;
; C ; LC38 ; MD[5] ; RD[5] ;
; C ; LC37 ; MD[6] ; RD[6] ;
; C ; LC35 ; MD[7] ; RD[7] ;
; C ; LC33 ; C14M, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[0], S[1], S[2], S[3] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], nCAS~reg0, nRAS~reg0 ;
; C ; LC40 ; MD[4] ; RD[4] ;
; C ; LC48 ; C14M, PHI1 ; S[2], S[3], S[1], S[0], nRAS~reg0 ;
; C ; LC47 ; C14M, PHI1 ; S[2], S[3], S[1], S[0], nRAS~reg0 ;
; C ; LC36 ; C14M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[1], S[2], S[3] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], nCAS~reg0, nRAS~reg0 ;
; C ; LC34 ; C14M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[0], S[1], S[2], S[3] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], nCAS~reg0, nRAS~reg0 ;
; C ; LC44 ; C14M, S[3], S[2], S[0], S[1] ; MDOE~1 ;
; C ; LC41 ; C14M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[1], S[2], S[3] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], nCAS~reg0, nRAS~reg0 ;
; C ; LC39 ; C14M, MD[5], C073SEL~reg0, S[0], S[1], S[2], S[3] ; RA[9]~reg0 ;
; D ; LC64 ; MD[0] ; RD[0] ;
; D ; LC61 ; MD[1] ; RD[1] ;
; D ; LC59 ; MD[2] ; RD[2] ;
; D ; LC57 ; MD[3] ; RD[3] ;
; D ; LC56 ; nWE80 ; nRWE ;
; D ; LC50 ; C14M, PHI0seen, PHI1reg, PHI1, S[0], S[3], S[2], S[1] ; S[2], S[3], MDBEN, VDR[3], VDR[2], VDR[1], VDR[0], MDR[7], MDR[6], MDR[5], MDR[4], MDR[3], MDR[2], MDR[1], MDR[0], VDR[4], VDR[5], S[1], VDR[6], VDR[7], S[0], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], C073SEL~7, C073SEL~reg0, lpm_counter:Ref_rtl_0|dffs[2], BA[5], BA[4], BA[3], BA[2], BA[1], BA[0], RA[10]~reg0, RA[8]~reg0, lpm_counter:Ref_rtl_0|dffs[3], RA[9]~reg0, nCAS~reg0, nRAS~reg0 ;
; D ; LC60 ; C14M, PHI0seen, PHI1reg, PHI1, S[2], S[3], S[0], S[1] ; S[2], S[3], MDBEN, VDR[3], VDR[2], VDR[1], VDR[0], MDR[7], MDR[6], MDR[5], MDR[4], MDR[3], MDR[2], MDR[1], MDR[0], VDR[4], VDR[5], S[1], VDR[6], VDR[7], S[0], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], C073SEL~7, C073SEL~reg0, lpm_counter:Ref_rtl_0|dffs[2], BA[5], BA[4], BA[3], BA[2], BA[1], BA[0], RA[10]~reg0, RA[8]~reg0, lpm_counter:Ref_rtl_0|dffs[3], RA[9]~reg0, nCAS~reg0, nRAS~8, nRAS~reg0 ;
; D ; LC58 ; C14M, PHI0seen, PHI1reg, PHI1, S[3], S[0], S[1], S[2] ; S[2], S[3], MDBEN, VDR[3], VDR[2], VDR[1], VDR[0], MDR[7], MDR[6], MDR[5], MDR[4], MDR[3], MDR[2], MDR[1], MDR[0], VDR[4], VDR[5], S[1], VDR[6], VDR[7], S[0], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], C073SEL~7, C073SEL~reg0, lpm_counter:Ref_rtl_0|dffs[2], BA[5], BA[4], BA[3], BA[2], BA[1], BA[0], RA[10]~reg0, RA[8]~reg0, lpm_counter:Ref_rtl_0|dffs[3], RA[9]~reg0, nCAS~reg0, nRAS~reg0 ;
; D ; LC62 ; C14M, MD[2], C073SEL~reg0, S[0], S[1], S[2], S[3] ; RA[8]~reg0 ;
; D ; LC54 ; C14M, MD[1], C073SEL~reg0, S[0], S[1], S[2], S[3] ; RA[9]~reg0 ;
; D ; LC55 ; C14M, MD[0], C073SEL~reg0, S[0], S[1], S[2], S[3] ; RA[8]~reg0 ;
; D ; LC49 ; C14M, BA[2], S[1], S[2], S[3], BA[0] ; RA[8] ;
; D ; LC51 ; C14M, BA[5], S[1], BA[4], S[2], S[3], BA[3], BA[1] ; RA[9] ;
; D ; LC53 ; C14M, PHI0seen, PHI1reg, PHI1, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[1], S[2], S[3], nRAS~8 ; nRAS ;
; D ; LC52 ; C14M, PHI0seen, PHI1reg, PHI1, S[1], S[2], S[3], S[0] ; S[2], S[3], MDBEN, VDR[3], VDR[2], VDR[1], VDR[0], MDR[7], MDR[6], MDR[5], MDR[4], MDR[3], MDR[2], MDR[1], MDR[0], VDR[4], VDR[5], S[1], VDR[6], VDR[7], S[0], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], C073SEL~7, C073SEL~reg0, lpm_counter:Ref_rtl_0|dffs[2], BA[5], BA[4], BA[3], BA[2], BA[1], BA[0], lpm_counter:Ref_rtl_0|dffs[3], nCAS~reg0, nRAS~8, nRAS~reg0 ;
; D ; LC63 ; C14M, MD[3], C073SEL~reg0, S[0], S[1], S[2], S[3] ; RA[9]~reg0 ;
; F ; LC86 ; C14M, RD[0], S[0], S[1], S[2], S[3] ; VD[0] ;
; F ; LC85 ; C14M, RD[7], S[0], S[1], S[2], S[3] ; MD[7] ;
; F ; LC91 ; C14M, RD[6], S[0], S[1], S[2], S[3] ; MD[6] ;
; F ; LC94 ; C14M, RD[1], S[0], S[1], S[2], S[3] ; MD[1] ;
; F ; LC88 ; C14M, RD[0], S[0], S[1], S[2], S[3] ; MD[0] ;
; F ; LC93 ; C14M, RD[6], S[0], S[1], S[2], S[3] ; VD[6] ;
; F ; LC83 ; C14M, RD[7], S[0], S[1], S[2], S[3] ; VD[7] ;
; G ; LC104 ; C14M, RD[2], S[0], S[1], S[2], S[3] ; VD[2] ;
; G ; LC97 ; C14M, RD[1], S[0], S[1], S[2], S[3] ; VD[1] ;
; G ; LC109 ; C14M, RD[4], S[0], S[1], S[2], S[3] ; VD[4] ;
; G ; LC99 ; C14M, RD[5], S[0], S[1], S[2], S[3] ; VD[5] ;
; G ; LC107 ; C14M, RD[4], S[0], S[1], S[2], S[3] ; MD[4] ;
; G ; LC105 ; C14M, RD[2], S[0], S[1], S[2], S[3] ; MD[2] ;
; G ; LC101 ; C14M, RD[5], S[0], S[1], S[2], S[3] ; MD[5] ;
; H ; LC117 ; C14M, RD[3], S[0], S[1], S[2], S[3] ; VD[3] ;
; H ; LC115 ; C14M, RD[3], S[0], S[1], S[2], S[3] ; MD[3] ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+----------------+
; Option ; Setting ;
+----------------------------------------------+----------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+----------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM7128SLC84-15 for design "RAM2E"
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4697 megabytes
Info: Processing ended: Sun Feb 16 22:32:23 2020
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:01

9
cpld/output_files/RAM2E.fit.summary Executable file
View File

@ -0,0 +1,9 @@
Fitter Status : Successful - Sun Feb 16 22:32:23 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Total macrocells : 55 / 128 ( 43 % )
Total pins : 68 / 68 ( 100 % )

133
cpld/output_files/RAM2E.flow.rpt Executable file
View File

@ -0,0 +1,133 @@
Flow report for RAM2E
Sun Feb 16 22:32:27 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Sun Feb 16 22:32:27 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX7000S ;
; Device ; EPM7128SLC84-15 ;
; Timing Models ; Final ;
; Total macrocells ; 55 / 128 ( 43 % ) ;
; Total pins ; 68 / 68 ( 100 % ) ;
+---------------------------+-------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/16/2020 22:32:22 ;
; Main task ; Compilation ;
; Revision Name ; RAM2E ;
+-------------------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+--------------------------------------------+---------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+--------------------------------------------+---------------------------------+---------------+-------------+----------------+
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.158191034233144 ; -- ; -- ; -- ;
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; On ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ;
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
; POWER_USE_PVA ; Off ; On ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ;
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
+--------------------------------------------+---------------------------------+---------------+-------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4586 MB ; 00:00:01 ;
; Fitter ; 00:00:00 ; 1.0 ; 4697 MB ; 00:00:00 ;
; Assembler ; 00:00:00 ; 1.0 ; 4522 MB ; 00:00:00 ;
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4525 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4493 MB ; 00:00:00 ;
; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E
quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
quartus_sta RAM2E -c RAM2E
quartus_eda --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E

8
cpld/output_files/RAM2E.jdi Executable file
View File

@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="44a3ae1b1e8c6325ff19"/>
</project>
<file_info>
<file device="EPM7128SLC84-15" path="RAM2E.sof" usercode="0x00000000"/>
</file_info>
</sld_project_info>

278
cpld/output_files/RAM2E.map.rpt Executable file
View File

@ -0,0 +1,278 @@
Analysis & Synthesis report for RAM2E
Sun Feb 16 22:32:22 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis
9. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
10. Analysis & Synthesis Messages
11. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Feb 16 22:32:22 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX7000S ;
; Total macrocells ; 55 ;
; Total pins ; 64 ;
+-----------------------------+-------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; RAM2E ; RAM2E ;
; Family name ; MAX7000S ; Cyclone IV GX ;
; Ignore LCELL Buffers ; Off ; Auto ;
; Auto Logic Cell Insertion ; Off ; On ;
; Auto Parallel Expanders ; Off ; On ;
; Analysis & Synthesis Message Level ; High ; Medium ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Parallel Expander Chain Length ; 4 ; 4 ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell ; 100 ; 100 ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+-----------------+---------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
; RAM2E.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v ; ;
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
; cmpconst.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cmpconst.inc ; ;
; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc ; ;
; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc ; ;
; dffeea.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffeea.inc ; ;
; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ;
; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 55 ;
; Total registers ; 39 ;
; I/O pins ; 64 ;
; Shareable expanders ; 4 ;
; Maximum fan-out node ; S[3] ;
; Maximum fan-out ; 39 ;
; Total fan-out ; 350 ;
; Average fan-out ; 2.85 ;
+----------------------+----------------------+
+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+------------------------------+--------------+
; |RAM2E ; 55 ; 64 ; |RAM2E ; work ;
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |RAM2E|lpm_counter:Ref_rtl_0 ; work ;
+----------------------------+------------+------+------------------------------+--------------+
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; RA[11]~reg0 ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 ;
+------------------------+-------------------+---------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+---------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Feb 16 22:32:21 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file ram2e.v
Info (12023): Found entity 1: RAM2E
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at RAM2E.v(60): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(65): truncated value with size 32 to match size of target (4)
Warning (14130): Reduced register "RA[11]~reg0" with stuck data_in port to stuck value GND
Info (19000): Inferred 1 megafunctions from design logic
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
Info (12130): Elaborated megafunction instantiation "lpm_counter:Ref_rtl_0"
Info (12133): Instantiated megafunction "lpm_counter:Ref_rtl_0" with the following parameter:
Info (12134): Parameter "LPM_WIDTH" = "4"
Info (12134): Parameter "LPM_DIRECTION" = "UP"
Info (12134): Parameter "LPM_TYPE" = "LPM_COUNTER"
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "RA[11]" is stuck at GND
Warning (13410): Pin "DelayOut[0]" is stuck at GND
Warning (13410): Pin "DelayOut[3]" is stuck at GND
Info (280013): Promoted pin-driven signal(s) to global signal
Info (280014): Promoted clock signal driven by pin "C14M" to global clock signal
Warning (21074): Design contains 18 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "C14M_2"
Warning (15610): No output dependent on input pin "C7M"
Warning (15610): No output dependent on input pin "Q3"
Warning (15610): No output dependent on input pin "PHI0"
Warning (15610): No output dependent on input pin "nPRAS"
Warning (15610): No output dependent on input pin "nPCAS"
Warning (15610): No output dependent on input pin "MA[1]"
Warning (15610): No output dependent on input pin "MA[2]"
Warning (15610): No output dependent on input pin "MA[4]"
Warning (15610): No output dependent on input pin "MA[5]"
Warning (15610): No output dependent on input pin "MA[6]"
Warning (15610): No output dependent on input pin "MA[7]"
Warning (15610): No output dependent on input pin "Q3_2"
Warning (15610): No output dependent on input pin "C3M58"
Warning (15610): No output dependent on input pin "AN3"
Warning (15610): No output dependent on input pin "nCASEN"
Warning (15610): No output dependent on input pin "DelayIn[0]"
Warning (15610): No output dependent on input pin "DelayIn[3]"
Info (21057): Implemented 123 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 28 input pins
Info (21059): Implemented 12 output pins
Info (21060): Implemented 24 bidirectional pins
Info (21063): Implemented 55 macrocells
Info (21073): Implemented 4 shareable expanders
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 27 warnings
Info: Peak virtual memory: 4586 megabytes
Info: Processing ended: Sun Feb 16 22:32:22 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg.

3
cpld/output_files/RAM2E.map.smsg Executable file
View File

@ -0,0 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2E.v(39): extended using "x" or "z"
Warning (10273): Verilog HDL warning at RAM2E.v(44): extended using "x" or "z"
Warning (10273): Verilog HDL warning at RAM2E.v(49): extended using "x" or "z"

7
cpld/output_files/RAM2E.map.summary Executable file
View File

@ -0,0 +1,7 @@
Analysis & Synthesis Status : Successful - Sun Feb 16 22:32:22 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX7000S
Total macrocells : 55
Total pins : 64

147
cpld/output_files/RAM2E.pin Executable file
View File

@ -0,0 +1,147 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCC : Dedicated power pin, which MUST be connected to VCC.
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
-- NON_MIGRATABLE: This pin cannot be migrated.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
CHIP "RAM2E" ASSIGNED TO AN: EPM7128SLC84-15
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
Q3_2 : 1 : input : TTL : : : Y
Q3 : 2 : input : TTL : : : Y
VCCINT : 3 : power : : 5.0V : :
AN3 : 4 : input : TTL : : : Y
nWE : 5 : input : TTL : : : Y
nC07X : 6 : input : TTL : : : Y
GND : 7 : gnd : : : :
nPRAS : 8 : input : TTL : : : Y
C7M : 9 : input : TTL : : : Y
C3M58 : 10 : input : TTL : : : Y
DelayIn[0] : 11 : input : TTL : : : Y
DelayOut[0] : 12 : output : TTL : : : Y
VCCIO : 13 : power : : 5.0V : :
TDI : 14 : input : TTL : : : N
DelayIn[1] : 15 : input : TTL : : : Y
DelayOut[1] : 16 : output : TTL : : : Y
DelayIn[2] : 17 : input : TTL : : : Y
DelayOut[2] : 18 : output : TTL : : : Y
GND : 19 : gnd : : : :
DelayIn[3] : 20 : input : TTL : : : Y
DelayOut[3] : 21 : output : TTL : : : Y
C073SEL : 22 : output : TTL : : : Y
TMS : 23 : input : TTL : : : N
RA[10] : 24 : output : TTL : : : Y
RA[11] : 25 : output : TTL : : : Y
VCCIO : 26 : power : : 5.0V : :
nCAS : 27 : output : TTL : : : Y
RD[4] : 28 : bidir : TTL : : : Y
RD[5] : 29 : bidir : TTL : : : Y
RD[6] : 30 : bidir : TTL : : : Y
RD[7] : 31 : bidir : TTL : : : Y
GND : 32 : gnd : : : :
RD[0] : 33 : bidir : TTL : : : Y
RD[1] : 34 : bidir : TTL : : : Y
RD[2] : 35 : bidir : TTL : : : Y
RD[3] : 36 : bidir : TTL : : : Y
nRWE : 37 : output : TTL : : : Y
VCCIO : 38 : power : : 5.0V : :
nRAS : 39 : output : TTL : : : Y
RA[9] : 40 : output : TTL : : : Y
RA[8] : 41 : output : TTL : : : Y
GND : 42 : gnd : : : :
VCCINT : 43 : power : : 5.0V : :
MA[7] : 44 : input : TTL : : : Y
MA[0] : 45 : input : TTL : : : Y
MA[1] : 46 : input : TTL : : : Y
GND : 47 : gnd : : : :
MA[2] : 48 : input : TTL : : : Y
MA[3] : 49 : input : TTL : : : Y
MA[4] : 50 : input : TTL : : : Y
MA[5] : 51 : input : TTL : : : Y
MA[6] : 52 : input : TTL : : : Y
VCCIO : 53 : power : : 5.0V : :
VD[7] : 54 : bidir : TTL : : : Y
MD[7] : 55 : bidir : TTL : : : Y
VD[0] : 56 : bidir : TTL : : : Y
MD[0] : 57 : bidir : TTL : : : Y
MD[6] : 58 : bidir : TTL : : : Y
GND : 59 : gnd : : : :
VD[6] : 60 : bidir : TTL : : : Y
MD[1] : 61 : bidir : TTL : : : Y
TCK : 62 : input : TTL : : : N
VD[1] : 63 : bidir : TTL : : : Y
VD[5] : 64 : bidir : TTL : : : Y
MD[5] : 65 : bidir : TTL : : : Y
VCCIO : 66 : power : : 5.0V : :
VD[2] : 67 : bidir : TTL : : : Y
MD[2] : 68 : bidir : TTL : : : Y
MD[4] : 69 : bidir : TTL : : : Y
VD[4] : 70 : bidir : TTL : : : Y
TDO : 71 : output : TTL : : : N
GND : 72 : gnd : : : :
MD[3] : 73 : bidir : TTL : : : Y
VD[3] : 74 : bidir : TTL : : : Y
PHI0 : 75 : input : TTL : : : Y
nEN80 : 76 : input : TTL : : : Y
nCASEN : 77 : input : TTL : : : Y
VCCIO : 78 : power : : 5.0V : :
PHI1 : 79 : input : TTL : : : Y
nWE80 : 80 : input : TTL : : : Y
nPCAS : 81 : input : TTL : : : Y
GND : 82 : gnd : : : :
C14M : 83 : input : TTL : : : Y
C14M_2 : 84 : input : TTL : : : Y

BIN
cpld/output_files/RAM2E.pof Executable file
View File

Binary file not shown.

866
cpld/output_files/RAM2E.sta.rpt Executable file
View File

@ -0,0 +1,866 @@
TimeQuest Timing Analyzer report for RAM2E
Sun Feb 16 22:32:26 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Fmax Summary
6. Setup Summary
7. Hold Summary
8. Recovery Summary
9. Removal Summary
10. Minimum Pulse Width Summary
11. Setup: 'C14M'
12. Hold: 'C14M'
13. Minimum Pulse Width: 'C14M'
14. Setup Times
15. Hold Times
16. Clock to Output Times
17. Minimum Clock to Output Times
18. Propagation Delay
19. Minimum Propagation Delay
20. Output Enable Times
21. Minimum Output Enable Times
22. Output Disable Times
23. Minimum Output Disable Times
24. Setup Transfers
25. Hold Transfers
26. Report TCCS
27. Report RSKM
28. Unconstrained Paths
29. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Device Family ; MAX7000S ;
; Device Name ; EPM7128SLC84-15 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
; C14M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C14M } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
+-------------------------------------------------+
; Fmax Summary ;
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 21.28 MHz ; 21.28 MHz ; C14M ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+---------------------------------+
; Setup Summary ;
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
; C14M ; -46.000 ; -954.000 ;
+-------+---------+---------------+
+-------------------------------+
; Hold Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; C14M ; 5.000 ; 0.000 ;
+-------+-------+---------------+
--------------------
; Recovery Summary ;
--------------------
No paths to report.
-------------------
; Removal Summary ;
-------------------
No paths to report.
+--------------------------------+
; Minimum Pulse Width Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C14M ; -4.500 ; -351.000 ;
+-------+--------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'C14M' ;
+---------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
; -46.000 ; S[2] ; C073SEL~reg0 ; C14M ; C14M ; 1.000 ; 0.000 ; 43.000 ;
; -46.000 ; S[0] ; nRAS~reg0 ; C14M ; C14M ; 1.000 ; 0.000 ; 43.000 ;
; -46.000 ; S[0] ; C073SEL~reg0 ; C14M ; C14M ; 1.000 ; 0.000 ; 43.000 ;
; -46.000 ; S[3] ; C073SEL~reg0 ; C14M ; C14M ; 1.000 ; 0.000 ; 43.000 ;
; -46.000 ; S[1] ; C073SEL~reg0 ; C14M ; C14M ; 1.000 ; 0.000 ; 43.000 ;
; -46.000 ; S[3] ; nRAS~reg0 ; C14M ; C14M ; 1.000 ; 0.000 ; 43.000 ;
; -25.000 ; PHI0seen ; S[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI1reg ; S[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; S[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; S[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; S[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; S[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; S[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; S[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI0seen ; S[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI1reg ; S[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; S[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; S[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI0seen ; S[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI1reg ; S[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; S[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; S[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; S[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; S[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI0seen ; S[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; PHI1reg ; S[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; S[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; S[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; S[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; S[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; MDR[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; MDR[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; MDR[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; MDR[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; MDR[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; MDR[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; MDR[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; MDR[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; MDR[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; MDR[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; MDR[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; MDR[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; MDR[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; MDR[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; MDR[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; MDR[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; MDR[4] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; MDR[4] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; MDR[4] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; MDR[4] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; MDR[5] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; MDR[5] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; MDR[5] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; MDR[5] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; MDR[6] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; MDR[6] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; MDR[6] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; MDR[6] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; MDR[7] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; MDR[7] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; MDR[7] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; MDR[7] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; VDR[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; VDR[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; VDR[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; VDR[3] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; VDR[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; VDR[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; VDR[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; VDR[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; VDR[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; VDR[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; VDR[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; VDR[1] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; VDR[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; VDR[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; VDR[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; VDR[0] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; VDR[4] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; VDR[4] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; VDR[4] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; VDR[4] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; VDR[5] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; VDR[5] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; VDR[5] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; VDR[5] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; VDR[6] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; VDR[6] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; VDR[6] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; VDR[6] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; VDR[7] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; VDR[7] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[2] ; VDR[7] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[3] ; VDR[7] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
; -25.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 1.000 ; 0.000 ; 22.000 ;
+---------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'C14M' ;
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
; 5.000 ; S[3] ; MDBEN ; C14M ; C14M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[2] ; MDBEN ; C14M ; C14M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[0] ; MDBEN ; C14M ; C14M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; S[1] ; MDBEN ; C14M ; C14M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 9.000 ;
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 9.000 ;
; 18.000 ; PHI0seen ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI1reg ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI0seen ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI0seen ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI1reg ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI0seen ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; PHI1reg ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; MDR[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; MDR[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; MDR[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; MDR[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; MDR[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; MDR[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; MDR[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; MDR[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; MDR[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; MDR[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; MDR[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; MDR[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; MDR[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; MDR[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; MDR[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; MDR[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; MDR[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; MDR[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; MDR[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; MDR[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; MDR[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; MDR[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; MDR[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; MDR[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; MDR[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; MDR[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; MDR[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; MDR[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; MDR[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; MDR[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; MDR[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; MDR[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; VDR[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; VDR[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; VDR[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; VDR[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; VDR[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; VDR[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; VDR[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; VDR[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; VDR[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; VDR[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; VDR[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; VDR[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; VDR[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; VDR[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; VDR[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; VDR[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; VDR[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; VDR[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; VDR[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; VDR[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; VDR[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; VDR[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; VDR[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; VDR[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; VDR[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; VDR[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; VDR[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; VDR[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; VDR[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; VDR[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[2] ; VDR[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[3] ; VDR[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 22.000 ;
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------+
; Minimum Pulse Width: 'C14M' ;
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; BA[0] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; BA[0] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; BA[1] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; BA[1] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; BA[2] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; BA[2] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; BA[3] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; BA[3] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; BA[4] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; BA[4] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; BA[5] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; BA[5] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; C073SEL~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; C073SEL~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDBEN ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDBEN ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDR[0] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDR[0] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDR[1] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDR[1] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDR[2] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDR[2] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDR[3] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDR[3] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDR[4] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDR[4] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDR[5] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDR[5] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDR[6] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDR[6] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; MDR[7] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; MDR[7] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; PHI0seen ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; PHI0seen ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; PHI1reg ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; PHI1reg ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; RA[10]~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; RA[10]~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; RA[8]~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; RA[8]~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; RA[9]~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; RA[9]~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; S[0] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; S[0] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; S[1] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; S[1] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; S[2] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; S[2] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; S[3] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; S[3] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; VDR[0] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; VDR[0] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; VDR[1] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; VDR[1] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; VDR[2] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; VDR[2] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; VDR[3] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; VDR[3] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; VDR[4] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; VDR[4] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; VDR[5] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; VDR[5] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; VDR[6] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; VDR[6] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; VDR[7] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; VDR[7] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; lpm_counter:Ref_rtl_0|dffs[0] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; lpm_counter:Ref_rtl_0|dffs[0] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; lpm_counter:Ref_rtl_0|dffs[1] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; lpm_counter:Ref_rtl_0|dffs[1] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; lpm_counter:Ref_rtl_0|dffs[2] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; lpm_counter:Ref_rtl_0|dffs[2] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; lpm_counter:Ref_rtl_0|dffs[3] ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; lpm_counter:Ref_rtl_0|dffs[3] ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; nCAS~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; nCAS~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C14M ; Rise ; nRAS~reg0 ;
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C14M ; Rise ; nRAS~reg0 ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; BA[0]|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; BA[0]|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; BA[1]|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; BA[1]|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; BA[2]|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; BA[2]|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; BA[3]|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; BA[3]|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; BA[4]|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; BA[4]|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; BA[5]|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; BA[5]|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; C073SEL~reg0|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; C073SEL~reg0|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; C14M|dataout ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; C14M|dataout ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; MDBEN|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; MDBEN|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; MDR[0]|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; MDR[0]|clk ;
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C14M ; Rise ; MDR[1]|clk ;
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C14M ; Rise ; MDR[1]|clk ;
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
+-------------------------------------------------------------------------+
; Setup Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; MA[*] ; C14M ; 45.000 ; 45.000 ; Rise ; C14M ;
; MA[0] ; C14M ; 45.000 ; 45.000 ; Rise ; C14M ;
; MA[3] ; C14M ; 45.000 ; 45.000 ; Rise ; C14M ;
; MD[*] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; MD[0] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; MD[1] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; MD[2] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; MD[3] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; MD[4] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; MD[5] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; PHI1 ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[*] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[0] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[1] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[2] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[3] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[4] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[5] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[6] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; RD[7] ; C14M ; 24.000 ; 24.000 ; Rise ; C14M ;
; nC07X ; C14M ; 45.000 ; 45.000 ; Rise ; C14M ;
; nWE ; C14M ; 45.000 ; 45.000 ; Rise ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
+---------------------------------------------------------------------------+
; Hold Times ;
+-----------+------------+---------+---------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+---------+---------+------------+-----------------+
; MA[*] ; C14M ; -37.000 ; -37.000 ; Rise ; C14M ;
; MA[0] ; C14M ; -37.000 ; -37.000 ; Rise ; C14M ;
; MA[3] ; C14M ; -37.000 ; -37.000 ; Rise ; C14M ;
; MD[*] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; MD[0] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; MD[1] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; MD[2] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; MD[3] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; MD[4] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; MD[5] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; PHI1 ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[*] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[0] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[1] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[2] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[3] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[4] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[5] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[6] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; RD[7] ; C14M ; -16.000 ; -16.000 ; Rise ; C14M ;
; nC07X ; C14M ; -37.000 ; -37.000 ; Rise ; C14M ;
; nWE ; C14M ; -37.000 ; -37.000 ; Rise ; C14M ;
+-----------+------------+---------+---------+------------+-----------------+
+-------------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; C073SEL ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[*] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[0] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[1] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[2] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[3] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[4] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[5] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[6] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[7] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; RA[*] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; RA[8] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; RA[9] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; RA[10] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[*] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[0] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[1] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[2] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[3] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[4] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[5] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[6] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[7] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; nCAS ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; nRAS ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
+-------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; C073SEL ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[*] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[0] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[1] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[2] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[3] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[4] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[5] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[6] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; MD[7] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; RA[*] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; RA[8] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; RA[9] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; RA[10] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[*] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[0] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[1] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[2] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[3] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[4] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[5] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[6] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; VD[7] ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; nCAS ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
; nRAS ; C14M ; 12.000 ; 12.000 ; Rise ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
+--------------------------------------------------------------+
; Propagation Delay ;
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+--------+--------+--------+
; DelayIn[1] ; DelayOut[2] ; 32.000 ; ; ; 32.000 ;
; DelayIn[2] ; MD[0] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[1] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[2] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[3] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[4] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[5] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[6] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[7] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[0] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[1] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[2] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[3] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[4] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[5] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[6] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[7] ; 39.000 ; ; ; 39.000 ;
; MD[0] ; RD[0] ; 32.000 ; ; ; 32.000 ;
; MD[1] ; RD[1] ; 32.000 ; ; ; 32.000 ;
; MD[2] ; RD[2] ; 32.000 ; ; ; 32.000 ;
; MD[3] ; RD[3] ; 32.000 ; ; ; 32.000 ;
; MD[4] ; RD[4] ; 32.000 ; ; ; 32.000 ;
; MD[5] ; RD[5] ; 32.000 ; ; ; 32.000 ;
; MD[6] ; RD[6] ; 32.000 ; ; ; 32.000 ;
; MD[7] ; RD[7] ; 32.000 ; ; ; 32.000 ;
; PHI1 ; VD[0] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[1] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[2] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[3] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[4] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[5] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[6] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[7] ; 17.000 ; ; ; 17.000 ;
; nEN80 ; DelayOut[1] ; ; 32.000 ; 32.000 ; ;
; nWE ; MD[0] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[1] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[2] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[3] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[4] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[5] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[6] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[7] ; 39.000 ; ; ; 39.000 ;
; nWE ; RD[0] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[1] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[2] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[3] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[4] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[5] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[6] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[7] ; ; 39.000 ; 39.000 ; ;
; nWE80 ; nRWE ; 32.000 ; ; ; 32.000 ;
+------------+-------------+--------+--------+--------+--------+
+--------------------------------------------------------------+
; Minimum Propagation Delay ;
+------------+-------------+--------+--------+--------+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+--------+--------+--------+
; DelayIn[1] ; DelayOut[2] ; 32.000 ; ; ; 32.000 ;
; DelayIn[2] ; MD[0] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[1] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[2] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[3] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[4] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[5] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[6] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; MD[7] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[0] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[1] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[2] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[3] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[4] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[5] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[6] ; 39.000 ; ; ; 39.000 ;
; DelayIn[2] ; RD[7] ; 39.000 ; ; ; 39.000 ;
; MD[0] ; RD[0] ; 32.000 ; ; ; 32.000 ;
; MD[1] ; RD[1] ; 32.000 ; ; ; 32.000 ;
; MD[2] ; RD[2] ; 32.000 ; ; ; 32.000 ;
; MD[3] ; RD[3] ; 32.000 ; ; ; 32.000 ;
; MD[4] ; RD[4] ; 32.000 ; ; ; 32.000 ;
; MD[5] ; RD[5] ; 32.000 ; ; ; 32.000 ;
; MD[6] ; RD[6] ; 32.000 ; ; ; 32.000 ;
; MD[7] ; RD[7] ; 32.000 ; ; ; 32.000 ;
; PHI1 ; VD[0] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[1] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[2] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[3] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[4] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[5] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[6] ; 17.000 ; ; ; 17.000 ;
; PHI1 ; VD[7] ; 17.000 ; ; ; 17.000 ;
; nEN80 ; DelayOut[1] ; ; 32.000 ; 32.000 ; ;
; nWE ; MD[0] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[1] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[2] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[3] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[4] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[5] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[6] ; 39.000 ; ; ; 39.000 ;
; nWE ; MD[7] ; 39.000 ; ; ; 39.000 ;
; nWE ; RD[0] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[1] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[2] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[3] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[4] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[5] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[6] ; ; 39.000 ; 39.000 ; ;
; nWE ; RD[7] ; ; 39.000 ; 39.000 ; ;
; nWE80 ; nRWE ; 32.000 ; ; ; 32.000 ;
+------------+-------------+--------+--------+--------+--------+
+-----------------------------------------------------------------------+
; Output Enable Times ;
+-----------+------------+--------+------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+------+------------+-----------------+
; MD[*] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[0] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[1] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[2] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[3] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[4] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[5] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[6] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[7] ; C14M ; 41.000 ; ; Rise ; C14M ;
+-----------+------------+--------+------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Output Enable Times ;
+-----------+------------+--------+------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+------+------------+-----------------+
; MD[*] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[0] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[1] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[2] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[3] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[4] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[5] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[6] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[7] ; C14M ; 41.000 ; ; Rise ; C14M ;
+-----------+------------+--------+------+------------+-----------------+
+-------------------------------------------------------------------------------+
; Output Disable Times ;
+-----------+------------+-----------+-----------+------------+-----------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+-----------+------------+-----------+-----------+------------+-----------------+
; MD[*] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[0] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[1] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[2] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[3] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[4] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[5] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[6] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[7] ; C14M ; 41.000 ; ; Rise ; C14M ;
+-----------+------------+-----------+-----------+------------+-----------------+
+-------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+-----------+------------+-----------+-----------+------------+-----------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+-----------+------------+-----------+-----------+------------+-----------------+
; MD[*] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[0] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[1] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[2] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[3] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[4] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[5] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[6] ; C14M ; 41.000 ; ; Rise ; C14M ;
; MD[7] ; C14M ; 41.000 ; ; Rise ; C14M ;
+-----------+------------+-----------+-----------+------------+-----------------+
+-------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C14M ; C14M ; 247 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C14M ; C14M ; 247 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 25 ; 25 ;
; Unconstrained Input Port Paths ; 84 ; 84 ;
; Unconstrained Output Ports ; 33 ; 33 ;
; Unconstrained Output Port Paths ; 81 ; 81 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Sun Feb 16 22:32:25 2020
Info: Command: quartus_sta RAM2E -c RAM2E
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (306004): Started post-fitting delay annotation
Info (306005): Delay annotation completed successfully
Warning (335095): TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2E.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name C14M C14M
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -46.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -46.000 -954.000 C14M
Info (332146): Worst-case hold slack is 5.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 5.000 0.000 C14M
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -4.500
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -4.500 -351.000 C14M
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 4525 megabytes
Info: Processing ended: Sun Feb 16 22:32:26 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

17
cpld/output_files/RAM2E.sta.summary Executable file
View File

@ -0,0 +1,17 @@
------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'C14M'
Slack : -46.000
TNS : -954.000
Type : Hold 'C14M'
Slack : 5.000
TNS : 0.000
Type : Minimum Pulse Width 'C14M'
Slack : -4.500
TNS : -351.000
------------------------------------------------------------

1
cpld/simulation/modelsim/RAM2E.sft Executable file
View File

@ -0,0 +1 @@
set tool_name "ModelSim-Altera (Verilog)"

2527
cpld/simulation/modelsim/RAM2E.vo Executable file
View File

File diff suppressed because it is too large Load Diff

136
cpld/simulation/modelsim/RAM2E_modelsim.xrf Executable file
View File

@ -0,0 +1,136 @@
vendor_name = ModelSim
source_file = 1, C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v
source_file = 1, C:/Users/Zane/Documents/GitHub/RAM2E/cpld/Simulation.vwf
source_file = 1, C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/RAM2E.cbx.xml
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cmpconst.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/dffeea.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_counter_stratix.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc
source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cbx.lst
design_name = RAM2E
instance = comp, \MA[0]~I , MA[0], RAM2E, 1
instance = comp, \MD[0]~I , MD[0], RAM2E, 1
instance = comp, \MD[1]~I , MD[1], RAM2E, 1
instance = comp, \MD[2]~I , MD[2], RAM2E, 1
instance = comp, \MD[3]~I , MD[3], RAM2E, 1
instance = comp, \MD[4]~I , MD[4], RAM2E, 1
instance = comp, \MD[5]~I , MD[5], RAM2E, 1
instance = comp, \MD[6]~I , MD[6], RAM2E, 1
instance = comp, \MD[7]~I , MD[7], RAM2E, 1
instance = comp, \RD[0]~I , RD[0], RAM2E, 1
instance = comp, \RD[1]~I , RD[1], RAM2E, 1
instance = comp, \RD[2]~I , RD[2], RAM2E, 1
instance = comp, \RD[3]~I , RD[3], RAM2E, 1
instance = comp, \RD[4]~I , RD[4], RAM2E, 1
instance = comp, \RD[5]~I , RD[5], RAM2E, 1
instance = comp, \RD[6]~I , RD[6], RAM2E, 1
instance = comp, \RD[7]~I , RD[7], RAM2E, 1
instance = comp, \C14M~I , C14M, RAM2E, 1
instance = comp, \PHI1~I , PHI1, RAM2E, 1
instance = comp, \S[2] , S[2], RAM2E, 1
instance = comp, \S[3] , S[3], RAM2E, 1
instance = comp, \S[1] , S[1], RAM2E, 1
instance = comp, \S[0] , S[0], RAM2E, 1
instance = comp, \MDR[0] , MDR[0], RAM2E, 1
instance = comp, \nWE~I , nWE, RAM2E, 1
instance = comp, \DelayIn[2]~I , DelayIn[2], RAM2E, 1
instance = comp, \MDOE~1 , MDOE~1, RAM2E, 1
instance = comp, \MDR[1] , MDR[1], RAM2E, 1
instance = comp, \MDR[2] , MDR[2], RAM2E, 1
instance = comp, \MDR[3] , MDR[3], RAM2E, 1
instance = comp, \MDR[4] , MDR[4], RAM2E, 1
instance = comp, \MDR[5] , MDR[5], RAM2E, 1
instance = comp, \MDR[6] , MDR[6], RAM2E, 1
instance = comp, \MDR[7] , MDR[7], RAM2E, 1
instance = comp, \MD[0]~24 , MD[0]~24, RAM2E, 1
instance = comp, \RDOE~1 , RDOE~1, RAM2E, 1
instance = comp, \MD[1]~26 , MD[1]~26, RAM2E, 1
instance = comp, \MD[2]~28 , MD[2]~28, RAM2E, 1
instance = comp, \MD[3]~30 , MD[3]~30, RAM2E, 1
instance = comp, \MD[4]~32 , MD[4]~32, RAM2E, 1
instance = comp, \MD[5]~34 , MD[5]~34, RAM2E, 1
instance = comp, \MD[6]~36 , MD[6]~36, RAM2E, 1
instance = comp, \MD[7]~38 , MD[7]~38, RAM2E, 1
instance = comp, \~GND~0 , ~GND~0, RAM2E, 1
instance = comp, \~GND~1 , ~GND~1, RAM2E, 1
instance = comp, \~GND~2 , ~GND~2, RAM2E, 1
instance = comp, \nWE80~I , nWE80, RAM2E, 1
instance = comp, \nWE80~1 , nWE80~1, RAM2E, 1
instance = comp, \nEN80~I , nEN80, RAM2E, 1
instance = comp, \nEN80~1 , nEN80~1, RAM2E, 1
instance = comp, \DelayIn[1]~I , DelayIn[1], RAM2E, 1
instance = comp, \DelayIn[1]~1 , DelayIn[1]~1, RAM2E, 1
instance = comp, \VDR[0] , VDR[0], RAM2E, 1
instance = comp, \VDR[1] , VDR[1], RAM2E, 1
instance = comp, \VDR[2] , VDR[2], RAM2E, 1
instance = comp, \VDR[3] , VDR[3], RAM2E, 1
instance = comp, \VDR[4] , VDR[4], RAM2E, 1
instance = comp, \VDR[5] , VDR[5], RAM2E, 1
instance = comp, \VDR[6] , VDR[6], RAM2E, 1
instance = comp, \VDR[7] , VDR[7], RAM2E, 1
instance = comp, \C073SEL~7 , C073SEL~7, RAM2E, 1
instance = comp, \MA[3]~I , MA[3], RAM2E, 1
instance = comp, \C073SEL~8 , C073SEL~8, RAM2E, 1
instance = comp, \nC07X~I , nC07X, RAM2E, 1
instance = comp, \C073SEL~9 , C073SEL~9, RAM2E, 1
instance = comp, \C073SEL~reg0 , C073SEL~reg0, RAM2E, 1
instance = comp, \BA[4] , BA[4], RAM2E, 1
instance = comp, \RA[10]~reg0 , RA[10]~reg0, RAM2E, 1
instance = comp, \BA[2] , BA[2], RAM2E, 1
instance = comp, \BA[0] , BA[0], RAM2E, 1
instance = comp, \RA[8]~reg0 , RA[8]~reg0, RAM2E, 1
instance = comp, \BA[5] , BA[5], RAM2E, 1
instance = comp, \BA[3] , BA[3], RAM2E, 1
instance = comp, \BA[1] , BA[1], RAM2E, 1
instance = comp, \RA[9]~reg0 , RA[9]~reg0, RAM2E, 1
instance = comp, \Ref_rtl_0|dffs[2] , Ref_rtl_0|dffs[2], RAM2E, 1
instance = comp, \Ref_rtl_0|dffs[0] , Ref_rtl_0|dffs[0], RAM2E, 1
instance = comp, \Ref_rtl_0|dffs[1] , Ref_rtl_0|dffs[1], RAM2E, 1
instance = comp, \Ref_rtl_0|dffs[3] , Ref_rtl_0|dffs[3], RAM2E, 1
instance = comp, \nRAS~8 , nRAS~8, RAM2E, 1
instance = comp, \nRAS~reg0 , nRAS~reg0, RAM2E, 1
instance = comp, \nCAS~reg0 , nCAS~reg0, RAM2E, 1
instance = comp, \C14M_2~I , C14M_2, RAM2E, 1
instance = comp, \C7M~I , C7M, RAM2E, 1
instance = comp, \Q3~I , Q3, RAM2E, 1
instance = comp, \PHI0~I , PHI0, RAM2E, 1
instance = comp, \nPRAS~I , nPRAS, RAM2E, 1
instance = comp, \nPCAS~I , nPCAS, RAM2E, 1
instance = comp, \MA[1]~I , MA[1], RAM2E, 1
instance = comp, \MA[2]~I , MA[2], RAM2E, 1
instance = comp, \MA[4]~I , MA[4], RAM2E, 1
instance = comp, \MA[5]~I , MA[5], RAM2E, 1
instance = comp, \MA[6]~I , MA[6], RAM2E, 1
instance = comp, \MA[7]~I , MA[7], RAM2E, 1
instance = comp, \RA[11]~I , RA[11], RAM2E, 1
instance = comp, \Q3_2~I , Q3_2, RAM2E, 1
instance = comp, \C3M58~I , C3M58, RAM2E, 1
instance = comp, \AN3~I , AN3, RAM2E, 1
instance = comp, \nCASEN~I , nCASEN, RAM2E, 1
instance = comp, \DelayIn[0]~I , DelayIn[0], RAM2E, 1
instance = comp, \DelayIn[3]~I , DelayIn[3], RAM2E, 1
instance = comp, \DelayOut[0]~I , DelayOut[0], RAM2E, 1
instance = comp, \DelayOut[3]~I , DelayOut[3], RAM2E, 1
instance = comp, \nRWE~I , nRWE, RAM2E, 1
instance = comp, \DelayOut[1]~I , DelayOut[1], RAM2E, 1
instance = comp, \DelayOut[2]~I , DelayOut[2], RAM2E, 1
instance = comp, \VD[0]~I , VD[0], RAM2E, 1
instance = comp, \VD[1]~I , VD[1], RAM2E, 1
instance = comp, \VD[2]~I , VD[2], RAM2E, 1
instance = comp, \VD[3]~I , VD[3], RAM2E, 1
instance = comp, \VD[4]~I , VD[4], RAM2E, 1
instance = comp, \VD[5]~I , VD[5], RAM2E, 1
instance = comp, \VD[6]~I , VD[6], RAM2E, 1
instance = comp, \VD[7]~I , VD[7], RAM2E, 1
instance = comp, \C073SEL~I , C073SEL, RAM2E, 1
instance = comp, \RA[10]~I , RA[10], RAM2E, 1
instance = comp, \RA[8]~I , RA[8], RAM2E, 1
instance = comp, \RA[9]~I , RA[9], RAM2E, 1
instance = comp, \nRAS~I , nRAS, RAM2E, 1
instance = comp, \nCAS~I , nCAS, RAM2E, 1

1880
cpld/simulation/modelsim/RAM2E_v.sdo Executable file
View File

File diff suppressed because it is too large Load Diff

10
cpld/simulation/qsim/RAM2E.do Executable file
View File

@ -0,0 +1,10 @@
onerror {quit -f}
vlib work
vlog -work work RAM2E.vo
vlog -work work RAM2E.vt
vsim -novopt -c -t 1ps -L max7000s_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.RAM2E_vlg_vec_tst
vcd file -direction RAM2E.msim.vcd
vcd add -internal RAM2E_vlg_vec_tst/*
vcd add -internal RAM2E_vlg_vec_tst/i1/*
add wave /*
run -all

Some files were not shown because too many files have changed in this diff Show More