Zane Kaminski
9ad3a94263
Update Makefile
2023-11-07 15:35:42 -05:00
Zane Kaminski
38c155d6b0
2.1?
2023-11-03 04:35:53 -04:00
Zane Kaminski
a9d1ca7995
Fixed MachXO board wrong JTAG pinout
2023-09-21 07:26:21 -04:00
Zane Kaminski
eaeba53cda
Merge branch 'dev-GW4203B-2.0' into dev-GW4203B
2023-09-21 05:50:11 -04:00
Zane Kaminski
dec33238f1
RC
2023-09-21 05:45:21 -04:00
Zane Kaminski
7a4150866d
Remove old files
2023-09-21 05:33:45 -04:00
Zane Kaminski
3ede4b322f
Documentation update
2021-09-04 23:56:58 -04:00
Zane Kaminski
aae70e15f7
Documentation update
2021-08-06 02:37:57 -04:00
Zane Kaminski
385bd8cf01
Documentation update
2021-08-06 02:37:29 -04:00
Zane Kaminski
cc3e8eee05
Fabbed
2021-07-02 03:26:28 -04:00
Zane Kaminski
8bdf1ed67b
Add stencil zip files
2021-06-01 06:17:37 -04:00
Zane Kaminski
6c35796a09
Zip everything
2021-06-01 05:30:29 -04:00
Zane Kaminski
2a7fe4255f
BOM finished
2021-06-01 05:30:16 -04:00
Zane Kaminski
b631c47120
DNP 3d models and add FrontIsom render pics of all board variants
2021-06-01 05:15:30 -04:00
Zane Kaminski
62e88ed09a
Fixed DRC violations on LCMXO2 and iCE40 boards
2021-06-01 04:25:55 -04:00
Zane Kaminski
8bfd2e7747
Generated gerbers and documentation
2021-06-01 04:01:07 -04:00
Zane Kaminski
49f5b75493
idk
2021-05-23 00:44:33 -04:00
Zane Kaminski
3dfd39e40f
still workin
2021-05-22 17:35:02 -04:00
Zane Kaminski
26ce482a1d
started
2021-05-08 02:48:29 -04:00
Zane Kaminski
6da25b024e
Documentation update
2021-04-13 03:41:45 -04:00
Zane Kaminski
b26cc3582d
Add transparent isometric front image
2021-04-03 01:06:25 -04:00
Zane Kaminski
3614fb0c10
Remove dev note stuff from manual
2021-04-03 00:43:52 -04:00
Zane Kaminski
b61242900b
Add dev note
2021-04-03 00:43:41 -04:00
Zane Kaminski
25b6032966
Removed old MAX II stuff from MAX V directory
2021-03-10 21:14:36 -05:00
Zane Kaminski
3fcf6a1bb2
Added MAX V CPLD firmware
2021-03-10 21:14:12 -05:00
Zane Kaminski
fc00c0c422
Rename /cpld directory to /cpld_maxii
2021-03-10 20:47:44 -05:00
Zane Kaminski
dcd0c240a6
Add MAX V BOM and placement table
2021-02-16 14:44:27 -05:00
Zane Kaminski
f3a3759c04
Documentation update
2021-01-31 15:56:55 -05:00
Zane Kaminski
8004b1caf4
Merge branch 'dev-GW4203B-1.3' into dev-GW4203B
2021-01-28 20:39:34 -05:00
Zane Kaminski
cc016d9032
Gitignore Quartus CDFs (chain definition files)
2021-01-28 14:43:03 -05:00
Zane Kaminski
ae8c84d2c9
Refresh rate increase compiled in Quartus
2021-01-28 14:42:44 -05:00
Zane Kaminski
245a7e8a30
Merge branch 'dev-GW4203B-1.3' into dev-GW4203B
2021-01-24 08:47:56 -05:00
Zane Kaminski
8c50842fed
Merge branch 'dev-GW4203B-1.2' into dev-GW4203B
2021-01-24 08:35:41 -05:00
Zane Kaminski
2b838cdd7f
Increased refresh frequency
2020-12-26 14:15:17 -05:00
Zane Kaminski
a688f82d4f
Fabbed
2020-12-25 13:02:24 -05:00
Zane Kaminski
4a9341dcc8
Added C14M buffering and header
2020-12-16 14:43:41 -05:00
Zane Kaminski
455f9e99f1
Actually fabbed 10/6/2020
2020-10-09 13:02:03 -04:00
Zane Kaminski
5af7a4b84d
Fabbed 9/29/2020
2020-09-29 14:59:55 -04:00
Zane Kaminski
a4fc5a2ebe
Update timing diagram in schematic
...
Now reflects longer MAX V propagation delays
2020-09-25 13:05:58 -04:00
Zane Kaminski
cdb4c1f4c8
Create Banner.jpg
2020-09-18 16:05:22 -04:00
Zane Kaminski
d15023c86f
Update GW4203BManual
2020-09-18 00:47:18 -04:00
Zane Kaminski
a4c86c60f8
Update GW4203BManual
2020-09-18 00:45:40 -04:00
Zane Kaminski
29a75c8028
Delete Picture.png
2020-09-18 00:45:19 -04:00
Zane Kaminski
7d88c5d625
Merge branch 'dev-GW4203B-1.2' of https://github.com/garrettsworkshop/RAM2E into dev-GW4203B-1.2
2020-09-17 23:32:03 -04:00
Zane Kaminski
383c2b5760
Merge branch 'dev-GW4203B-1.2' of https://github.com/garrettsworkshop/RAM2E into dev-GW4203B-1.2
2020-09-17 23:32:01 -04:00
Zane Kaminski
7ff514a26c
Fix snow on screen
...
Previous commit had "snow" in 80-col mode when updating display. Put back command timing to fix problem. Kept PHI0 read gating depending on EN80 and data output gating
2020-09-16 20:20:16 -04:00
Zane Kaminski
8eb7ead8ee
Improve power consumption
...
Gated RAM access during PHI0, squeezed video access and MPU access together, gated data bus output buffer OE to only output at end of PHI0
2020-09-16 19:49:18 -04:00
Zane Kaminski
9a3e845413
Actually put the right pictures
2020-09-11 16:36:18 -04:00
Zane Kaminski
2a58e754c6
Updated pictures
2020-09-11 16:30:51 -04:00
Zane Kaminski
e8dee0f319
Updated schematic with 1V8 regulator and MAX V
2020-09-10 10:44:47 -04:00