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GNU GENERAL PUBLIC LICENSE
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*.sch~
*.bak
*.bak0
*.pcb.old

35
hardware/Makefile Normal file
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JUNK =\
scsi2sd.pcb.bak \
scsi2sd.pcb.bak0 \
scsi2sd.pcb.old \
scsi2sd.sch~ \
SYMBOLS =\
symbols/7406.sym \
symbols/CY8C53.sym \
symbols/FCI-10067847.sym \
symbols/LD1117.sym \
symbols/MOLEX8981.sym \
symbols/SCDA7A0101.sym \
symbols/wurth-microsd.sym \
all: $(SYMBOLS) scsi2sd.bom scsi2sd.pcb
symbols/%.sym : symbols/%.tragesym
tragesym $< $@
scsi2sd.bom : scsi2sd.sch
gnetlist -g partslist3 -o scsi2sd.bom scsi2sd.sch
scsi2sd.pcb : scsi2sd.sch
gsch2pcb -d symbols scsi2sd.sch
clean:
rm $(JUNK)
realclean:
rm $(JUNK)
rm $(SYMBOLS)

208
hardware/bracket/3.5_hdd_mount.scad Normal file
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// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
//
// This file is part of SCSI2SD.
//
// SCSI2SD is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// SCSI2SD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
$fa = 3; // 4-times as many angles per circle.
$fs = 0.1; // 0.1mm accuracy
// A* taken from SFF-8301 Specification for Form Factor of 3.5" Disk Drives
A3 = 101.6; // width
A5 = 3.19; // Distance from side to bottom hole.
A6 = 44.45; // Distance from A7 to second bottom hole.
A7 = 41.28; // Distance from front to bottom holes.
A8 = 28.5; // Distance from front to side holes
A9 = 101.60; // Distance between side holes.
A10 = 6.35; // Height from base to site holes.
A13 = 76.2; // Distance from A7 to third bottom hole.
m3HoleRadius=2.667/2; // M3x0.50 minimum hole size (aluminium or softer material)
holeBulk=4; // Extra around holes
tmp = 10;
wallWidth = 1.3;
screwWidth = 3;
foo = 6;
bar = 4; // PSOC MOUNT
PCB_DIFF=90.42; // Clearance line of "fat" via is 10mil from edge.
PCB_off = (A3 - PCB_DIFF) / 2;
// from front = A7 + foo = 47.28
// second = 47.28 + A6 = 91.73. Perfect!
// Height between board and screw:
// screwWidth + 1.6mm pcb only = 3 + 1.6 =4.6. Not a problem!
// Width of PCB vs side hole bulk: 101.6 - 97.5360 = 4.064
// only 2mm to spare on either side.
// TODO Made a NOTCH in the PCB to handle this!
// notch: A8 +- holeBulk = 28.5 - 4, 28.5 + 4 = 24 -> 33mm. 3mm in.
module hdd_side()
{
difference()
{
union()
{
cube([A8 + A9 + tmp, wallWidth, A10 + holeBulk]);
// Bottom mount 1
translate([A7 - (foo / 2), 0, 0])
{
cube([foo, foo, screwWidth]);
}
// Bottom mount 2
translate([A6 + A7 - (foo / 2), 0, 0])
{
cube([foo, foo, screwWidth]);
}
// Bottom mount 3
translate([A13 + A7 - (foo / 2), 0, 0])
{
cube([foo, foo, screwWidth]);
}
// psoc mount 1
translate([A7 - (foo / 2) + foo, 0, 0])
{
cube([foo, foo + bar, screwWidth]);
}
// psoc mount 2
translate([A6 + A7 - (foo / 2) + foo, 0, 0])
{
cube([foo, foo + bar, screwWidth]);
}
// Extra bulk behind side holes
translate([A8, 0, A10])
{
rotate([270, 0, 0])
{
cylinder(h=screwWidth, r=holeBulk);
}
}
translate([A8 + A9, 0, A10])
{
rotate([270, 0, 0])
{
cylinder(h=screwWidth, r=holeBulk);
}
}
}
// Remove excess material from the side
translate([-0.5, -0.5,screwWidth + wallWidth])
{
cube([A8 - tmp + 0.5, wallWidth + 1, A10 + holeBulk]);
}
translate([A8 + tmp, -0.5, screwWidth + wallWidth])
{
cube([A9 - (tmp * 2), wallWidth + 1, A10 + holeBulk]);
}
// SIDE HOLES
translate([A8, -0.5, A10])
{
rotate([270, 0, 0])
{
cylinder(h=screwWidth + 1, r=m3HoleRadius);
}
}
translate([A8 + A9, -0.5, A10])
{
rotate([270, 0, 0])
{
cylinder(h=screwWidth + 1, r=m3HoleRadius);
}
}
// BOTTOM HOLES
// Bottom hole 1
translate([A7, A5, -0.5])
{
cylinder(h=screwWidth + 1, r = m3HoleRadius);
}
// Bottom hole 2
translate([A6 + A7, A5, -0.5])
{
cylinder(h=screwWidth + 1, r = m3HoleRadius);
}
// Bottom hole 3
translate([A13 + A7, A5, -0.5])
{
cylinder(h=screwWidth + 1, r = m3HoleRadius);
}
// PSOC hole1
translate([A7 + foo, PCB_off, -0.5])
{
cylinder(h=screwWidth + 1, r = m3HoleRadius);
}
// PSOC hole2
translate([A6 + A7 + foo, PCB_off, -0.5])
{
cylinder(h=screwWidth + 1, r = m3HoleRadius);
}
}
}
union()
{
hdd_side();
translate([0, A3, 0])
{
mirror([0, 1, 0])
{
hdd_side();
}
}
cube([wallWidth * 2, A3, wallWidth]);
translate([A8 + A9 + tmp - wallWidth * 2, 0, 0])
{
cube([wallWidth * 2, A3, wallWidth]);
}
// Bottom hole 1
translate([A7 + foo, foo + bar, 0])
{
cube([wallWidth * 2, A3 - ((foo + bar) * 2), wallWidth]);
}
// Bottom hole 2
translate([A6 + A7 + foo, foo + bar, 0])
{
cube([wallWidth * 2, A3 - ((foo + bar) * 2), wallWidth]);
}
for (i = [0:3])
{
translate([0, (i * (A3 - wallWidth) / 3), 0])
{
cube([A8 + A9 + tmp, wallWidth, wallWidth]);
}
}
}

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hardware/gafrc Normal file
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(component-library "./symbols")
(load (string-append geda-data-path "/scheme/auto-uref.scm")) ; load the autonumbering script
(add-hook! add-component-hook auto-uref) ; autonumber when adding a component
(add-hook! copy-component-hook auto-uref) ; autonumber when copying a component
(output-color "enabled")

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G04 start of page 14 for group -4078 idx -4078 *
G04 Title: (unknown), bottomsilk *
G04 Creator: pcb 20110918 *
G04 CreationDate: Wed 02 Oct 2013 12:06:16 GMT UTC *
G04 For: michael *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions: 384000 393500 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNBOTTOMSILK*%
%ADD11C,0.0100*%
M02*

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G04 start of page 8 for group -4062 idx -4062 *
G04 Title: (unknown), soldermask *
G04 Creator: pcb 20110918 *
G04 CreationDate: Wed 02 Oct 2013 12:02:10 GMT UTC *
G04 For: michael *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions: 384000 393500 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNBOTTOMMASK*%
%ADD98C,0.1600*%
%ADD97C,0.1100*%
%ADD96C,0.0001*%
%ADD95C,0.0660*%
G54D95*X132000Y349500D03*
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X44300D01*
Y316800D01*
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G37*
G54D95*X41000Y303500D03*
M02*

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G04 start of page 7 for group -4063 idx -4063 *
G04 Title: (unknown), componentmask *
G04 Creator: pcb 20110918 *
G04 CreationDate: Wed 02 Oct 2013 12:02:10 GMT UTC *
G04 For: michael *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions: 384000 393500 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNTOPMASK*%
%ADD94C,0.0410*%
%ADD93R,0.0375X0.0375*%
%ADD92R,0.1006X0.1006*%
%ADD91R,0.0660X0.0660*%
%ADD90R,0.0769X0.0769*%
%ADD89R,0.0690X0.0690*%
%ADD88R,0.0218X0.0218*%
%ADD87R,0.0750X0.0750*%
%ADD86R,0.0300X0.0300*%
%ADD85R,0.0611X0.0611*%
%ADD84R,0.0140X0.0140*%
%ADD83R,0.0510X0.0510*%
%ADD82C,0.1600*%
%ADD81C,0.1100*%
%ADD80C,0.0001*%
%ADD79C,0.0660*%
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G37*
G36*
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Y148750D01*
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G37*
G36*
Y133750D02*Y121250D01*
X351750D01*
Y133750D01*
X339250D01*
G37*
G54D87*X347000Y111500D02*Y106000D01*
X329000Y111500D02*Y106000D01*
G54D83*X314300Y100000D02*X315700D01*
X343800Y71500D02*X345200D01*
X343800Y79500D02*X345200D01*
X333300Y71500D02*X334700D01*
X333300Y79500D02*X334700D01*
X322800Y71500D02*X324200D01*
X322800Y79500D02*X324200D01*
X312300Y71500D02*X313700D01*
X312300Y79500D02*X313700D01*
X301300Y71500D02*X302700D01*
X301300Y79500D02*X302700D01*
X290300Y71500D02*X291700D01*
X290300Y79500D02*X291700D01*
X361800Y99000D02*X363200D01*
X361800Y107000D02*X363200D01*
G54D84*X221610Y98378D02*X226508D01*
X221610Y100346D02*X226508D01*
X221610Y102315D02*X226508D01*
X221610Y104283D02*X226508D01*
X221610Y106252D02*X226508D01*
X221610Y108220D02*X226508D01*
X221610Y110189D02*X226508D01*
X221610Y112157D02*X226508D01*
G54D83*X240500Y74700D02*Y73300D01*
G54D85*X246831Y63071D02*X248406D01*
G54D88*X172725Y18902D02*Y15162D01*
X177843Y18902D02*Y15162D01*
X167607Y18902D02*Y15162D01*
X175284Y18902D02*Y15162D01*
X170166Y18902D02*Y15162D01*
G54D89*X159536Y16540D02*X161504D01*
X183945D02*X185914D01*
G54D90*X157764Y6697D02*Y6303D01*
G54D91*X157000Y34000D02*Y33000D01*
X145000Y34000D02*Y33000D01*
G54D92*X127607Y56000D02*X128394D01*
X144536D02*X145323D01*
G54D80*G36*
X163960Y10540D02*Y2460D01*
X172040D01*
Y10540D01*
X163960D01*
G37*
G36*
X173409D02*Y2460D01*
X181489D01*
Y10540D01*
X173409D01*
G37*
G54D90*X187685Y6697D02*Y6303D01*
G54D80*G36*
X279216Y17284D02*Y14716D01*
X281784D01*
Y17284D01*
X279216D01*
G37*
G36*
X275278D02*Y14716D01*
X277848D01*
Y17284D01*
X275278D01*
G37*
G54D85*X270453Y7953D02*Y5984D01*
G54D93*X251555Y23701D02*Y20945D01*
X247224Y25276D02*Y22520D01*
X242894Y23701D02*Y20945D01*
X238563Y22913D02*Y20157D01*
X234232Y23701D02*Y20945D01*
X229902Y22913D02*Y20157D01*
X225571Y23701D02*Y20945D01*
X221240Y23701D02*Y20945D01*
G54D85*X218091Y12283D02*Y10315D01*
G54D86*X148000Y226000D02*Y219500D01*
X143000Y226000D02*Y219500D01*
X138000Y226000D02*Y219500D01*
X133000Y226000D02*Y219500D01*
X128000Y226000D02*Y219500D01*
X123000Y226000D02*Y219500D01*
X118000Y226000D02*Y219500D01*
G54D83*X73800Y230000D02*X75200D01*
X73800Y222000D02*X75200D01*
G54D92*X20500Y234894D02*Y234107D01*
Y251823D02*Y251036D01*
G54D86*X118000Y205500D02*Y199000D01*
X123000Y205500D02*Y199000D01*
X128000Y205500D02*Y199000D01*
X133000Y205500D02*Y199000D01*
X138000Y205500D02*Y199000D01*
X143000Y205500D02*Y199000D01*
X148000Y205500D02*Y199000D01*
G54D80*G36*
X152216Y211284D02*Y208716D01*
X154784D01*
Y211284D01*
X152216D01*
G37*
G36*
Y207348D02*Y204778D01*
X154784D01*
Y207348D01*
X152216D01*
G37*
G54D91*X20500Y321000D02*X21500D01*
X20500Y309000D02*X21500D01*
G54D92*X76106D02*X76893D01*
X59177D02*X59964D01*
G54D84*X156492Y145622D02*X161390D01*
X156492Y143654D02*X161390D01*
X156492Y141685D02*X161390D01*
X156492Y139717D02*X161390D01*
X156492Y137748D02*X161390D01*
X156492Y135780D02*X161390D01*
G54D80*G36*
X159716Y153784D02*Y151216D01*
X162284D01*
Y153784D01*
X159716D01*
G37*
G54D83*X135000Y155200D02*Y153800D01*
X143000Y155200D02*Y153800D01*
G54D80*G36*
X159716Y157722D02*Y155152D01*
X162284D01*
Y157722D01*
X159716D01*
G37*
G54D84*X156492Y133811D02*X161390D01*
X156492Y131843D02*X161390D01*
X156492Y129874D02*X161390D01*
X156492Y127906D02*X161390D01*
X156492Y125937D02*X161390D01*
X156492Y123969D02*X161390D01*
X156492Y122000D02*X161390D01*
X156492Y120032D02*X161390D01*
X156492Y118063D02*X161390D01*
X156492Y116095D02*X161390D01*
X156492Y114126D02*X161390D01*
X156492Y112158D02*X161390D01*
X156492Y110189D02*X161390D01*
X156492Y108221D02*X161390D01*
X156492Y106252D02*X161390D01*
X156492Y104284D02*X161390D01*
X156492Y102315D02*X161390D01*
X156492Y100347D02*X161390D01*
G54D94*X124844Y85950D02*X132944D01*
X108844D02*X116944D01*
X124844Y90950D02*X132944D01*
X108844D02*X116944D01*
X108844Y95950D02*X116944D01*
X108844Y100950D02*X116944D01*
X108844Y105950D02*X116944D01*
X124844Y95950D02*X132944D01*
X124844Y100950D02*X132944D01*
X124844Y105950D02*X132944D01*
G54D84*X215122Y157008D02*Y152110D01*
X213154Y157008D02*Y152110D01*
X211185Y157008D02*Y152110D01*
X209217Y157008D02*Y152110D01*
X207248Y157008D02*Y152110D01*
X205280Y157008D02*Y152110D01*
G54D80*G36*
X220716Y157722D02*Y155152D01*
X223284D01*
Y157722D01*
X220716D01*
G37*
G36*
Y153784D02*Y151216D01*
X223284D01*
Y153784D01*
X220716D01*
G37*
G54D84*X203311Y157008D02*Y152110D01*
X201343Y157008D02*Y152110D01*
X199374Y157008D02*Y152110D01*
X197406Y157008D02*Y152110D01*
X195437Y157008D02*Y152110D01*
X193469Y157008D02*Y152110D01*
X191500Y157008D02*Y152110D01*
G54D80*G36*
X191216Y166222D02*Y163652D01*
X193784D01*
Y166222D01*
X191216D01*
G37*
G36*
Y162284D02*Y159716D01*
X193784D01*
Y162284D01*
X191216D01*
G37*
G54D84*X189532Y157008D02*Y152110D01*
X187563Y157008D02*Y152110D01*
X185595Y157008D02*Y152110D01*
X183626Y157008D02*Y152110D01*
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X179689Y157008D02*Y152110D01*
X177721Y157008D02*Y152110D01*
X175752Y157008D02*Y152110D01*
X173784Y157008D02*Y152110D01*
X171815Y157008D02*Y152110D01*
X169847Y157008D02*Y152110D01*
X167878Y157008D02*Y152110D01*
G54D86*X261500Y226250D02*Y219750D01*
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Y205750D02*Y199250D01*
X261500Y205750D02*Y199250D01*
X266500Y205750D02*Y199250D01*
X271500Y205750D02*Y199250D01*
X276500Y205750D02*Y199250D01*
G54D80*G36*
X230216Y211284D02*Y208716D01*
X232784D01*
Y211284D01*
X230216D01*
G37*
G36*
Y207348D02*Y204778D01*
X232784D01*
Y207348D01*
X230216D01*
G37*
G54D86*X216000Y226000D02*Y219500D01*
G54D83*X204800Y266000D02*X206200D01*
X204800Y258000D02*X206200D01*
G54D86*X211000Y226000D02*Y219500D01*
X206000Y226000D02*Y219500D01*
X201000Y226000D02*Y219500D01*
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X216000Y205500D02*Y199000D01*
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X226000Y205500D02*Y199000D01*
M02*

206
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M48
INCH
T78C0.035
T77C0.125
T76C0.012
T75C0.157
T74C0.100
T73C0.060
T72C0.028
T71C0.038
%
T76
X017250Y008150
X019700Y006700
X017800Y002400
X027750Y003100
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X027750Y004300
X027750Y004950
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T72
X030700Y024600
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T78
X011150Y005550
X034700Y009350
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X032950Y020300
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X007400Y021300
X007450Y023900
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T71
X013200Y034950
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X018200Y034950
X016200Y033950
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T73
X006100Y033950
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T74
X009100Y034950
X001100Y034950
T77
X001400Y003200
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T75
X003100Y037950
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M30

25
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G04 start of page 4 for group 2 idx 2 *
G04 Title: (unknown), outline *
G04 Creator: pcb 20110918 *
G04 CreationDate: Wed 02 Oct 2013 12:02:10 GMT UTC *
G04 For: michael *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions: 384000 393500 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNOUTLINE*%
%ADD56C,0.0100*%
G54D56*X367500Y263000D02*X383500D01*
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M02*

490
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G04 start of page 10 for group -4015 idx -4015 *
G04 Title: (unknown), toppaste *
G04 Creator: pcb 20110918 *
G04 CreationDate: Wed 02 Oct 2013 12:02:10 GMT UTC *
G04 For: michael *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions: 384000 393500 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNTOPPASTE*%
%ADD116R,0.0906X0.0906*%
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%ADD107C,0.0001*%
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G54D104*X362500Y327200D02*Y325800D01*
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G54D105*X148000Y226000D02*Y219500D01*
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G54D104*X287500Y157200D02*Y155800D01*
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G54D105*X286500Y226250D02*Y219750D01*
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G54D104*X204800Y266000D02*X206200D01*
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G54D106*X156492Y145622D02*X161390D01*
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X221610Y131842D02*X226508D01*
X221610Y133811D02*X226508D01*
X221610Y135779D02*X226508D01*
X221610Y137748D02*X226508D01*
X221610Y139716D02*X226508D01*
X221610Y141685D02*X226508D01*
X221610Y143653D02*X226508D01*
X221610Y145622D02*X226508D01*
X215122Y157008D02*Y152110D01*
X213154Y157008D02*Y152110D01*
X211185Y157008D02*Y152110D01*
X209217Y157008D02*Y152110D01*
X207248Y157008D02*Y152110D01*
X205280Y157008D02*Y152110D01*
X203311Y157008D02*Y152110D01*
X201343Y157008D02*Y152110D01*
X199374Y157008D02*Y152110D01*
X197406Y157008D02*Y152110D01*
X195437Y157008D02*Y152110D01*
X193469Y157008D02*Y152110D01*
X191500Y157008D02*Y152110D01*
X189532Y157008D02*Y152110D01*
X187563Y157008D02*Y152110D01*
X185595Y157008D02*Y152110D01*
X183626Y157008D02*Y152110D01*
X181658Y157008D02*Y152110D01*
X179689Y157008D02*Y152110D01*
X177721Y157008D02*Y152110D01*
X175752Y157008D02*Y152110D01*
X173784Y157008D02*Y152110D01*
X171815Y157008D02*Y152110D01*
X169847Y157008D02*Y152110D01*
X167878Y157008D02*Y152110D01*
G54D107*G36*
X191516Y165922D02*Y163952D01*
X193484D01*
Y165922D01*
X191516D01*
G37*
G36*
Y161984D02*Y160016D01*
X193484D01*
Y161984D01*
X191516D01*
G37*
G36*
X160016Y153484D02*Y151516D01*
X161984D01*
Y153484D01*
X160016D01*
G37*
G36*
Y157422D02*Y155452D01*
X161984D01*
Y157422D01*
X160016D01*
G37*
G36*
X221016D02*Y155452D01*
X222984D01*
Y157422D01*
X221016D01*
G37*
G36*
Y153484D02*Y151516D01*
X222984D01*
Y153484D01*
X221016D01*
G37*
G36*
Y92484D02*Y90516D01*
X222984D01*
Y92484D01*
X221016D01*
G37*
G36*
Y88548D02*Y86578D01*
X222984D01*
Y88548D01*
X221016D01*
G37*
G36*
X152516Y210984D02*Y209016D01*
X154484D01*
Y210984D01*
X152516D01*
G37*
G36*
Y207048D02*Y205078D01*
X154484D01*
Y207048D01*
X152516D01*
G37*
G36*
X292016Y209422D02*Y207452D01*
X293984D01*
Y209422D01*
X292016D01*
G37*
G36*
Y205484D02*Y203516D01*
X293984D01*
Y205484D01*
X292016D01*
G37*
G36*
X160016Y92422D02*Y90452D01*
X161984D01*
Y92422D01*
X160016D01*
G37*
G36*
Y88484D02*Y86516D01*
X161984D01*
Y88484D01*
X160016D01*
G37*
G36*
X279516Y16984D02*Y15016D01*
X281484D01*
Y16984D01*
X279516D01*
G37*
G36*
X275578D02*Y15016D01*
X277548D01*
Y16984D01*
X275578D01*
G37*
G36*
X229516Y130421D02*Y128453D01*
X231484D01*
Y130421D01*
X229516D01*
G37*
G36*
Y126484D02*Y124516D01*
X231484D01*
Y126484D01*
X229516D01*
G37*
G36*
X195952Y72984D02*Y71016D01*
X197922D01*
Y72984D01*
X195952D01*
G37*
G36*
X192016D02*Y71016D01*
X193984D01*
Y72984D01*
X192016D01*
G37*
G36*
X235088Y130349D02*Y128380D01*
X237056D01*
Y130349D01*
X235088D01*
G37*
G36*
Y126412D02*Y124444D01*
X237056D01*
Y126412D01*
X235088D01*
G37*
G36*
X197516Y78484D02*Y76516D01*
X199484D01*
Y78484D01*
X197516D01*
G37*
G36*
Y82422D02*Y80452D01*
X199484D01*
Y82422D01*
X197516D01*
G37*
G36*
X229516Y117547D02*Y115579D01*
X231484D01*
Y117547D01*
X229516D01*
G37*
G36*
Y121484D02*Y119516D01*
X231484D01*
Y121484D01*
X229516D01*
G37*
G54D104*X338800Y194500D02*X340200D01*
X338800Y202500D02*X340200D01*
X73800Y230000D02*X75200D01*
X73800Y222000D02*X75200D01*
X305300Y266000D02*X306700D01*
X305300Y258000D02*X306700D01*
G54D107*G36*
X230516Y210984D02*Y209016D01*
X232484D01*
Y210984D01*
X230516D01*
G37*
G36*
Y207048D02*Y205078D01*
X232484D01*
Y207048D01*
X230516D01*
G37*
G54D105*X226000Y226000D02*Y219500D01*
X221000Y226000D02*Y219500D01*
X216000Y226000D02*Y219500D01*
X211000Y226000D02*Y219500D01*
X206000Y226000D02*Y219500D01*
X201000Y226000D02*Y219500D01*
X196000Y226000D02*Y219500D01*
Y205500D02*Y199000D01*
X201000Y205500D02*Y199000D01*
X206000Y205500D02*Y199000D01*
X211000Y205500D02*Y199000D01*
X216000Y205500D02*Y199000D01*
X221000Y205500D02*Y199000D01*
X226000Y205500D02*Y199000D01*
G54D104*X135000Y155200D02*Y153800D01*
X143000Y155200D02*Y153800D01*
X314300Y100000D02*X315700D01*
X314300Y108000D02*X315700D01*
G54D107*G36*
X339750Y148250D02*Y136750D01*
X351250D01*
Y148250D01*
X339750D01*
G37*
G36*
X324750D02*Y136750D01*
X336250D01*
Y148250D01*
X324750D01*
G37*
G36*
X339750Y133250D02*Y121750D01*
X351250D01*
Y133250D01*
X339750D01*
G37*
G36*
X324750D02*Y121750D01*
X336250D01*
Y133250D01*
X324750D01*
G37*
G54D108*X347000Y111500D02*Y106000D01*
X329000Y111500D02*Y106000D01*
G54D104*X168500Y64200D02*Y62800D01*
X176500Y64200D02*Y62800D01*
X168439Y74952D02*Y73552D01*
X176439Y74952D02*Y73552D01*
G54D109*X172725Y18902D02*Y15162D01*
X177843Y18902D02*Y15162D01*
X167607Y18902D02*Y15162D01*
X175284Y18902D02*Y15162D01*
X170166Y18902D02*Y15162D01*
G54D110*X159536Y16540D02*X161504D01*
X183945D02*X185914D01*
G54D111*X157764Y6697D02*Y6303D01*
G54D107*G36*
X164260Y10240D02*Y2760D01*
X171740D01*
Y10240D01*
X164260D01*
G37*
G36*
X173709D02*Y2760D01*
X181189D01*
Y10240D01*
X173709D01*
G37*
G54D111*X187685Y6697D02*Y6303D01*
G54D112*X157000Y34000D02*Y33000D01*
X145000Y34000D02*Y33000D01*
X20500Y321000D02*X21500D01*
X20500Y309000D02*X21500D01*
G54D104*X343800Y71500D02*X345200D01*
X343800Y79500D02*X345200D01*
X333300Y71500D02*X334700D01*
X333300Y79500D02*X334700D01*
X322800Y71500D02*X324200D01*
X322800Y79500D02*X324200D01*
X240500Y74700D02*Y73300D01*
X232500Y74700D02*Y73300D01*
X312300Y71500D02*X313700D01*
X312300Y79500D02*X313700D01*
X301300Y71500D02*X302700D01*
X301300Y79500D02*X302700D01*
X290300Y71500D02*X291700D01*
X290300Y79500D02*X291700D01*
X287500Y169700D02*Y168300D01*
X279500Y169700D02*Y168300D01*
G54D107*G36*
X192016Y78484D02*Y76516D01*
X193984D01*
Y78484D01*
X192016D01*
G37*
G36*
Y82422D02*Y80452D01*
X193984D01*
Y82422D01*
X192016D01*
G37*
G54D113*X251555Y23701D02*Y20945D01*
X247224Y25276D02*Y22520D01*
X242894Y23701D02*Y20945D01*
X238563Y22913D02*Y20157D01*
X234232Y23701D02*Y20945D01*
X229902Y22913D02*Y20157D01*
X225571Y23701D02*Y20945D01*
X221240Y23701D02*Y20945D01*
G54D114*X218091Y12283D02*Y10315D01*
X224390Y63071D02*X225965D01*
X246831D02*X248406D01*
X270453Y7953D02*Y5984D01*
G54D115*X124844Y85950D02*X132944D01*
X124844Y90950D02*X132944D01*
X124844Y95950D02*X132944D01*
X124844Y100950D02*X132944D01*
X124844Y105950D02*X132944D01*
X108844Y85950D02*X116944D01*
X108844Y90950D02*X116944D01*
X108844Y95950D02*X116944D01*
X108844Y100950D02*X116944D01*
X108844Y105950D02*X116944D01*
G54D104*X361800Y99000D02*X363200D01*
X361800Y107000D02*X363200D01*
G54D107*G36*
X340250Y260750D02*Y249250D01*
X351750D01*
Y260750D01*
X340250D01*
G37*
G36*
X325250D02*Y249250D01*
X336750D01*
Y260750D01*
X325250D01*
G37*
G36*
X340250Y245750D02*Y234250D01*
X351750D01*
Y245750D01*
X340250D01*
G37*
G36*
X325250D02*Y234250D01*
X336750D01*
Y245750D01*
X325250D01*
G37*
G54D108*X347500Y224000D02*Y218500D01*
X329500Y224000D02*Y218500D01*
G54D116*X127607Y56000D02*X128394D01*
X144536D02*X145323D01*
X76106Y309000D02*X76893D01*
X59177D02*X59964D01*
X20500Y234894D02*Y234107D01*
Y251823D02*Y251036D01*
M02*

23
hardware/scsi2sd.bom Normal file
View File

@ -0,0 +1,23 @@
.START
..device value footprint quantity refdes
7406 unknown SO14 3 U3 U4 U5
CAPACITOR 100nF cap_0402 11 C10 C11 C17 C19 C21 C22 C23 C24 C28 C3 C9
CAPACITOR 10uF SMD_SIMPLE 80 50 8 C1 C12 C13 C14 C2 C4 C5 C7
CAPACITOR 1uF cap_0402 4 C20 C26 C27 C8
CY8C53 unknown TQFP100_14 1 U1
DIODE unknown diode-DO-214AA-SMB 3 D1 D2 D3
FUSE 1.5A Hold SMD_SIMPLE 120 60 1 F1
FUSE 500mA Hold SMD_SIMPLE 120 60 1 F2
HEADER10 unknown FTSH-105-01-L-DV-K 1 J4
HEADER50 unknown HEADER50_2_RA 1 J2
JUMPER unknown HEADER2_2 1 J3
LD1117 unknown DPAK 2 U2 U6
LED unknown SMD_DIODE 80 50 1 LED1
MOLEX8981 unknown MOLEX8981 1 J1
RESISTOR 10K SMD_SIMPLE 80 50 7 R10 R11 R12 R6 R7 R8 R9
RESISTOR 1600 SMD_SIMPLE 80 50 1 R3
RESISTOR 22Ω SMD_SIMPLE 80 50 2 R4 R5
RESISTORPACK_10 unknown SIP10 2 R1 R2
USB unknown fci-10118192-0001LF 1 J5
wurth-693071010811 unknown wurth-microsd 1 J6
.END

434
hardware/scsi2sd.cmd Normal file
View File

@ -0,0 +1,434 @@
# Pin name action command file
# Start of element J6
ChangePinName(J6, 10, \_CD\_)
ChangePinName(J6, 9, GND)
ChangePinName(J6, 8, DAT1)
ChangePinName(J6, 7, DAT0)
ChangePinName(J6, 6, GND)
ChangePinName(J6, 5, CLK)
ChangePinName(J6, 4, Vcc)
ChangePinName(J6, 3, CMD)
ChangePinName(J6, 2, DAT3)
ChangePinName(J6, 1, DAT2)
# Start of element R2
ChangePinName(R2, 10, 10)
ChangePinName(R2, 9, 9)
ChangePinName(R2, 8, 8)
ChangePinName(R2, 7, 7)
ChangePinName(R2, 6, 6)
ChangePinName(R2, 1, 1)
ChangePinName(R2, 5, 5)
ChangePinName(R2, 4, 4)
ChangePinName(R2, 3, 3)
ChangePinName(R2, 2, 2)
# Start of element R1
ChangePinName(R1, 10, 10)
ChangePinName(R1, 9, 9)
ChangePinName(R1, 8, 8)
ChangePinName(R1, 7, 7)
ChangePinName(R1, 6, 6)
ChangePinName(R1, 1, 1)
ChangePinName(R1, 5, 5)
ChangePinName(R1, 4, 4)
ChangePinName(R1, 3, 3)
ChangePinName(R1, 2, 2)
# Start of element R5
ChangePinName(R5, 1, 1)
ChangePinName(R5, 2, 2)
# Start of element R4
ChangePinName(R4, 1, 1)
ChangePinName(R4, 2, 2)
# Start of element J5
ChangePinName(J5, 5, GND)
ChangePinName(J5, 1, VCC)
ChangePinName(J5, 2, D-)
ChangePinName(J5, 3, D+)
ChangePinName(J5, 4, ID)
# Start of element D3
ChangePinName(D3, 1, cathode)
ChangePinName(D3, 2, anode)
# Start of element F2
ChangePinName(F2, 2, 2)
ChangePinName(F2, 1, 1)
# Start of element F1
ChangePinName(F1, 2, 2)
ChangePinName(F1, 1, 1)
# Start of element D1
ChangePinName(D1, 1, cathode)
ChangePinName(D1, 2, anode)
# Start of element D2
ChangePinName(D2, 1, cathode)
ChangePinName(D2, 2, anode)
# Start of element J3
ChangePinName(J3, 1, 1)
ChangePinName(J3, 2, 2)
# Start of element C14
ChangePinName(C14, 2, 2)
ChangePinName(C14, 1, 1)
# Start of element C4
ChangePinName(C4, 2, 2)
ChangePinName(C4, 1, 1)
# Start of element C7
ChangePinName(C7, 2, 2)
ChangePinName(C7, 1, 1)
# Start of element U6
ChangePinName(U6, 3, IN)
ChangePinName(U6, 2, OUT)
ChangePinName(U6, 1, GND)
# Start of element U2
ChangePinName(U2, 3, IN)
ChangePinName(U2, 2, OUT)
ChangePinName(U2, 1, GND)
# Start of element C12
ChangePinName(C12, 2, 2)
ChangePinName(C12, 1, 1)
# Start of element C13
ChangePinName(C13, 2, 2)
ChangePinName(C13, 1, 1)
# Start of element C5
ChangePinName(C5, 2, 2)
ChangePinName(C5, 1, 1)
# Start of element C8
ChangePinName(C8, 2, 2)
ChangePinName(C8, 1, 1)
# Start of element U1
ChangePinName(U1, 76, P0[4])
ChangePinName(U1, 77, P0[5])
ChangePinName(U1, 78, P0[6])
ChangePinName(U1, 79, P0[7])
ChangePinName(U1, 80, P4[2])
ChangePinName(U1, 81, P4[3])
ChangePinName(U1, 82, P4[4])
ChangePinName(U1, 83, P4[5])
ChangePinName(U1, 84, P4[6])
ChangePinName(U1, 85, P4[7])
ChangePinName(U1, 86, VCCD)
ChangePinName(U1, 87, VSSD)
ChangePinName(U1, 88, VDDD)
ChangePinName(U1, 89, P6[0])
ChangePinName(U1, 90, P6[1])
ChangePinName(U1, 91, P6[2])
ChangePinName(U1, 92, P6[3])
ChangePinName(U1, 93, P15[4])
ChangePinName(U1, 94, P15[5])
ChangePinName(U1, 95, P2[0])
ChangePinName(U1, 96, P2[1])
ChangePinName(U1, 97, P2[2])
ChangePinName(U1, 98, P2[3])
ChangePinName(U1, 99, P2[4])
ChangePinName(U1, 100, VDDIO2)
ChangePinName(U1, 51, P3[6])
ChangePinName(U1, 52, P3[7])
ChangePinName(U1, 53, P12[0])
ChangePinName(U1, 54, P12[1])
ChangePinName(U1, 55, "XO XTAL P15[2],KHZ")
ChangePinName(U1, 56, "XI XTAL P15[3],KHZ")
ChangePinName(U1, 57, NC)
ChangePinName(U1, 58, NC)
ChangePinName(U1, 59, NC)
ChangePinName(U1, 60, NC)
ChangePinName(U1, 61, NC)
ChangePinName(U1, 62, NC)
ChangePinName(U1, 63, VCCA)
ChangePinName(U1, 64, VSSA)
ChangePinName(U1, 65, VDDA)
ChangePinName(U1, 66, VSSD)
ChangePinName(U1, 67, P12[2])
ChangePinName(U1, 68, P12[3])
ChangePinName(U1, 69, P4[0])
ChangePinName(U1, 70, P4[1])
ChangePinName(U1, 71, P0[0])
ChangePinName(U1, 72, P0[1])
ChangePinName(U1, 73, P0[2])
ChangePinName(U1, 74, P0[3])
ChangePinName(U1, 75, VDDIO0)
ChangePinName(U1, 50, VDDIO3)
ChangePinName(U1, 49, P3[5])
ChangePinName(U1, 48, P3[4])
ChangePinName(U1, 47, P3[3])
ChangePinName(U1, 46, P3[2])
ChangePinName(U1, 45, P3[1])
ChangePinName(U1, 44, P3[0])
ChangePinName(U1, 43, MHZ XTAL XI)
ChangePinName(U1, 42, MHZ XTAL XO)
ChangePinName(U1, 41, NC)
ChangePinName(U1, 40, NC)
ChangePinName(U1, 39, VCCD)
ChangePinName(U1, 38, VSSD)
ChangePinName(U1, 37, VDDD)
ChangePinName(U1, 36, "SWDCK,USB D-")
ChangePinName(U1, 35, "SWDIO,USB D+")
ChangePinName(U1, 34, P5[7])
ChangePinName(U1, 33, P5[6])
ChangePinName(U1, 32, P5[5])
ChangePinName(U1, 31, P5[4])
ChangePinName(U1, 30, P12[7])
ChangePinName(U1, 29, P12[6])
ChangePinName(U1, 28, P1[7])
ChangePinName(U1, 27, P1[6])
ChangePinName(U1, 26, VDDIO1)
ChangePinName(U1, 25, P1[5])
ChangePinName(U1, 24, P1[4])
ChangePinName(U1, 23, "SWV,P1[3]")
ChangePinName(U1, 22, P1[2])
ChangePinName(U1, 21, "SWDCK,P1[1]")
ChangePinName(U1, 20, "SWDIO,P1[0]")
ChangePinName(U1, 19, P5[3])
ChangePinName(U1, 18, P5[2])
ChangePinName(U1, 17, P5[1])
ChangePinName(U1, 16, P5[0])
ChangePinName(U1, 15, \_XRES\_)
ChangePinName(U1, 14, VSSD)
ChangePinName(U1, 13, VSSD)
ChangePinName(U1, 12, VSSD)
ChangePinName(U1, 11, NC)
ChangePinName(U1, 10, VSSD)
ChangePinName(U1, 9, P6[7])
ChangePinName(U1, 8, P6[6])
ChangePinName(U1, 7, P6[5])
ChangePinName(U1, 6, P6[4])
ChangePinName(U1, 5, P12[5])
ChangePinName(U1, 4, P12[4])
ChangePinName(U1, 3, P2[7])
ChangePinName(U1, 2, P2[6])
ChangePinName(U1, 1, P2[5])
# Start of element R12
ChangePinName(R12, 1, 1)
ChangePinName(R12, 2, 2)
# Start of element R11
ChangePinName(R11, 1, 1)
ChangePinName(R11, 2, 2)
# Start of element R10
ChangePinName(R10, 1, 1)
ChangePinName(R10, 2, 2)
# Start of element R9
ChangePinName(R9, 1, 1)
ChangePinName(R9, 2, 2)
# Start of element R8
ChangePinName(R8, 1, 1)
ChangePinName(R8, 2, 2)
# Start of element R7
ChangePinName(R7, 1, 1)
ChangePinName(R7, 2, 2)
# Start of element R6
ChangePinName(R6, 1, 1)
ChangePinName(R6, 2, 2)
# Start of element C26
ChangePinName(C26, 2, 2)
ChangePinName(C26, 1, 1)
# Start of element C20
ChangePinName(C20, 2, 2)
ChangePinName(C20, 1, 1)
# Start of element C27
ChangePinName(C27, 2, 2)
ChangePinName(C27, 1, 1)
# Start of element C19
ChangePinName(C19, 2, 2)
ChangePinName(C19, 1, 1)
# Start of element C24
ChangePinName(C24, 2, 2)
ChangePinName(C24, 1, 1)
# Start of element C23
ChangePinName(C23, 2, 2)
ChangePinName(C23, 1, 1)
# Start of element C17
ChangePinName(C17, 2, 2)
ChangePinName(C17, 1, 1)
# Start of element C21
ChangePinName(C21, 2, 2)
ChangePinName(C21, 1, 1)
# Start of element C28
ChangePinName(C28, 2, 2)
ChangePinName(C28, 1, 1)
# Start of element R3
ChangePinName(R3, 1, 1)
ChangePinName(R3, 2, 2)
# Start of element LED1
ChangePinName(LED1, 2, K)
ChangePinName(LED1, 1, A)
# Start of element C11
ChangePinName(C11, 2, 2)
ChangePinName(C11, 1, 1)
# Start of element C10
ChangePinName(C10, 2, 2)
ChangePinName(C10, 1, 1)
# Start of element C3
ChangePinName(C3, 2, 2)
ChangePinName(C3, 1, 1)
# Start of element C9
ChangePinName(C9, 2, 2)
ChangePinName(C9, 1, 1)
# Start of element J4
ChangePinName(J4, 6, 6)
ChangePinName(J4, 7, 7)
ChangePinName(J4, 8, 8)
ChangePinName(J4, 9, 9)
ChangePinName(J4, 10, 10)
ChangePinName(J4, 5, 5)
ChangePinName(J4, 1, 1)
ChangePinName(J4, 4, 4)
ChangePinName(J4, 3, 3)
ChangePinName(J4, 2, 2)
# Start of element C1
ChangePinName(C1, 2, 2)
ChangePinName(C1, 1, 1)
# Start of element U5
ChangePinName(U5, 8, \_Y3\_)
ChangePinName(U5, 9, A3)
ChangePinName(U5, 10, \_Y4\_)
ChangePinName(U5, 11, A4)
ChangePinName(U5, 12, \_Y5\_)
ChangePinName(U5, 13, A5)
ChangePinName(U5, 14, Vcc)
ChangePinName(U5, 7, GND)
ChangePinName(U5, 6, \_Y2\_)
ChangePinName(U5, 5, A2)
ChangePinName(U5, 4, \_Y1\_)
ChangePinName(U5, 3, A1)
ChangePinName(U5, 2, \_Y0\_)
ChangePinName(U5, 1, A0)
# Start of element U4
ChangePinName(U4, 8, \_Y3\_)
ChangePinName(U4, 9, A3)
ChangePinName(U4, 10, \_Y4\_)
ChangePinName(U4, 11, A4)
ChangePinName(U4, 12, \_Y5\_)
ChangePinName(U4, 13, A5)
ChangePinName(U4, 14, Vcc)
ChangePinName(U4, 7, GND)
ChangePinName(U4, 6, \_Y2\_)
ChangePinName(U4, 5, A2)
ChangePinName(U4, 4, \_Y1\_)
ChangePinName(U4, 3, A1)
ChangePinName(U4, 2, \_Y0\_)
ChangePinName(U4, 1, A0)
# Start of element U3
ChangePinName(U3, 8, \_Y3\_)
ChangePinName(U3, 9, A3)
ChangePinName(U3, 10, \_Y4\_)
ChangePinName(U3, 11, A4)
ChangePinName(U3, 12, \_Y5\_)
ChangePinName(U3, 13, A5)
ChangePinName(U3, 14, Vcc)
ChangePinName(U3, 7, GND)
ChangePinName(U3, 6, \_Y2\_)
ChangePinName(U3, 5, A2)
ChangePinName(U3, 4, \_Y1\_)
ChangePinName(U3, 3, A1)
ChangePinName(U3, 2, \_Y0\_)
ChangePinName(U3, 1, A0)
# Start of element C2
ChangePinName(C2, 2, 2)
ChangePinName(C2, 1, 1)
# Start of element C22
ChangePinName(C22, 2, 2)
ChangePinName(C22, 1, 1)
# Start of element J1
ChangePinName(J1, 4, +5V)
ChangePinName(J1, 3, GND)
ChangePinName(J1, 2, GND)
ChangePinName(J1, 1, +12V)
# Start of element J2
ChangePinName(J2, 50, 50)
ChangePinName(J2, 49, 49)
ChangePinName(J2, 48, 48)
ChangePinName(J2, 47, 47)
ChangePinName(J2, 46, 46)
ChangePinName(J2, 45, 45)
ChangePinName(J2, 44, 44)
ChangePinName(J2, 43, 43)
ChangePinName(J2, 42, 42)
ChangePinName(J2, 41, 41)
ChangePinName(J2, 40, 40)
ChangePinName(J2, 39, 39)
ChangePinName(J2, 38, 38)
ChangePinName(J2, 37, 37)
ChangePinName(J2, 36, 36)
ChangePinName(J2, 35, 35)
ChangePinName(J2, 34, 34)
ChangePinName(J2, 33, 33)
ChangePinName(J2, 32, 32)
ChangePinName(J2, 31, 31)
ChangePinName(J2, 30, 30)
ChangePinName(J2, 29, 29)
ChangePinName(J2, 28, 28)
ChangePinName(J2, 27, 27)
ChangePinName(J2, 26, 26)
ChangePinName(J2, 25, 25)
ChangePinName(J2, 24, 24)
ChangePinName(J2, 23, 23)
ChangePinName(J2, 22, 22)
ChangePinName(J2, 21, 21)
ChangePinName(J2, 20, 20)
ChangePinName(J2, 19, 19)
ChangePinName(J2, 18, 18)
ChangePinName(J2, 17, 17)
ChangePinName(J2, 16, 16)
ChangePinName(J2, 15, 15)
ChangePinName(J2, 14, 14)
ChangePinName(J2, 13, 13)
ChangePinName(J2, 12, 12)
ChangePinName(J2, 11, 11)
ChangePinName(J2, 10, 10)
ChangePinName(J2, 9, 9)
ChangePinName(J2, 8, 8)
ChangePinName(J2, 7, 7)
ChangePinName(J2, 6, 6)
ChangePinName(J2, 5, 5)
ChangePinName(J2, 4, 4)
ChangePinName(J2, 3, 3)
ChangePinName(J2, 2, 2)
ChangePinName(J2, 1, 1)

77
hardware/scsi2sd.net Normal file
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unnamed_net28 R5-1 J5-2
unnamed_net27 R4-1 J5-3
unnamed_net26 J5-4
unnamed_net25 D3-2 F2-2
unnamed_net24 J5-1 F2-1
unnamed_net23 D1-2 J3-1
drive_5V F1-2 D2-2 J3-2
unnamed_net22 R1-1 R2-1 C14-2 C7-2 U2-2
unnamed_net21 U1-55
unnamed_net20 U1-42
unnamed_net19 R5-2 U1-36
unnamed_net18 R4-2 U1-35
unnamed_net17 U1-25
unnamed_net16 U1-24
unnamed_net15 U1-22
unnamed_net14 U1-11
SD_DAT2 J6-1 U1-49 R12-1
\_SD_CS\_ J6-2 U1-48 R11-1
SD_MOSI J6-3 U1-47 R10-1
\_SD_CD\_ J6-10 U1-51 R9-1
SD_SCK J6-5 U1-46 R8-1
SD_MISO J6-7 U1-45 R7-1
SD_DAT1 J6-8 U1-44 R6-1
unnamed_net13 U1-86 U1-39 C20-2
unnamed_net12 U1-63 C27-2
unnamed_net11 U1-68 LED1-2
unnamed_net10 R3-1 LED1-1
unnamed_net9 U1-23 J4-6
unnamed_net8 J4-8
unnamed_net7 U1-15 J4-10
unnamed_net6 U1-21 J4-4
unnamed_net5 U1-20 J4-2
DB0 U1-92 U5-9
DB2 U1-90 U5-11
DB4 U1-85 U5-13
DB1 U1-91 U5-5
DB3 U1-89 U5-3
DB5 U1-84 U5-1
DB6 U1-83 U4-9
DBP U1-81 U4-11
BSY U1-79 U4-13
DB7 U1-82 U4-5
ATN U1-80 U4-3
ACK U1-78 U4-1
RST U1-77 U3-9
SEL U1-74 U3-11
REQ U1-72 U3-13
MSG U1-76 U3-5
C/D U1-73 U3-3
I/O U1-71 U3-1
5V D3-1 U6-3 C12-2 C26-2 U1-65 C24-2 U1-88 C8-2 C19-2 U1-37 C23-2 U1-100 C17-2 U1-75 C21-2 R3-2 U1-26 C9-2 J4-1 C11-2 U5-14 C10-2 U4-14 C3-2 U3-14 D2-1 C4-2 C2-2
3.3V U6-2 C13-2 R12-2 R11-2 R10-2 R9-2 R8-2 R7-2 R6-2 U1-50 C28-2 J6-4 C22-2
unnamed_net4 F1-1 J1-4
unnamed_net3 J1-1
\_I/O\_ R2-2 U1-19 U3-2 J2-50
\_REQ\_ R2-3 U1-18 U3-12 J2-48
\_C/D\_ R2-4 U1-17 U3-4 J2-46
\_SEL\_ R2-5 U1-16 U3-10 J2-44
\_MSG\_ R2-6 U1-9 U3-6 J2-42
\_RST\_ R2-7 U1-8 U3-8 J2-40
\_ACK\_ R2-8 U1-7 U4-2 J2-38
\_BSY\_ R2-9 U1-6 U4-12 J2-36
\_ATN\_ R2-10 U1-5 U4-4 J2-32
unnamed_net2 D1-1 U2-3 C5-2 C1-2 J2-26
unnamed_net1 J2-25
\_DBP\_ R1-2 U1-95 U4-10 J2-18
\_DB7\_ R1-3 U1-96 U4-6 J2-16
\_DB6\_ R1-4 U1-97 U4-8 J2-14
\_DB5\_ R1-5 U1-98 U5-2 J2-12
\_DB4\_ R1-6 U1-99 U5-12 J2-10
\_DB3\_ R1-7 U1-1 U5-4 J2-8
\_DB2\_ R1-8 U1-2 U5-10 J2-6
\_DB1\_ R1-9 U1-3 U5-6 J2-4
\_DB0\_ R1-10 U1-4 U5-8 J2-2
GND J6-9 J6-6 J5-5 C14-1 C4-1 C7-1 U6-1 U2-1 C12-1 C13-1 C5-1 C8-1 U1-87 U1-93 U1-94 U1-52 U1-53 U1-54 U1-56 U1-57 U1-58 U1-59 U1-60 U1-61 U1-62 U1-64 U1-66 U1-67 U1-69 U1-70 U1-43 U1-41 U1-40 U1-38 \
U1-34 U1-33 U1-32 U1-31 U1-30 U1-29 U1-28 U1-27 U1-14 U1-13 U1-12 U1-10 C26-1 C20-1 C27-1 C19-1 C24-1 C23-1 C17-1 C21-1 C28-1 C11-1 C10-1 C3-1 C9-1 J4-7 J4-9 J4-5 J4-3 C1-1 U5-7 U4-7 U3-7 C2-1 C22-1 \
J1-3 J1-2 J2-34 J2-30 J2-28 J2-22 J2-24 J2-20 J2-49 J2-47 J2-45 J2-43 J2-41 J2-39 J2-37 J2-35 J2-33 J2-31 J2-29 J2-27 J2-19 J2-17 J2-15 J2-13 J2-11 J2-9 J2-7 J2-5 J2-3 J2-23 J2-21 J2-1

3874
hardware/scsi2sd.pcb Normal file
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2458
hardware/scsi2sd.sch Normal file
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176
hardware/symbols/7406.sym Normal file
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@ -0,0 +1,176 @@
v 20060113 1
P 100 2900 400 2900 1 0 0
{
T 300 2950 5 8 1 1 0 6 1
pinnumber=1
T 300 2850 5 8 0 1 0 8 1
pinseq=1
T 450 2900 9 8 1 1 0 0 1
pinlabel=A0
T 450 2900 5 8 0 1 0 2 1
pintype=in
}
P 100 2500 400 2500 1 0 0
{
T 300 2550 5 8 1 1 0 6 1
pinnumber=2
T 300 2450 5 8 0 1 0 8 1
pinseq=2
T 450 2500 9 8 1 1 0 0 1
pinlabel=\_Y0\_
T 450 2500 5 8 0 1 0 2 1
pintype=out
}
P 100 2100 400 2100 1 0 0
{
T 300 2150 5 8 1 1 0 6 1
pinnumber=3
T 300 2050 5 8 0 1 0 8 1
pinseq=3
T 450 2100 9 8 1 1 0 0 1
pinlabel=A1
T 450 2100 5 8 0 1 0 2 1
pintype=in
}
P 100 1700 400 1700 1 0 0
{
T 300 1750 5 8 1 1 0 6 1
pinnumber=4
T 300 1650 5 8 0 1 0 8 1
pinseq=4
T 450 1700 9 8 1 1 0 0 1
pinlabel=\_Y1\_
T 450 1700 5 8 0 1 0 2 1
pintype=out
}
P 100 1300 400 1300 1 0 0
{
T 300 1350 5 8 1 1 0 6 1
pinnumber=5
T 300 1250 5 8 0 1 0 8 1
pinseq=5
T 450 1300 9 8 1 1 0 0 1
pinlabel=A2
T 450 1300 5 8 0 1 0 2 1
pintype=in
}
P 100 900 400 900 1 0 0
{
T 300 950 5 8 1 1 0 6 1
pinnumber=6
T 300 850 5 8 0 1 0 8 1
pinseq=6
T 450 900 9 8 1 1 0 0 1
pinlabel=\_Y2\_
T 450 900 5 8 0 1 0 2 1
pintype=out
}
P 100 500 400 500 1 0 0
{
T 300 550 5 8 1 1 0 6 1
pinnumber=7
T 300 450 5 8 0 1 0 8 1
pinseq=7
T 450 500 9 8 1 1 0 0 1
pinlabel=GND
T 450 500 5 8 0 1 0 2 1
pintype=pwr
}
P 1700 2900 1400 2900 1 0 0
{
T 1500 2950 5 8 1 1 0 0 1
pinnumber=14
T 1500 2850 5 8 0 1 0 2 1
pinseq=8
T 1350 2900 9 8 1 1 0 6 1
pinlabel=Vcc
T 1350 2900 5 8 0 1 0 8 1
pintype=pwr
}
P 1700 2500 1400 2500 1 0 0
{
T 1500 2550 5 8 1 1 0 0 1
pinnumber=13
T 1500 2450 5 8 0 1 0 2 1
pinseq=9
T 1350 2500 9 8 1 1 0 6 1
pinlabel=A5
T 1350 2500 5 8 0 1 0 8 1
pintype=in
}
P 1700 2100 1400 2100 1 0 0
{
T 1500 2150 5 8 1 1 0 0 1
pinnumber=12
T 1500 2050 5 8 0 1 0 2 1
pinseq=10
T 1350 2100 9 8 1 1 0 6 1
pinlabel=\_Y5\_
T 1350 2100 5 8 0 1 0 8 1
pintype=out
}
P 1700 1700 1400 1700 1 0 0
{
T 1500 1750 5 8 1 1 0 0 1
pinnumber=11
T 1500 1650 5 8 0 1 0 2 1
pinseq=11
T 1350 1700 9 8 1 1 0 6 1
pinlabel=A4
T 1350 1700 5 8 0 1 0 8 1
pintype=in
}
P 1700 1300 1400 1300 1 0 0
{
T 1500 1350 5 8 1 1 0 0 1
pinnumber=10
T 1500 1250 5 8 0 1 0 2 1
pinseq=12
T 1350 1300 9 8 1 1 0 6 1
pinlabel=\_Y4\_
T 1350 1300 5 8 0 1 0 8 1
pintype=out
}
P 1700 900 1400 900 1 0 0
{
T 1500 950 5 8 1 1 0 0 1
pinnumber=9
T 1500 850 5 8 0 1 0 2 1
pinseq=13
T 1350 900 9 8 1 1 0 6 1
pinlabel=A3
T 1350 900 5 8 0 1 0 8 1
pintype=in
}
P 1700 500 1400 500 1 0 0
{
T 1500 550 5 8 1 1 0 0 1
pinnumber=8
T 1500 450 5 8 0 1 0 2 1
pinseq=14
T 1350 500 9 8 1 1 0 6 1
pinlabel=\_Y3\_
T 1350 500 5 8 0 1 0 8 1
pintype=out
}
B 400 100 1000 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1400 3400 8 10 1 1 0 6 1
refdes=U?
T 400 3400 9 10 1 0 0 0 1
7406
T 400 3600 5 10 0 0 0 0 1
device=7406
T 400 3800 5 10 0 0 0 0 1
footprint=SO14
T 400 4000 5 10 0 0 0 0 1
author=Michael McMaster <michael@codesrc.com>
T 400 4200 5 10 0 0 0 0 1
documentation=http://www.nxp.com/products/logic/buffers_inverters_drivers/N74F06D.html
T 400 4400 5 10 0 0 0 0 1
description=Hex Inverter (Open Drain)
T 400 4600 5 10 0 0 0 0 1
numslots=0
T 400 4800 5 10 0 0 0 0 1
dist-license=gpl3+
T 400 5000 5 10 0 0 0 0 1
use-license=gpl3+

74
hardware/symbols/7406.tragesym Normal file
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# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.
[options]
# wordswap swaps labels if the pin is on the right side an looks like this:
# "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
# this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
# useful for address ports, busses, ...
wordswap=yes
rotate_labels=yes
sort_labels=no
generate_pinseq=yes
sym_width=1000
pinwidthvertical=400
pinwidthhorizontal=400
[geda_attr]
# name will be printed in the top of the symbol
# name is only some graphical text, not an attribute
# version specifies a gschem version.
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=7406
device=7406
refdes=U?
footprint=SO14
description=Hex Inverter (Open Drain)
documentation=http://www.nxp.com/products/logic/buffers_inverters_drivers/N74F06D.html
author=Michael McMaster <michael@codesrc.com>
dist-license=gpl3+
use-license=gpl3+
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=
[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets.
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
# negation lines can be added with "\_" example: \_enable\_
# if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr seq type style posit. net label
#-----------------------------------------------------
1 in line l A0
2 out line l \_Y0\_
3 in line l A1
4 out line l \_Y1\_
5 in line l A2
6 out line l \_Y2\_
7 pwr line l GND GND
14 pwr line r Vcc
13 in line r A5
12 out line r \_Y5\_
11 in line r A4
10 out line r \_Y4\_
9 in line r A3
8 out line r \_Y3\_

1126
hardware/symbols/CY8C53.sym Normal file
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164
hardware/symbols/CY8C53.tragesym Normal file
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# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.
[options]
# wordswap swaps labels if the pin is on the right side an looks like this:
# "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
# this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
# useful for address ports, busses, ...
wordswap=yes
rotate_labels=yes
sort_labels=no
generate_pinseq=yes
sym_width=18000
pinwidthvertical=700
pinwidthhorizontal=700
[geda_attr]
# name will be printed in the top of the symbol
# name is only some graphical text, not an attribute
# version specifies a gschem version.
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=CY8C53
device=CY8C53
refdes=U?
footprint=TQFP100_14
description=Cypress PSoC5 CY8C53
documentation=http://www.cypress.com/?id=2233
author=Michael McMaster <michael@codesrc.com>
dist-license=gpl3+
use-license=gpl3+
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=
[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets.
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
# negation lines can be added with "\_" example: \_enable\_
# if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr seq type style posit. net label
#-----------------------------------------------------
1 io line l P2[5]
2 io line l P2[6]
3 io line l P2[7]
4 io line l P12[4]
5 io line l P12[5]
6 io line l P6[4]
7 io line l P6[5]
8 io line l P6[6]
9 io line l P6[7]
10 pwr line l GND VSSD
11 io line l NC
12 pwr line l GND VSSD
13 pwr line l GND VSSD
14 pwr line l GND VSSD
15 in line l \_XRES\_
16 io line l P5[0]
17 io line l P5[1]
18 io line l P5[2]
19 io line l P5[3]
20 io line l SWDIO,P1[0]
21 io line l SWDCK,P1[1]
22 io line l P1[2]
23 io line l SWV,P1[3]
24 io line l P1[4]
25 io line l P1[5]
26 pwr line b VDDIO1
27 io line b P1[6]
28 io line b P1[7]
29 io line b P12[6]
30 io line b P12[7]
31 io line b P5[4]
32 io line b P5[5]
33 io line b P5[6]
34 io line b P5[7]
35 io line b SWDIO,USB D+
36 io line b SWDCK,USB D-
37 pwr line b VDDD
38 pwr line b GND VSSD
39 pwr line b VCCD
40 io line b NC
41 io line b NC
42 clk clk b MHZ XTAL XO
43 clk clk b MHZ XTAL XI
44 io line b P3[0]
45 io line b P3[1]
46 io line b P3[2]
47 io line b P3[3]
48 io line b P3[4]
49 io line b P3[5]
50 pwr line b VDDIO3
75 pwr line r VDDIO0
74 io line r P0[3]
73 io line r P0[2]
72 io line r P0[1]
71 io line r P0[0]
70 io line r P4[1]
69 io line r P4[0]
68 io line r P12[3]
67 io line r P12[2]
66 pwr line r GND VSSD
65 pwr line r VDDA
64 pwr line r GND VSSA
63 pwr line r VCCA
62 io line r NC
61 io line r NC
60 io line r NC
59 io line r NC
58 io line r NC
57 io line r NC
56 io line r P15[3],KHZ XTAL XI
55 io line r P15[2],KHZ XTAL XO
54 io line r P12[1]
53 io line r P12[0]
52 io line r P3[7]
51 io line r P3[6]
100 pwr line t VDDIO2
99 io line t P2[4]
98 io line t P2[3]
97 io line t P2[2]
96 io line t P2[1]
95 io line t P2[0]
94 io line t P15[5]
93 io line t P15[4]
92 io line t P6[3]
91 io line t P6[2]
90 io line t P6[1]
89 io line t P6[0]
88 pwr line t VDDD
87 pwr line t GND VSSD
86 pwr line t VCCD
85 io line t P4[7]
84 io line t P4[6]
83 io line t P4[5]
82 io line t P4[4]
81 io line t P4[3]
80 io line t P4[2]
79 io line t P0[7]
78 io line t P0[6]
77 io line t P0[5]
76 io line t P0[4]

10
hardware/symbols/DO-41-vert.fp Normal file
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Element[0x00000000 "DIO__DO-41-vertical.fp" "D?" "" 172500 127500 -9900
6050 0 100 0x00000000]
(
Pin[-6200 0 9500 2000 10700 4200 "" "1" 0x0101]
Pin[6200 0 9500 2000 10700 4200 "" "2" 0x01]
ElementLine [-11450 -5300 6200 -5300 1000]
ElementLine [-11450 5300 6200 5300 1000]
ElementLine [-11450 -5300 -11450 5300 1000]
ElementArc [6200 0 5300 5300 90 180 1000]
)

10
hardware/symbols/DO-41.fp Normal file
View File

@ -0,0 +1,10 @@
Element[0x00000000 "DO-41" "D?" "" 172500 127500 -9900 6050 0 100 0x00000000]
(
Pin[-21250 0 9500 2000 10700 4200 "" "1" 0x0101]
Pin[21250 0 9500 2000 10700 4200 "" "2" 0x01]
ElementLine [-9850 -5050 9850 -5050 1000]
ElementLine [9850 -5050 9850 5050 1000]
ElementLine [9850 5050 -9850 5050 1000]
ElementLine [-9850 5050 -9850 -5050 1000]
ElementLine [-6800 -5050 -6800 5050 1000]
)

20
hardware/symbols/DPAK.fp Normal file
View File

@ -0,0 +1,20 @@
Element["" "" "" "" 12750 8250 0 0 0 100 ""]
(
Pad[8250 10750 8250 10750 26500 2000 27500 "2" "2" "square,nopaste"]
Pad[750 3250 750 3250 11500 2000 12500 "2_1" "2" "square"]
Pad[750 18250 750 18250 11500 2000 12500 "2_2" "2" "square"]
Pad[15750 3250 15750 3250 11500 2000 12500 "2_3" "2" "square,edge2"]
Pad[15750 18250 15750 18250 11500 2000 12500 "2_4" "2" "square,edge2"]
Pad[31750 1750 37250 1750 6500 2000 7500 "3" "3" "square,edge2"]
Pad[31750 19750 37250 19750 6500 2000 7500 "1" "1" "square,edge2"]
ElementLine [-7500 -5000 44500 -5000 1000]
ElementLine [44500 -5000 44500 26500 1000]
ElementLine [44500 26500 -7500 26500 1000]
ElementLine [-7500 26500 -7500 -5000 1000]
ElementLine [28500 10500 32500 10500 1000]
)

66
hardware/symbols/FCI-10067847.fp Normal file
View File

@ -0,0 +1,66 @@
Element["" "FCI SD Card 10067847" "" "" 88425 50698 0 0 0 100 ""]
(
Pin[-56138 64233 7906 2 6906 5906 "" "" ""]
Pin[39138 64233 7906 2 6906 5906 "" "" ""]
Pad[-62044 53997 -62044 57934 4724 2 4725 "GND_SHIELD" "12" "square,edge2"]
Pad[28311 -32027 28311 -30451 4330 2 4331 "PIN9" "9" "square"]
Pad[-60074 -32224 -60074 -30254 3937 2 3938 "WP" "10" "square"]
Pad[-46886 -32026 -46886 -30452 4331 2 4332 "PIN8" "8" "square"]
Pad[-40192 -32026 -40192 -30452 4331 2 4332 "PIN7" "7" "square"]
Pad[-30744 -32027 -30744 -30451 4330 2 4331 "PIN6" "6" "square"]
Pad[-20902 -32026 -20902 -30452 4331 2 4332 "PIN5" "5" "square"]
Pad[-11059 -32027 -11059 -30451 4330 2 4331 "PIN4" "4" "square"]
Pad[8626 -32027 8626 -30451 4330 2 4331 "PIN2" "2" "square"]
Pad[2130 -32224 2130 -30254 3937 2 3938 "CD" "11" "square"]
Pad[-4366 -32027 -4366 -30451 4330 2 4331 "PIN3" "3" "square"]
Pad[18468 -32026 18468 -30452 4331 2 4332 "PIN1" "1" "square"]
Pad[48193 49272 48193 53210 4724 2 4725 "GND_SHIELD" "13" "square,edge2"]
ElementLine [50162 -29074 50162 45730 800]
ElementLine [50162 83918 50162 56843 800]
ElementLine [-63666 50697 -63666 -29082 800]
ElementLine [-63666 83918 -63666 61701 800]
ElementLine [-56592 -29082 -50304 -29082 800]
ElementLine [31841 -29074 31833 -29082 800]
ElementLine [50162 -29074 31841 -29074 800]
ElementLine [50162 83918 -63618 83918 800]
ElementLine [-49051 -7814 30476 -7814 800]
ElementLine [30476 -7814 30476 12265 800]
ElementLine [30476 12265 -49051 12265 800]
ElementLine [-49051 12265 -49051 -7814 800]
ElementLine [-46767 -4716 -46767 10218 800]
ElementLine [-46767 10218 28296 10218 800]
ElementLine [28296 10218 28296 -5895 800]
ElementLine [28296 -5895 -44016 -5895 800]
ElementLine [-44016 -5895 -44016 7860 800]
ElementLine [-44016 7860 25545 7860 800]
ElementLine [25545 7860 25545 -3930 800]
ElementLine [25545 -3930 -41658 -3930 800]
ElementLine [-41658 -3930 -41658 5502 800]
ElementLine [-41658 5502 23187 5502 800]
ElementLine [23187 5502 23187 -1965 800]
ElementLine [23187 -1965 -38907 -1965 800]
ElementLine [-38907 -1965 -38907 3537 800]
ElementLine [-38907 3537 20829 3537 800]
ElementLine [20829 3537 20829 0 800]
ElementLine [20829 0 -36942 0 800]
ElementLine [-36942 0 -36942 1965 800]
ElementLine [-36942 1965 18471 1965 800]
ElementLine [18471 1965 18864 1572 800]
ElementLine [-66375 7146 -61650 7146 800]
ElementLine [-61650 7146 -61650 31782 800]
ElementLine [-61650 31782 -61701 31833 800]
ElementLine [-61701 31833 -66417 31833 800]
ElementLine [-66417 31833 -66417 7188 800]
ElementLine [-66417 7188 -66375 7146 800]
ElementLine [-65631 8253 -62487 11397 800]
ElementLine [-62487 11397 -65631 14541 800]
ElementLine [-65631 14541 -62487 17685 800]
ElementLine [-62487 17685 -65631 20829 800]
ElementLine [-65631 20829 -62487 23973 800]
ElementLine [-62487 23973 -65631 27117 800]
ElementLine [-65631 27117 -62487 30261 800]
ElementLine [-62487 30261 -62880 30261 800]
ElementLine [-62880 30261 -64452 31833 800]
)

156
hardware/symbols/FCI-10067847.sym Normal file
View File

@ -0,0 +1,156 @@
v 20060113 1
P 100 4900 400 4900 1 0 0
{
T 300 4950 5 8 1 1 0 6 1
pinnumber=9
T 300 4850 5 8 0 1 0 8 1
pinseq=1
T 450 4900 9 8 1 1 0 0 1
pinlabel=DAT2
T 450 4900 5 8 0 1 0 2 1
pintype=io
}
P 100 4500 400 4500 1 0 0
{
T 300 4550 5 8 1 1 0 6 1
pinnumber=1
T 300 4450 5 8 0 1 0 8 1
pinseq=2
T 450 4500 9 8 1 1 0 0 1
pinlabel=DAT3,\_CS\_
T 450 4500 5 8 0 1 0 2 1
pintype=io
}
P 100 4100 400 4100 1 0 0
{
T 300 4150 5 8 1 1 0 6 1
pinnumber=2
T 300 4050 5 8 0 1 0 8 1
pinseq=3
T 450 4100 9 8 1 1 0 0 1
pinlabel=CMD/DI,MOSI
T 450 4100 5 8 0 1 0 2 1
pintype=io
}
P 100 3700 400 3700 1 0 0
{
T 300 3750 5 8 1 1 0 6 1
pinnumber=3
T 300 3650 5 8 0 1 0 8 1
pinseq=4
T 450 3700 9 8 1 1 0 0 1
pinlabel=GND
T 450 3700 5 8 0 1 0 2 1
pintype=pwr
}
P 100 3300 400 3300 1 0 0
{
T 300 3350 5 8 1 1 0 6 1
pinnumber=4
T 300 3250 5 8 0 1 0 8 1
pinseq=5
T 450 3300 9 8 1 1 0 0 1
pinlabel=Vcc
T 450 3300 5 8 0 1 0 2 1
pintype=io
}
P 100 2900 400 2900 1 0 0
{
T 300 2950 5 8 1 1 0 6 1
pinnumber=5
T 300 2850 5 8 0 1 0 8 1
pinseq=6
T 450 2900 9 8 1 1 0 0 1
pinlabel=SCK
T 450 2900 5 8 0 1 0 2 1
pintype=io
}
P 100 2500 400 2500 1 0 0
{
T 300 2550 5 8 1 1 0 6 1
pinnumber=6
T 300 2450 5 8 0 1 0 8 1
pinseq=7
T 450 2500 9 8 1 1 0 0 1
pinlabel=GND
T 450 2500 5 8 0 1 0 2 1
pintype=pwr
}
P 100 2100 400 2100 1 0 0
{
T 300 2150 5 8 1 1 0 6 1
pinnumber=7
T 300 2050 5 8 0 1 0 8 1
pinseq=8
T 450 2100 9 8 1 1 0 0 1
pinlabel=DAT0/DO,MISO
T 450 2100 5 8 0 1 0 2 1
pintype=io
}
P 100 1700 400 1700 1 0 0
{
T 300 1750 5 8 1 1 0 6 1
pinnumber=8
T 300 1650 5 8 0 1 0 8 1
pinseq=9
T 450 1700 9 8 1 1 0 0 1
pinlabel=DAT1/IRQ
T 450 1700 5 8 0 1 0 2 1
pintype=io
}
P 100 1300 400 1300 1 0 0
{
T 300 1350 5 8 1 1 0 6 1
pinnumber=11
T 300 1250 5 8 0 1 0 8 1
pinseq=10
T 450 1300 9 8 1 1 0 0 1
pinlabel=\_CD\_
T 450 1300 5 8 0 1 0 2 1
pintype=out
}
P 100 900 400 900 1 0 0
{
T 300 950 5 8 1 1 0 6 1
pinnumber=12
T 300 850 5 8 0 1 0 8 1
pinseq=11
T 450 900 9 8 1 1 0 0 1
pinlabel=GND
T 450 900 5 8 0 1 0 2 1
pintype=pwr
}
P 100 500 400 500 1 0 0
{
T 300 550 5 8 1 1 0 6 1
pinnumber=10
T 300 450 5 8 0 1 0 8 1
pinseq=12
T 450 500 9 8 1 1 0 0 1
pinlabel=\_WP\_
T 450 500 5 8 0 1 0 2 1
pintype=out
}
B 400 100 1000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1400 5400 8 10 1 1 0 6 1
refdes=J?
T 400 5400 9 10 1 0 0 0 1
FCI-10067847-001RLF
T 400 5600 5 10 0 0 0 0 1
device=FCI-10067847-001RLF
T 400 5800 5 10 0 0 0 0 1
footprint=FCI-10067847-001RLF
T 400 6000 5 10 0 0 0 0 1
author=Michael McMaster <michael@codesrc.com>
T 400 6200 5 10 0 0 0 0 1
documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html
T 400 6400 5 10 0 0 0 0 1
description=FCI SD Card 10067847-001RLF
T 400 6600 5 10 0 0 0 0 1
numslots=0
T 400 6800 5 10 0 0 0 0 1
dist-license=gpl3+
T 400 7000 5 10 0 0 0 0 1
use-license=gpl3+
T 400 7200 5 10 0 0 0 0 1
net=GND:13

73
hardware/symbols/FCI-10067847.tragesym Normal file
View File

@ -0,0 +1,73 @@
# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.
[options]
# wordswap swaps labels if the pin is on the right side an looks like this:
# "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
# this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
# useful for address ports, busses, ...
wordswap=yes
rotate_labels=yes
sort_labels=no
generate_pinseq=yes
sym_width=1000
pinwidthvertical=400
pinwidthhorizontal=400
[geda_attr]
# name will be printed in the top of the symbol
# name is only some graphical text, not an attribute
# version specifies a gschem version.
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=FCI-10067847-001RLF
device=FCI-10067847-001RLF
refdes=J?
footprint=FCI-10067847-001RLF
description=FCI SD Card 10067847-001RLF
documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html
author=Michael McMaster <michael@codesrc.com>
dist-license=gpl3+
use-license=gpl3+
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=
[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets.
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
# negation lines can be added with "\_" example: \_enable\_
# if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr seq type style posit. net label
#-----------------------------------------------------
9 io line l DAT2
1 io line l DAT3,\_CS\_
2 io line l CMD/DI,MOSI
3 PWR line l GND GND
4 io line l Vcc
5 io line l SCK
6 PWR line l GND GND
7 io line l DAT0/DO,MISO
8 io line l DAT1/IRQ
11 out line l \_CD\_
12 pwr line l GND GND
10 out line l \_WP\_
13 pwr none r GND GND

25
hardware/symbols/FTSH-105-01-L-DV-K.fp Normal file
View File

@ -0,0 +1,25 @@
Element["" "" "" "" 12500 1700 0 0 0 100 ""]
(
Pad[20550 356 20550 8456 2900 1200 4100 "" "10" ""]
Pad[15550 356 15550 8456 2900 1200 4100 "" "8" ""]
Pad[10550 356 10550 8456 2900 1200 4100 "" "6" ""]
Pad[5550 356 5550 8456 2900 1200 4100 "" "4" ""]
Pad[550 356 550 8456 2900 1200 4100 "" "2" ""]
Pad[20550 16356 20550 24456 2900 1200 4100 "" "9" "edge2"]
Pad[15550 16356 15550 24456 2900 1200 4100 "" "7" "edge2"]
Pad[10550 16356 10550 24456 2900 1200 4100 "" "5" "edge2"]
Pad[5550 16356 5550 24456 2900 1200 4100 "" "3" "edge2"]
Pad[550 16356 550 24456 2900 1200 4100 "" "1" "edge2"]
ElementLine [33000 19406 33000 5606 1000]
ElementLine [-12000 5606 -12000 19406 1000]
ElementLine [-12000 5606 -2906 5606 1000]
ElementLine [-2906 5606 -2900 5600 1000]
ElementLine [33000 5700 24200 5700 1000]
ElementLine [-12000 19400 -2900 19400 1000]
ElementLine [33000 19400 24300 19400 1000]
ElementLine [-2900 19400 -2900 14000 1000]
ElementLine [-2900 14000 24300 14000 1000]
ElementLine [24300 14000 24300 19400 1000]
)

64
hardware/symbols/HEADER50_2_RA.fp Normal file
View File

@ -0,0 +1,64 @@
Element(0x00 "Right-angle Header connector, ribbon cable numbering" "" "HEADER50_2" 260 0 3 100 0x00)
(
Pin(150 2450 60 38 "1" 0x01)
Pin(50 2450 60 38 "2" 0x01)
Pin(150 2350 60 38 "3" 0x01)
Pin(50 2350 60 38 "4" 0x01)
Pin(150 2250 60 38 "5" 0x01)
Pin(50 2250 60 38 "6" 0x01)
Pin(150 2150 60 38 "7" 0x01)
Pin(50 2150 60 38 "8" 0x01)
Pin(150 2050 60 38 "9" 0x01)
Pin(50 2050 60 38 "10" 0x01)
Pin(150 1950 60 38 "11" 0x01)
Pin(50 1950 60 38 "12" 0x01)
Pin(150 1850 60 38 "13" 0x01)
Pin(50 1850 60 38 "14" 0x01)
Pin(150 1750 60 38 "15" 0x01)
Pin(50 1750 60 38 "16" 0x01)
Pin(150 1650 60 38 "17" 0x01)
Pin(50 1650 60 38 "18" 0x01)
Pin(150 1550 60 38 "19" 0x01)
Pin(50 1550 60 38 "20" 0x01)
Pin(150 1450 60 38 "21" 0x01)
Pin(50 1450 60 38 "22" 0x01)
Pin(150 1350 60 38 "23" 0x01)
Pin(50 1350 60 38 "24" 0x01)
Pin(150 1250 60 38 "25" 0x01)
Pin(50 1250 60 38 "26" 0x01)
Pin(150 1150 60 38 "27" 0x01)
Pin(50 1150 60 38 "28" 0x01)
Pin(150 1050 60 38 "29" 0x01)
Pin(50 1050 60 38 "30" 0x01)
Pin(150 950 60 38 "31" 0x01)
Pin(50 950 60 38 "32" 0x01)
Pin(150 850 60 38 "33" 0x01)
Pin(50 850 60 38 "34" 0x01)
Pin(150 750 60 38 "35" 0x01)
Pin(50 750 60 38 "36" 0x01)
Pin(150 650 60 38 "37" 0x01)
Pin(50 650 60 38 "38" 0x01)
Pin(150 550 60 38 "39" 0x01)
Pin(50 550 60 38 "40" 0x01)
Pin(150 450 60 38 "41" 0x01)
Pin(50 450 60 38 "42" 0x01)
Pin(150 350 60 38 "43" 0x01)
Pin(50 350 60 38 "44" 0x01)
Pin(150 250 60 38 "45" 0x01)
Pin(50 250 60 38 "46" 0x01)
Pin(150 150 60 38 "47" 0x01)
Pin(50 150 60 38 "48" 0x01)
Pin(150 50 60 38 "49" 0x01)
Pin(50 50 60 38 "50" 0x101)
ElementLine(0 0 0 2500 10)
ElementLine(0 2500 200 2500 10)
ElementLine(200 2500 200 0 10)
ElementLine(200 0 0 0 10)
ElementLine(0 100 100 100 10)
ElementLine(100 100 100 0 10)
ElementLine(-350 0 0 0 10)
ElementLine(-350 0 -350 2500 10)
ElementLine(-350 2500 0 2500 10)
Mark(50 50)
)

55
hardware/symbols/LD1117.sym Normal file
View File

@ -0,0 +1,55 @@
v 20060113 1
P 900 100 900 400 1 0 0
{
T 850 300 5 8 1 1 90 6 1
pinnumber=1
T 950 300 5 8 0 1 90 8 1
pinseq=1
T 900 450 9 8 1 1 90 0 1
pinlabel=GND
T 900 450 5 8 0 1 90 2 1
pintype=pwr
}
P 1700 800 1400 800 1 0 0
{
T 1500 850 5 8 1 1 0 0 1
pinnumber=2
T 1500 750 5 8 0 1 0 2 1
pinseq=2
T 1350 800 9 8 1 1 0 6 1
pinlabel=OUT
T 1350 800 5 8 0 1 0 8 1
pintype=pwr
}
P 100 800 400 800 1 0 0
{
T 300 850 5 8 1 1 0 6 1
pinnumber=3
T 300 750 5 8 0 1 0 8 1
pinseq=3
T 450 800 9 8 1 1 0 0 1
pinlabel=IN
T 450 800 5 8 0 1 0 2 1
pintype=pwr
}
B 400 400 1000 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1400 1300 8 10 1 1 0 6 1
refdes=U?
T 400 1300 9 10 1 0 0 0 1
LD1117
T 400 1500 5 10 0 0 0 0 1
device=LD1117
T 400 1700 5 10 0 0 0 0 1
footprint=DPAK
T 400 1900 5 10 0 0 0 0 1
author=Michael McMaster <michael@codesrc.com>
T 400 2100 5 10 0 0 0 0 1
documentation=http://www.st.com/web/en/resource/technical/document/datasheet/CD00000544.pdf
T 400 2300 5 10 0 0 0 0 1
description=LDO Regulator, fixed
T 400 2500 5 10 0 0 0 0 1
numslots=0
T 400 2700 5 10 0 0 0 0 1
dist-license=gpl3+
T 400 2900 5 10 0 0 0 0 1
use-license=gpl3+

64
hardware/symbols/LD1117.tragesym Normal file
View File

@ -0,0 +1,64 @@
# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.
[options]
# wordswap swaps labels if the pin is on the right side an looks like this:
# "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
# this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
# useful for address ports, busses, ...
wordswap=yes
rotate_labels=yes
sort_labels=no
generate_pinseq=yes
sym_width=1000
pinwidthvertical=400
pinwidthhorizontal=400
[geda_attr]
# name will be printed in the top of the symbol
# name is only some graphical text, not an attribute
# version specifies a gschem version.
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=LD1117
device=LD1117
refdes=U?
footprint=DPAK
description=LDO Regulator, fixed
documentation=http://www.st.com/web/en/resource/technical/document/datasheet/CD00000544.pdf
author=Michael McMaster <michael@codesrc.com>
dist-license=gpl3+
use-license=gpl3+
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=
[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets.
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
# negation lines can be added with "\_" example: \_enable\_
# if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr seq type style posit. net label
#-----------------------------------------------------
1 pwr line b GND GND
2 pwr line r OUT
3 pwr line l IN

18
hardware/symbols/MOLEX8981.fp Normal file
View File

@ -0,0 +1,18 @@
Element ["" "Molex 15-24-4441" "" "" 10000 10000 8000 8000 0 100 ""] (
Pin [0 0 10000 3000 11000 6000 "Pin4" "4" ""]
Pin [20000 0 10000 3000 11000 6000 "Pin3" "3" ""]
Pin [40000 0 10000 3000 11000 6000 "Pin2" "2" ""]
Pin [60000 0 10000 3000 11000 6000 "Pin1" "1" ""]
Pin [-10000 -10000 11000 3000 11000 10000 "LeftHole" "" "hole"]
Pin [70000 -10000 11000 3000 11000 10000 "RightHole" "" "hole"]
Pin [10000 -40000 16000 3000 16000 15700 "BackLeftHole" "" "hole"]
Pin [50000 -40000 16000 3000 16000 15700 "BackRightHole" "" "hole"]
ElementLine[-16000 9000 76000 9000 1000]
ElementLine[-16000 9000 -16000 -50000 1000]
ElementLine[-16000 -50000 76000 -50000 1000]
ElementLine[76000 -50000 76000 9000 1000]
)

64
hardware/symbols/MOLEX8981.sym Normal file
View File

@ -0,0 +1,64 @@
v 20060113 1
P 100 1700 400 1700 1 0 0
{
T 300 1750 5 8 1 1 0 6 1
pinnumber=1
T 300 1650 5 8 0 1 0 8 1
pinseq=1
T 450 1700 9 8 1 1 0 0 1
pinlabel=+12V
T 450 1700 5 8 0 1 0 2 1
pintype=pwr
}
P 100 1300 400 1300 1 0 0
{
T 300 1350 5 8 1 1 0 6 1
pinnumber=2
T 300 1250 5 8 0 1 0 8 1
pinseq=2
T 450 1300 9 8 1 1 0 0 1
pinlabel=GND
T 450 1300 5 8 0 1 0 2 1
pintype=pwr
}
P 100 900 400 900 1 0 0
{
T 300 950 5 8 1 1 0 6 1
pinnumber=3
T 300 850 5 8 0 1 0 8 1
pinseq=3
T 450 900 9 8 1 1 0 0 1
pinlabel=GND
T 450 900 5 8 0 1 0 2 1
pintype=pwr
}
P 100 500 400 500 1 0 0
{
T 300 550 5 8 1 1 0 6 1
pinnumber=4
T 300 450 5 8 0 1 0 8 1
pinseq=4
T 450 500 9 8 1 1 0 0 1
pinlabel=+5V
T 450 500 5 8 0 1 0 2 1
pintype=pwr
}
B 400 100 500 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 900 2200 8 10 1 1 0 6 1
refdes=J?
T 400 2200 9 10 1 0 0 0 1
MOLEX8981
T 400 2400 5 10 0 0 0 0 1
device=MOLEX8981
T 400 2600 5 10 0 0 0 0 1
footprint=MOLEX
T 400 2800 5 10 0 0 0 0 1
author=Michael McMaster <michael@codesrc.com>
T 400 3000 5 10 0 0 0 0 1
description=Disk drive power connector
T 400 3200 5 10 0 0 0 0 1
numslots=0
T 400 3400 5 10 0 0 0 0 1
dist-license=gpl3+
T 400 3600 5 10 0 0 0 0 1
use-license=gpl3+

63
hardware/symbols/MOLEX8981.tragesym Normal file
View File

@ -0,0 +1,63 @@
# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.
[options]
# wordswap swaps labels if the pin is on the right side an looks like this:
# "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
# this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
# useful for address ports, busses, ...
wordswap=yes
rotate_labels=yes
sort_labels=no
generate_pinseq=yes
sym_width=500
pinwidthvertical=400
pinwidthhorizontal=400
[geda_attr]
# name will be printed in the top of the symbol
# name is only some graphical text, not an attribute
# version specifies a gschem version.
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=MOLEX8981
device=MOLEX8981
refdes=J?
footprint=MOLEX
description=Disk drive power connector
documentation=
author=Michael McMaster <michael@codesrc.com>
dist-license=gpl3+
use-license=gpl3+
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=
[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets.
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
# negation lines can be added with "\_" example: \_enable\_
# if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr seq type style posit. net label
#-----------------------------------------------------
1 pwr line l +12V
2 pwr line l GND
3 pwr line l GND
4 pwr line l +5V

156
hardware/symbols/SCDA7A0101.sym Normal file
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@ -0,0 +1,156 @@
v 20060113 1
P 100 4900 400 4900 1 0 0
{
T 300 4950 5 8 1 1 0 6 1
pinnumber=9
T 300 4850 5 8 0 1 0 8 1
pinseq=1
T 450 4900 9 8 1 1 0 0 1
pinlabel=DAT2
T 450 4900 5 8 0 1 0 2 1
pintype=io
}
P 100 4500 400 4500 1 0 0
{
T 300 4550 5 8 1 1 0 6 1
pinnumber=1
T 300 4450 5 8 0 1 0 8 1
pinseq=2
T 450 4500 9 8 1 1 0 0 1
pinlabel=DAT3,\_CS\_
T 450 4500 5 8 0 1 0 2 1
pintype=io
}
P 100 4100 400 4100 1 0 0
{
T 300 4150 5 8 1 1 0 6 1
pinnumber=2
T 300 4050 5 8 0 1 0 8 1
pinseq=3
T 450 4100 9 8 1 1 0 0 1
pinlabel=CMD/DI,MOSI
T 450 4100 5 8 0 1 0 2 1
pintype=io
}
P 100 3700 400 3700 1 0 0
{
T 300 3750 5 8 1 1 0 6 1
pinnumber=3
T 300 3650 5 8 0 1 0 8 1
pinseq=4
T 450 3700 9 8 1 1 0 0 1
pinlabel=GND
T 450 3700 5 8 0 1 0 2 1
pintype=pwr
}
P 100 3300 400 3300 1 0 0
{
T 300 3350 5 8 1 1 0 6 1
pinnumber=4
T 300 3250 5 8 0 1 0 8 1
pinseq=5
T 450 3300 9 8 1 1 0 0 1
pinlabel=Vcc
T 450 3300 5 8 0 1 0 2 1
pintype=io
}
P 100 2900 400 2900 1 0 0
{
T 300 2950 5 8 1 1 0 6 1
pinnumber=5
T 300 2850 5 8 0 1 0 8 1
pinseq=6
T 450 2900 9 8 1 1 0 0 1
pinlabel=SCK
T 450 2900 5 8 0 1 0 2 1
pintype=io
}
P 100 2500 400 2500 1 0 0
{
T 300 2550 5 8 1 1 0 6 1
pinnumber=6
T 300 2450 5 8 0 1 0 8 1
pinseq=7
T 450 2500 9 8 1 1 0 0 1
pinlabel=GND
T 450 2500 5 8 0 1 0 2 1
pintype=pwr
}
P 100 2100 400 2100 1 0 0
{
T 300 2150 5 8 1 1 0 6 1
pinnumber=7
T 300 2050 5 8 0 1 0 8 1
pinseq=8
T 450 2100 9 8 1 1 0 0 1
pinlabel=DAT0/DO,MISO
T 450 2100 5 8 0 1 0 2 1
pintype=io
}
P 100 1700 400 1700 1 0 0
{
T 300 1750 5 8 1 1 0 6 1
pinnumber=8
T 300 1650 5 8 0 1 0 8 1
pinseq=9
T 450 1700 9 8 1 1 0 0 1
pinlabel=DAT1/IRQ
T 450 1700 5 8 0 1 0 2 1
pintype=io
}
P 100 1300 400 1300 1 0 0
{
T 300 1350 5 8 1 1 0 6 1
pinnumber=10
T 300 1250 5 8 0 1 0 8 1
pinseq=10
T 450 1300 9 8 1 1 0 0 1
pinlabel=\_CD\_
T 450 1300 5 8 0 1 0 2 1
pintype=out
}
P 100 900 400 900 1 0 0
{
T 300 950 5 8 1 1 0 6 1
pinnumber=11
T 300 850 5 8 0 1 0 8 1
pinseq=11
T 450 900 9 8 1 1 0 0 1
pinlabel=GND
T 450 900 5 8 0 1 0 2 1
pintype=pwr
}
P 100 500 400 500 1 0 0
{
T 300 550 5 8 1 1 0 6 1
pinnumber=12
T 300 450 5 8 0 1 0 8 1
pinseq=12
T 450 500 9 8 1 1 0 0 1
pinlabel=\_WP\_
T 450 500 5 8 0 1 0 2 1
pintype=out
}
B 400 100 1000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1400 5400 8 10 1 1 0 6 1
refdes=J?
T 400 5400 9 10 1 0 0 0 1
SCDA7A0101
T 400 5600 5 10 0 0 0 0 1
device=SCDA7A0101
T 400 5800 5 10 0 0 0 0 1
footprint=SCDA7A0101
T 400 6000 5 10 0 0 0 0 1
author=Michael McMaster <michael@codesrc.com>
T 400 6200 5 10 0 0 0 0 1
documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html
T 400 6400 5 10 0 0 0 0 1
description=SD Memory Card Connector
T 400 6600 5 10 0 0 0 0 1
numslots=0
T 400 6800 5 10 0 0 0 0 1
dist-license=gpl3+
T 400 7000 5 10 0 0 0 0 1
use-license=gpl3+
T 400 7200 5 10 0 0 0 0 1
net=GND:13,14

74
hardware/symbols/SCDA7A0101.tragesym Normal file
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# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.
[options]
# wordswap swaps labels if the pin is on the right side an looks like this:
# "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
# this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
# useful for address ports, busses, ...
wordswap=yes
rotate_labels=yes
sort_labels=no
generate_pinseq=yes
sym_width=1000
pinwidthvertical=400
pinwidthhorizontal=400
[geda_attr]
# name will be printed in the top of the symbol
# name is only some graphical text, not an attribute
# version specifies a gschem version.
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=SCDA7A0101
device=SCDA7A0101
refdes=J?
footprint=SCDA7A0101
description=SD Memory Card Connector
documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html
author=Michael McMaster <michael@codesrc.com>
dist-license=gpl3+
use-license=gpl3+
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=
[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets.
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
# negation lines can be added with "\_" example: \_enable\_
# if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr seq type style posit. net label
#-----------------------------------------------------
9 io line l DAT2
1 io line l DAT3,\_CS\_
2 io line l CMD/DI,MOSI
3 PWR line l GND GND
4 io line l Vcc
5 io line l SCK
6 PWR line l GND GND
7 io line l DAT0/DO,MISO
8 io line l DAT1/IRQ
10 out line l \_CD\_
11 pwr line l GND GND
12 out line l \_WP\_
13 pwr none r GND GND
14 pwr none r GND GND

30
hardware/symbols/SOT23_MOSFET.fp Normal file
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@ -0,0 +1,30 @@
# 78 for SOT23
# 82 for SOT23
# 41 for SOT23
# 34 for SOT23, 24 for SOT25
Element(0x00 "SMT transistor, 3 pins" "" "SOT23" 148 0 3 100 0x00)
(
ElementLine(0 0 0 139 10)
ElementLine(0 139 128 139 10)
ElementLine(128 139 128 0 10)
ElementLine(128 0 0 0 10)
# 1st side, 1st pin
Pad(25 107
25 113
34
"1" "G" 0x100)
# 1st side, 2nd pin
# 1st side, 3rd pin
Pad(103 107
103 113
34
"2" "S" 0x100)
# 2nd side, 3rd pin
# 2nd side, 2nd pin
Pad(64 25
64 31
34
"3" "D" 0x100)
# 2nd side, 1st pin
Mark(25 110)
)

36
hardware/symbols/SOT26_MOSFET.fp Normal file
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@ -0,0 +1,36 @@
# 78 for SOT23
# 82 for SOT23
# 41 for SOT23
# 34 for SOT23, 24 for SOT25
Element(0x00 "SMT transistor, 6 pins" "" "SOT26" 138 0 3 100 0x00)
(
ElementLine(0 0 0 139 10)
ElementLine(0 139 118 139 10)
ElementLine(118 139 118 0 10)
ElementLine(118 0 0 0 10)
# 1st side, 1st pin
Pad(20 102
20 118
24 "1" "D" 0x100)
# 1st side, 2nd pin
Pad(59 102
59 118
24 "2" "D" 0x100)
# 1st side, 3rd pin
Pad(98 102
98 118
24 "3" "G" 0x100)
# 2nd side, 3rd pin
Pad(98 20
98 36
24 "4" "S" 0x100)
# 2nd side, 2nd pin
Pad(59 20
59 36
24 "5" "D" 0x100)
# 2nd side, 1st pin
Pad(20 20
20 36
24 "6" "D" 0x100)
Mark(20 110)
)

19
hardware/symbols/TO220_TRANSISTOR.fp Normal file
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@ -0,0 +1,19 @@
Element(0x00 "Transistor" "" "TO220W" 0 10 0 100 0x00)
(
Pin(100 200 90 60 "1" "B" 0x101)
Pin(200 200 90 60 "2" "C" 0x01)
Pin(300 200 90 60 "3" "E" 0x01)
# Gehaeuse
ElementLine( 0 80 400 80 20)
ElementLine(400 80 400 260 20)
ElementLine(400 260 0 260 20)
ElementLine( 0 260 0 80 20)
# Kuehlfahne icl. Bohrung
ElementLine( 0 80 400 80 20)
ElementLine(400 80 400 140 20)
ElementLine(400 140 0 140 20)
ElementLine( 0 140 0 80 20)
ElementLine(130 80 130 140 10)
ElementLine(270 80 270 140 10)
Mark(100 200)
)

11
hardware/symbols/cap_0402.fp Normal file
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@ -0,0 +1,11 @@
Element["" "" "" "" 2137 2037 0 0 0 100 ""]
(
Pad[3872 35 3872 35 1969 1200 2569 "1" "1" "square,edge2"]
Pad[-65 35 -65 35 1969 1200 2569 "2" "2" "square"]
ElementLine [-1837 1806 -1837 -1737 600]
ElementLine [5643 1806 -1837 1806 600]
ElementLine [5643 -1737 5643 1806 600]
ElementLine [-1837 -1737 5643 -1737 600]
)

24
hardware/symbols/diode-DO-214AA-SMB.fp Normal file
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@ -0,0 +1,24 @@
Element["" "" "" "" 235039 155118 0 0 0 100 ""]
(
Pad[197 -591 984 -591 9055 2000 10055 "cathode" "1" "square"]
Pad[17126 -591 17913 -591 9055 2000 10055 "anode" "2" "square,edge2"]
ElementLine [-5118 -9843 -5118 9055 1000]
ElementLine [-5118 9055 23622 9055 1000]
ElementLine [23622 9055 23622 -9843 1000]
ElementLine [23622 -9843 -5118 -9843 1000]
ElementLine [-394 -9843 -394 -5906 1000]
ElementLine [-394 -5906 394 -5906 1000]
ElementLine [394 -5906 394 -9055 1000]
ElementLine [-394 9055 -394 5118 1000]
ElementLine [-394 5118 394 5118 1000]
ElementLine [394 5118 394 8268 1000]
ElementLine [10236 3937 7874 6299 1000]
ElementLine [7874 6299 10630 9055 1000]
ElementLine [10630 9055 10630 4331 1000]
ElementLine [10630 4331 10236 3937 1000]
ElementLine [10630 6299 16535 6299 1000]
ElementLine [7087 3543 7087 9055 1000]
ElementLine [4724 6299 7874 6299 1000]
)

23
hardware/symbols/fci-10118192-0001LF.fp Normal file
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@ -0,0 +1,23 @@
Element["" "" "" "" 275009 222794 0 0 0 100 ""]
(
Pad[-63 -8271 -63 -4531 1575 1200 2175 "3" "3" "square"]
Pad[5055 -8271 5055 -4531 1575 1200 2175 "5" "5" "square"]
Pad[-5181 -8271 -5181 -4531 1575 1200 2175 "1" "1" "square"]
Pad[2496 -8271 2496 -4531 1575 1200 2175 "4" "4" "square"]
Pad[-2622 -8271 -2622 -4531 1575 1200 2175 "2" "2" "square"]
Pad[-13252 -5909 -11284 -5909 6299 1200 6899 "" "6" "square"]
Pad[11157 -5909 13126 -5909 6299 1200 6899 "" "7" "square,edge2"]
Pad[-15024 3934 -15024 4328 7087 1200 7687 "" "8" "square,edge2"]
Pad[-4788 4131 -4788 4131 7480 1200 8080 "" "9" "square"]
Pad[4661 4131 4661 4131 7480 1200 8080 "" "10" "square,edge2"]
Pad[14897 3934 14897 4328 7087 1200 7687 "" "11" "square,edge2"]
ElementLine [-18567 9840 18441 9840 600]
ElementLine [-15024 9840 -15024 8462 600]
ElementLine [-15024 -3 -15024 -2168 600]
ElementLine [15094 9840 15094 8462 600]
ElementLine [15094 -3 15094 -2168 600]
ElementLine [-7741 -7877 -6559 -7877 600]
ElementLine [6236 -7877 7614 -7877 600]
)

51
hardware/symbols/usbmini.sym Normal file
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@ -0,0 +1,51 @@
v 20070818 1
T 100 100 0 1 0 0 0 0 1
gedasymbols::url=http://www.gedasymbols.org/user/sean_depagnier/symbols/usbmini.sym
T 700 1600 8 10 1 1 0 0 1
refdes=CONN?
T 100 1600 9 10 1 1 0 0 1
device=USB
T 400 12650 8 10 0 0 0 0 1
footprint=usbminib
B 100 0 800 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1300 400 900 400 1 0 0
{
T 1100 490 5 10 1 1 0 0 1
pinnumber=4
T 600 380 5 10 1 1 0 0 1
pinlabel=ID
}
P 1300 700 900 700 1 0 0
{
T 1100 730 5 10 1 1 0 0 1
pinnumber=3
T 600 720 5 10 1 1 0 0 1
pinlabel=D+
}
P 1300 1000 900 1000 1 0 0
{
T 1100 1070 5 10 1 1 0 0 1
pinnumber=2
T 600 1060 5 10 1 1 0 0 1
pinlabel=D-
}
P 1300 1300 900 1300 1 0 0
{
T 1100 1310 5 10 1 1 0 0 1
pinnumber=1
T 400 1300 5 10 1 1 0 0 1
pinlabel=VCC
}
T 400 12450 8 10 0 0 0 0 1
T 400 13650 8 10 0 0 0 0 1
T 400 13850 8 10 0 0 0 0 1
numslots=0
T 400 14050 8 10 0 0 0 0 1
author=Sean D'Epagnier
P 1300 100 900 100 1 0 0
{
T 1100 190 5 10 1 1 0 0 1
pinnumber=5
T 400 80 5 10 1 1 0 0 1
pinlabel=GND
}

28
hardware/symbols/wurth-microsd.fp Normal file
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@ -0,0 +1,28 @@
Element["" "" "" "" 58000 53000 0 0 0 100 ""]
(
Pad[-7555 -17555 -7555 -14799 3150 1200 3750 "1" "1" "square"]
Pad[-3224 -15980 -3224 -13224 3150 1200 3750 "2" "2" "square"]
Pad[1106 -17555 1106 -14799 3150 1200 3750 "3" "3" "square"]
Pad[5437 -18343 5437 -15587 3150 1200 3750 "4" "4" "square"]
Pad[9768 -17555 9768 -14799 3150 1200 3750 "5" "5" "square"]
Pad[14098 -18343 14098 -15587 3150 1200 3750 "6" "6" "square"]
Pad[18429 -17555 18429 -14799 3150 1200 3750 "7" "7" "square"]
Pad[22760 -17555 22760 -14799 3150 1200 3750 "8" "8" "square"]
Pad[25909 -28185 25909 -26217 5512 1200 6112 "9" "9" "square"]
Pad[18035 24571 19610 24571 5512 1200 6112 "10" "10" "square,edge2"]
Pad[-4406 24571 -2831 24571 5512 1200 6112 "10" "10" "square"]
Pad[-26453 -32516 -26453 -30547 5512 1200 6112 "9" "9" "square"]
ElementLine [-19000 -31500 -11000 -31500 600]
ElementLine [-11000 -31500 -11000 -26500 600]
ElementLine [-11000 -26500 19500 -26500 600]
ElementLine [19500 -26500 22000 -29000 600]
ElementLine [-19000 -31500 -19000 -34000 600]
ElementLine [-19000 -34000 -22500 -34000 600]
ElementLine [-28000 -27000 -28000 26000 600]
ElementLine [-28000 26000 -9000 26000 600]
ElementLine [1000 26000 14000 26000 600]
ElementLine [23500 26000 27500 26000 600]
ElementLine [27500 26000 27500 -22000 600]
)

132
hardware/symbols/wurth-microsd.sym Normal file
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@ -0,0 +1,132 @@
v 20060113 1
P 100 4100 400 4100 1 0 0
{
T 300 4150 5 8 1 1 0 6 1
pinnumber=1
T 300 4050 5 8 0 1 0 8 1
pinseq=1
T 450 4100 9 8 1 1 0 0 1
pinlabel=DAT2
T 450 4100 5 8 0 1 0 2 1
pintype=io
}
P 100 3700 400 3700 1 0 0
{
T 300 3750 5 8 1 1 0 6 1
pinnumber=2
T 300 3650 5 8 0 1 0 8 1
pinseq=2
T 450 3700 9 8 1 1 0 0 1
pinlabel=DAT3
T 450 3700 5 8 0 1 0 2 1
pintype=io
}
P 100 3300 400 3300 1 0 0
{
T 300 3350 5 8 1 1 0 6 1
pinnumber=3
T 300 3250 5 8 0 1 0 8 1
pinseq=3
T 450 3300 9 8 1 1 0 0 1
pinlabel=CMD
T 450 3300 5 8 0 1 0 2 1
pintype=io
}
P 100 2900 400 2900 1 0 0
{
T 300 2950 5 8 1 1 0 6 1
pinnumber=4
T 300 2850 5 8 0 1 0 8 1
pinseq=4
T 450 2900 9 8 1 1 0 0 1
pinlabel=Vcc
T 450 2900 5 8 0 1 0 2 1
pintype=pwr
}
P 100 2500 400 2500 1 0 0
{
T 300 2550 5 8 1 1 0 6 1
pinnumber=5
T 300 2450 5 8 0 1 0 8 1
pinseq=5
T 450 2500 9 8 1 1 0 0 1
pinlabel=CLK
T 450 2500 5 8 0 1 0 2 1
pintype=clk
}
P 100 2100 400 2100 1 0 0
{
T 300 2150 5 8 1 1 0 6 1
pinnumber=6
T 300 2050 5 8 0 1 0 8 1
pinseq=6
T 450 2100 9 8 1 1 0 0 1
pinlabel=GND
T 450 2100 5 8 0 1 0 2 1
pintype=pwr
}
P 100 1700 400 1700 1 0 0
{
T 300 1750 5 8 1 1 0 6 1
pinnumber=7
T 300 1650 5 8 0 1 0 8 1
pinseq=7
T 450 1700 9 8 1 1 0 0 1
pinlabel=DAT0
T 450 1700 5 8 0 1 0 2 1
pintype=io
}
P 100 1300 400 1300 1 0 0
{
T 300 1350 5 8 1 1 0 6 1
pinnumber=8
T 300 1250 5 8 0 1 0 8 1
pinseq=8
T 450 1300 9 8 1 1 0 0 1
pinlabel=DAT1
T 450 1300 5 8 0 1 0 2 1
pintype=io
}
P 100 900 400 900 1 0 0
{
T 300 950 5 8 1 1 0 6 1
pinnumber=9
T 300 850 5 8 0 1 0 8 1
pinseq=9
T 450 900 9 8 1 1 0 0 1
pinlabel=GND
T 450 900 5 8 0 1 0 2 1
pintype=io
}
P 100 500 400 500 1 0 0
{
T 300 550 5 8 1 1 0 6 1
pinnumber=10
T 300 450 5 8 0 1 0 8 1
pinseq=10
T 450 500 9 8 1 1 0 0 1
pinlabel=\_CD\_
T 450 500 5 8 0 1 0 2 1
pintype=pwr
}
B 400 100 1000 4400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1400 4600 8 10 1 1 0 6 1
refdes=J?
T 400 4600 9 10 1 0 0 0 1
wurth-microsd
T 400 4800 5 10 0 0 0 0 1
device=wurth-693071010811
T 400 5000 5 10 0 0 0 0 1
footprint=wurth-microsd
T 400 5200 5 10 0 0 0 0 1
author=Michael McMaster <michael@codesrc.com>
T 400 5400 5 10 0 0 0 0 1
documentation=http://www.digikey.com/product-detail/en/693071010811/732-3819-1-ND/3124603
T 400 5600 5 10 0 0 0 0 1
description=Wurth MicroSD socket 693071010811
T 400 5800 5 10 0 0 0 0 1
numslots=0
T 400 6000 5 10 0 0 0 0 1
dist-license=gpl3+
T 400 6200 5 10 0 0 0 0 1
use-license=gpl3+

70
hardware/symbols/wurth-microsd.tragesym Normal file
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@ -0,0 +1,70 @@
# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.
[options]
# wordswap swaps labels if the pin is on the right side an looks like this:
# "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
# this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
# useful for address ports, busses, ...
wordswap=yes
rotate_labels=yes
sort_labels=no
generate_pinseq=yes
sym_width=1000
pinwidthvertical=400
pinwidthhorizontal=400
[geda_attr]
# name will be printed in the top of the symbol
# name is only some graphical text, not an attribute
# version specifies a gschem version.
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=wurth-microsd
device=wurth-693071010811
refdes=J?
footprint=wurth-microsd
description=Wurth MicroSD socket 693071010811
documentation=http://www.digikey.com/product-detail/en/693071010811/732-3819-1-ND/3124603
author=Michael McMaster <michael@codesrc.com>
dist-license=gpl3+
use-license=gpl3+
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=
[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets.
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
# negation lines can be added with "\_" example: \_enable\_
# if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr seq type style posit. net label
#-----------------------------------------------------
1 io line l DAT2
2 io line l DAT3
3 io line l CMD
4 pwr line l Vcc
5 clk line l CLK
6 pwr line l GND GND
7 io line l DAT0
8 io line l DAT1
9 io line l GND GND
10 pwr line l \_CD\_

BIN
parts.ods Normal file
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Binary file not shown.

33
readme.txt Normal file
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@ -0,0 +1,33 @@
SCSI2SD, The SCSI Hard Drive Emulator for retro computing.
Traditional hard drives last X years. Maybe, if you're luckly, you'll get X years of
service from a particular drive. The lubricants wear out, the spindles rust.
SCSI2SD is a modern replacement for failed drives. It allows the use ofvintage
computer hardware long after their mechanical drives fail. The use of SD memory cards
solves the problem of transferring data between the retro computer and a
modern PC (who still has access to a working floppy drive ?)
Features:
Terminator, termpwr, firmware upgradable (via the SD card)
Selectable SCSI ID (via jumpers)
Emulates a non-removable hard drive (does not present as a removable memory card reader) for maximum compatibility.
Unit attention configurability.
Technical Specifications:
SCSI Interface: SCSI-2 Narrow 8-bit 50-pin connector.
SD Card Support:
(state max size)
Currently SD standard (1GB), no SDHC/SDXC support.
Power:
Dimensions:
Performance:
Sequential read/write: 250kb/sec, 50kb/sec. Add some results of some SCSI hard drives
for comparison. 160Mb, 250Mb, 1Gb.
Compatibility:
Tested with Linux, Apple Macintosh System 7.5 on LC-II, LC-III, and LC-475 hardware.
Love to hear your success stories on other platforms.

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*.cywrk*

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codegentemp
CortexM3
*.Micha_000
*.rpt
*.pdf
*.html

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;********************************************************************************
;* File Name: Cm3RealView.scat
;* Version 3.40
;*
;* Description:
;* This Linker Descriptor file describes the memory layout of the PSoC5
;* device. The memory layout of the final binary and hex images as well as
;* the placement in PSoC5 memory is described.
;*
;*
;* Note:
;*
;* romvectors: Cypress default Interrupt sevice routine vector table.
;*
;* This is the ISR vector table at bootup. Used only for the reset vector.
;*
;*
;* ramvectors: Cypress ram interrupt service routine vector table.
;*
;* This is the ISR vector table used by the application.
;*
;*
;********************************************************************************
;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;********************************************************************************/
LOAD_ROM 0 (262144 - 0)
{
VECTORS +0
{
* (.romvectors)
}
CODE +0
{
* (+RO)
}
ISRVECTORS (0x20000000 - (65536 / 2)) UNINIT
{
* (.ramvectors)
}
NOINIT_DATA +0 UNINIT
{
* (.noinit)
}
DATA +0
{
* (+RW, +ZI)
}
ARM_LIB_HEAP (0x20000000 + (65536 / 2) - 0x1000 - 0x4000) EMPTY 0x1000
{
}
ARM_LIB_STACK (0x20000000 + (65536 / 2)) EMPTY -0x4000
{
}
}

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/*******************************************************************************
* File Name: Cm3Start.c
* Version 3.40
*
* Description:
* Startup code for the ARM CM3.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cydevice_trm.h"
#include "cytypes.h"
#include "cyfitter_cfg.h"
#include "CyLib.h"
#include "CyDmac.h"
#include "cyfitter.h"
#define NUM_INTERRUPTS 32u
#define NUM_VECTORS (CYINT_IRQ_BASE+NUM_INTERRUPTS)
#define NUM_ROM_VECTORS 4u
#define NVIC_APINT ((reg32 *) CYREG_NVIC_APPLN_INTR)
#define NVIC_CFG_CTRL ((reg32 *) CYREG_NVIC_CFG_CONTROL)
#define NVIC_APINT_PRIGROUP_3_5 0x00000400u /* Priority group 3.5 split */
#define NVIC_APINT_VECTKEY 0x05FA0000u /* This key is required in order to write the NVIC_APINT register */
#define NVIC_CFG_STACKALIGN 0x00000200u /* This specifies that the exception stack must be 8 byte aligned */
/* Extern functions */
extern void CyBtldr_CheckLaunch(void);
/* Function prototypes */
void initialize_psoc(void);
CY_ISR(IntDefaultHandler);
void Reset(void);
CY_ISR(IntDefaultHandler);
#if defined(__ARMCC_VERSION)
#define INITIAL_STACK_POINTER (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit
#elif defined (__GNUC__)
#define INITIAL_STACK_POINTER __cs3_stack
#endif /* (__ARMCC_VERSION) */
/* Global variables */
CY_NOINIT static uint32 cySysNoInitDataValid;
/*******************************************************************************
* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.
*******************************************************************************/
__attribute__ ((section(".ramvectors")))
#if defined(__ARMCC_VERSION)
__align(256)
#elif defined (__GNUC__)
__attribute__ ((aligned(256)))
#endif
cyisraddress CyRamVectors[NUM_VECTORS];
/*******************************************************************************
* Function Name: IntDefaultHandler
********************************************************************************
*
* Summary:
* This function is called for all interrupts, other than reset, that get
* called before the system is setup.
*
* Parameters:
* None
*
* Return:
* None
*
* Theory:
* Any value other than zero is acceptable.
*
*******************************************************************************/
CY_ISR(IntDefaultHandler)
{
while(1)
{
/***********************************************************************
* We should never get here. If we do, a serious problem occured, so go
* into an infinite loop.
***********************************************************************/
}
}
#if defined(__ARMCC_VERSION)
/* Local function for the device reset. */
extern void Reset(void);
/* Application entry point. */
extern void $Super$$main(void);
/* Linker-generated Stack Base addresses, Two Region and One Region */
extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit;
/* RealView C Library initialization. */
extern int __main(void);
/*******************************************************************************
* Function Name: Reset
********************************************************************************
*
* Summary:
* This function handles the reset interrupt for the RVDS/MDK toolchains.
* This is the first bit of code that is executed at startup.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
__asm void Reset(void)
{
PRESERVE8
EXTERN __main
EXTERN CyResetStatus
#if(CYDEV_BOOTLOADER_ENABLE)
EXTERN CyBtldr_CheckLaunch
#endif /* (CYDEV_BOOTLOADER_ENABLE) */
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
#if(CYDEV_DEBUGGING_ENABLE)
ldr r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */
ldrb r4, [r3, #0]
orr r4, r4, #01
strb r4, [r3, #0]
debugEnabled
#endif /* (CYDEV_DEBUGGING_ENABLE) */
ldr r3, =0x400046fa /* CYREG_RESET_SR0 */
ldrb r2, [r3, #0]
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
ldr r3, =0x400076BC /* CYREG_PHUB_CFGMEM23_CFG1 */
strb r2, [r3, #0]
#if(CYDEV_BOOTLOADER_ENABLE)
bl CyBtldr_CheckLaunch
#endif /* (CYDEV_BOOTLOADER_ENABLE) */
/* Let RealView setup the libraries. */
bl __main
ALIGN
}
/*******************************************************************************
* Function Name: $Sub$$main
********************************************************************************
*
* Summary:
* This function is called imediatly before the users main
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void $Sub$$main(void)
{
initialize_psoc();
/* Call original main */
$Super$$main();
/* If main returns it is undefined what we should do. */
while (1);
}
#elif defined(__GNUC__)
extern void __cs3_stack(void);
extern void __cs3_start_c(void);
/*******************************************************************************
* Function Name: Reset
********************************************************************************
*
* Summary:
* This function handles the reset interrupt for the GCC toolchain. This is the
* first bit of code that is executed at startup.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
__attribute__ ((naked))
void Reset(void)
{
__asm volatile(
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
#if(CYDEV_DEBUGGING_ENABLE)
" ldr r3, =%0\n"
" ldrb r4, [r3, #0]\n"
" orr r4, r4, #01\n"
" strb r4, [r3, #0]\n"
"debugEnabled:\n"
#endif /* (CYDEV_DEBUGGING_ENABLE) */
" ldr r3, =%1\n"
" ldrb r2, [r3, #0]\n"
" uxtb r2, r2\n"
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
" ldr r3, =%2\n"
" strb r2, [r3, #0]\n"
#if(CYDEV_BOOTLOADER_ENABLE)
" bl CyBtldr_CheckLaunch\n"
#endif /* (CYDEV_BOOTLOADER_ENABLE) */
/* Switch to C initialization phase */
" bl __cs3_start_c\n" : : "i" (CYDEV_DEBUG_ENABLE_REGISTER), "i" (CYREG_RESET_SR0), "i" (CYREG_PHUB_CFGMEM23_CFG1));
}
#endif /* __GNUC__ */
/*******************************************************************************
*
* Default Rom Interrupt Vector table.
*
*******************************************************************************/
#if defined(__ARMCC_VERSION)
#pragma diag_suppress 1296
#endif
__attribute__ ((section(".romvectors")))
const cyisraddress RomVectors[NUM_ROM_VECTORS] =
{
#if defined(__ARMCC_VERSION)
INITIAL_STACK_POINTER, /* The initial stack pointer 0 */
#elif defined (__GNUC__)
&INITIAL_STACK_POINTER, /* The initial stack pointer 0 */
#endif /* (__ARMCC_VERSION) */
(cyisraddress)&Reset, /* The reset handler 1 */
&IntDefaultHandler, /* The NMI handler 2 */
&IntDefaultHandler, /* The hard fault handler 3 */
};
/*******************************************************************************
* Function Name: initialize_psoc
********************************************************************************
*
* Summary:
* This function used to initialize the PSoC chip before calling main.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))
__attribute__ ((constructor(101)))
#endif
void initialize_psoc(void)
{
uint32 i;
/* Set Priority group 5. */
/* Writes to NVIC_APINT register require the VECTKEY in the upper half */
*NVIC_APINT = NVIC_APINT_VECTKEY | NVIC_APINT_PRIGROUP_3_5;
*NVIC_CFG_CTRL |= NVIC_CFG_STACKALIGN;
/* Set Ram interrupt vectors to default functions. */
for(i = 0u; i < NUM_VECTORS; i++)
{
CyRamVectors[i] = (i < NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
}
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
/* Point NVIC at the RAM vector table. */
*CYINT_VECT_TABLE = CyRamVectors;
/* Initialize the configuration registers. */
cyfitter_cfg();
#if(0u != DMA_CHANNELS_USED__MASK0)
/* Setup DMA - only necessary if the design contains a DMA component. */
CyDmacConfigure();
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */
/* Actually, no need to clean this variable, just to make compiler happy. */
cySysNoInitDataValid = 0u;
}
/* [] END OF FILE */

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/*******************************************************************************
* File Name: CyBootAsmGnu.s
* Version 3.40
*
* Description:
* Assembly routines for GNU as.
*
********************************************************************************
* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
.syntax unified
.text
.thumb
/*******************************************************************************
* Function Name: CyDelayCycles
********************************************************************************
*
* Summary:
* Delays for the specified number of cycles.
*
* Parameters:
* uint32 cycles: number of cycles to delay.
*
* Return:
* None
*
*******************************************************************************/
/* void CyDelayCycles(uint32 cycles) */
.align 3 /* Align to 8 byte boundary (2^n) */
.global CyDelayCycles
.func CyDelayCycles, CyDelayCycles
.type CyDelayCycles, %function
.thumb_func
CyDelayCycles: /* cycles bytes */
ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */
LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */
BEQ CyDelayCycles_done /* 2 2 Skip if 0 */
NOP /* 1 2 Loop alignment padding */
CyDelayCycles_loop:
SUBS r0, r0, #1 /* 1 2 */
MOV r0, r0 /* 1 2 Pad loop to power of two cycles */
BNE CyDelayCycles_loop /* 2 2 */
CyDelayCycles_done:
BX lr /* 3 2 */
.endfunc
/*******************************************************************************
* Function Name: CyEnterCriticalSection
********************************************************************************
*
* Summary:
* CyEnterCriticalSection disables interrupts and returns a value indicating
* whether interrupts were previously enabled (the actual value depends on
* whether the device is PSoC 3 or PSoC 5).
*
* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
* with interrupts still enabled. The test and set of the interrupt bits is not
* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
* corrupting processor state, it must be the policy that all interrupt routines
* restore the interrupt enable bits as they were found on entry.
*
* Parameters:
* None
*
* Return:
* uint8
* Returns 0 if interrupts were previously enabled or 1 if interrupts
* were previously disabled.
*
*******************************************************************************/
/* uint8 CyEnterCriticalSection(void) */
.global CyEnterCriticalSection
.func CyEnterCriticalSection, CyEnterCriticalSection
.type CyEnterCriticalSection, %function
.thumb_func
CyEnterCriticalSection:
MRS r0, PRIMASK /* Save and return interrupt state */
CPSID I /* Disable interrupts */
BX lr
.endfunc
/*******************************************************************************
* Function Name: CyExitCriticalSection
********************************************************************************
*
* Summary:
* CyExitCriticalSection re-enables interrupts if they were enabled before
* CyEnterCriticalSection was called. The argument should be the value returned
* from CyEnterCriticalSection.
*
* Parameters:
* uint8 savedIntrStatus:
* Saved interrupt status returned by the CyEnterCriticalSection function.
*
* Return:
* None
*
*******************************************************************************/
/* void CyExitCriticalSection(uint8 savedIntrStatus) */
.global CyExitCriticalSection
.func CyExitCriticalSection, CyExitCriticalSection
.type CyExitCriticalSection, %function
.thumb_func
CyExitCriticalSection:
MSR PRIMASK, r0 /* Restore interrupt state */
BX lr
.endfunc
.end
/* [] END OF FILE */

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;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmRv.s
; Version 3.40
;
; DESCRIPTION:
; Assembly routines for RealView.
;
;-------------------------------------------------------------------------------
; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;-------------------------------------------------------------------------------
AREA |.text|,CODE,ALIGN=3
THUMB
EXTERN Reset
;-------------------------------------------------------------------------------
; Function Name: CyDelayCycles
;-------------------------------------------------------------------------------
;
; Summary:
; Delays for the specified number of cycles.
;
; Parameters:
; uint32 cycles: number of cycles to delay.
;
; Return:
; None
;
;-------------------------------------------------------------------------------
; void CyDelayCycles(uint32 cycles)
ALIGN 8
CyDelayCycles FUNCTION
EXPORT CyDelayCycles
; cycles bytes
ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4
LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags
BEQ CyDelayCycles_done ; 2 2 Skip if 0
NOP ; 1 2 Loop alignment padding
CyDelayCycles_loop
SUBS r0, r0, #1 ; 1 2
MOV r0, r0 ; 1 2 Pad loop to power of two cycles
BNE CyDelayCycles_loop ; 2 2
CyDelayCycles_done
BX lr ; 3 2
ENDFUNC
;-------------------------------------------------------------------------------
; Function Name: CyEnterCriticalSection
;-------------------------------------------------------------------------------
;
; Summary:
; CyEnterCriticalSection disables interrupts and returns a value indicating
; whether interrupts were previously enabled (the actual value depends on
; whether the device is PSoC 3 or PSoC 5).
;
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
; with interrupts still enabled. The test and set of the interrupt bits is not
; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
; corrupting processor state, it must be the policy that all interrupt routines
; restore the interrupt enable bits as they were found on entry.
;
; Parameters:
; None
;
; Return:
; uint8
; Returns 0 if interrupts were previously enabled or 1 if interrupts
; were previously disabled.
;
;-------------------------------------------------------------------------------
; uint8 CyEnterCriticalSection(void)
CyEnterCriticalSection FUNCTION
EXPORT CyEnterCriticalSection
MRS r0, PRIMASK ; Save and return interrupt state
CPSID I ; Disable interrupts
BX lr
ENDFUNC
;-------------------------------------------------------------------------------
; Function Name: CyExitCriticalSection
;-------------------------------------------------------------------------------
;
; Summary:
; CyExitCriticalSection re-enables interrupts if they were enabled before
; CyEnterCriticalSection was called. The argument should be the value returned
; from CyEnterCriticalSection.
;
; Parameters:
; uint8 savedIntrStatus:
; Saved interrupt status returned by the CyEnterCriticalSection function.
;
; Return:
; None
;
;-------------------------------------------------------------------------------
; void CyExitCriticalSection(uint8 savedIntrStatus)
CyExitCriticalSection FUNCTION
EXPORT CyExitCriticalSection
MSR PRIMASK, r0 ; Restore interrupt state
BX lr
ENDFUNC
END
; [] END OF FILE

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/*******************************************************************************
* File Name: CyDmac.h
* Version 3.40
*
* Description:
* Provides the function definitions for the DMA Controller.
*
* Note:
* Documentation of the API's in this file is located in the
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_BOOT_CYDMAC_H)
#define CY_BOOT_CYDMAC_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cydevice_trm.h"
#include "CyLib.h"
/***************************************
* Function Prototypes
***************************************/
/* DMA Controller functions. */
void CyDmacConfigure(void) ;
uint8 CyDmacError(void) ;
void CyDmacClearError(uint8 error) ;
uint32 CyDmacErrorAddress(void) ;
/* Channel specific functions. */
uint8 CyDmaChAlloc(void) ;
cystatus CyDmaChFree(uint8 chHandle) ;
cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ;
cystatus CyDmaChDisable(uint8 chHandle) ;
cystatus CyDmaClearPendingDrq(uint8 chHandle) ;
cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;
cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination);
cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;
cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;
cystatus CyDmaChGetRequest(uint8 chHandle) ;
cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;
cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, uint8 tdDone1, uint8 tdStop) ;
cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;
/* Transfer Descriptor functions. */
uint8 CyDmaTdAllocate(void) ;
void CyDmaTdFree(uint8 tdHandle) ;
uint8 CyDmaTdFreeCount(void) ;
cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) ;
cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) ;
cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;
cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;
/***************************************
* Data Struct Definitions
***************************************/
typedef struct dmac_ch_struct
{
volatile uint8 basic_cfg[4];
volatile uint8 action[4];
volatile uint8 basic_status[4];
volatile uint8 reserved[4];
} dmac_ch;
typedef struct dmac_cfgmem_struct
{
volatile uint8 CFG0[4];
volatile uint8 CFG1[4];
} dmac_cfgmem;
typedef struct dmac_tdmem_struct
{
volatile uint8 TD0[4];
volatile uint8 TD1[4];
} dmac_tdmem;
typedef struct dmac_tdmem2_struct
{
volatile uint16 xfercnt;
volatile uint8 next_td_ptr;
volatile uint8 flags;
volatile uint16 src_adr;
volatile uint16 dst_adr;
} dmac_tdmem2;
/***************************************
* API Constants
***************************************/
#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */
#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */
#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */
#if(CY_PSOC3 || CY_PSOC5LP)
#define CY_DMA_DISABLE_TD 0xFEu
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define CY_DMA_TD_SIZE 0x08u
/* The "u" was removed as workaround for Keil compiler bug */
#define CY_DMA_TD_SWAP_EN 0x80
#define CY_DMA_TD_SWAP_SIZE4 0x40
#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20
#define CY_DMA_TD_TERMIN_EN 0x10
#define CY_DMA_TD_TERMOUT1_EN 0x08
#define CY_DMA_TD_TERMOUT0_EN 0x04
#define CY_DMA_TD_INC_DST_ADR 0x02
#define CY_DMA_TD_INC_SRC_ADR 0x01
#define CY_DMA_NUMBEROF_TDS 128u
#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE))
/* Action register bits */
#define CY_DMA_CPU_REQ ((uint8)(1u << 0u))
#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u))
#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u))
/* Basic Status register bits */
#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u))
#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u))
/* DMA controller register error bits */
#define CY_DMA_BUS_TIMEOUT (1u << 1u)
#define CY_DMA_UNPOP_ACC (1u << 2u)
#define CY_DMA_PERIPH_ERR (1u << 3u)
/* Round robin bits */
#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u))
/***************************************
* Registers
***************************************/
#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG)
#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG)
#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR)
#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR)
#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR)
#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR)
#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
/*******************************************************************************
* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
*******************************************************************************/
#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL)
#define DMA_INVALID_TD (CY_DMA_INVALID_TD)
#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD)
#define DMAC_TD_SIZE (CY_DMA_TD_SIZE)
#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN)
#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4)
#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT)
#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN)
#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN)
#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN)
#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR)
#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR)
#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS)
#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS)
#define CPU_REQ (CY_DMA_CPU_REQ)
#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD)
#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN)
#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE)
#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE)
#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT)
#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC)
#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR)
#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE)
#if(CY_PSOC3 || CY_PSOC5LP)
#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define DMAC_CFG (CY_DMA_CFG_PTR)
#define DMAC_ERR (CY_DMA_ERR_PTR)
#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR)
#define DMAC_CH (CY_DMA_CH_STRUCT_PTR)
#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR)
#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR)
#endif /* (CY_BOOT_CYDMAC_H) */
/* [] END OF FILE */

732
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/*******************************************************************************
* File Name: CyFlash.c
* Version 3.40
*
* Description:
* Provides an API for the FLASH/EEPROM.
*
* Note:
* This code is endian agnostic.
*
* Note:
* Documentation of the API's in this file is located in the
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "CyFlash.h"
/*******************************************************************************
* Holds die temperature, updated by CySetTemp(). Used for flash writting.
* The first byte is the sign of the temperature (0 = negative, 1 = positive).
* The second byte is the magnitude.
*******************************************************************************/
uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
#if(CYDEV_ECC_ENABLE == 0)
static uint8 * rowBuffer = 0;
#endif /* (CYDEV_ECC_ENABLE == 0) */
static cystatus CySetTempInt(void);
/*******************************************************************************
* Function Name: CyFlash_Start
********************************************************************************
*
* Summary:
* Enable the EEPROM/Flash.
*
* Note: For PSoC 5, this will enable both Flash and EEPROM. For PSoC 3 and
* PSOC 5LP this will enable only Flash.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyFlash_Start(void)
{
#if(CY_PSOC5A)
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;
#endif /* (CY_PSOC5A) */
#if(CY_PSOC3 || CY_PSOC5LP)
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
}
/*******************************************************************************
* Function Name: CyFlash_Stop
********************************************************************************
*
* Summary:
* Disable the EEPROM/Flash.
*
* Note:
* PSoC 5: disable both Flash and EEPROM.
* PSoC 3 and PSOC 5LP: disable only Flash. Use CyEEPROM_Stop() to stop EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
* Side Effects:
* This setting is ignored as long as the CPU is currently running. This will
* only take effect when the CPU is later disabled.
*
*******************************************************************************/
void CyFlash_Stop(void)
{
#if (CY_PSOC5A)
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
}
/*******************************************************************************
* Function Name: CySetTempInt
********************************************************************************
*
* Summary:
* Sends a command to the SPC to read the die temperature. Sets a global value
* used by the Write functions. This function must be called once before
* executing a series of Flash writing functions.
*
* Parameters:
* None
*
* Return:
* status:
* CYRET_SUCCESS - if successful
* CYRET_LOCKED - if Flash writing already in use
* CYRET_UNKNOWN - if there was an SPC error
*
*******************************************************************************/
static cystatus CySetTempInt(void)
{
cystatus status;
/* Make sure SPC is powered */
CySpcStart();
/* Plan for failure. */
status = CYRET_UNKNOWN;
if(CySpcLock() == CYRET_SUCCESS)
{
/* Write the command. */
#if(CY_PSOC5A)
if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES, CY_TEMP_TIMER_PERIOD, CY_TEMP_CLK_DIV_SELECT))
#else
if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
#endif /* (CY_PSOC5A) */
{
do
{
if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
{
status = CYRET_SUCCESS;
while(CY_SPC_BUSY)
{
/* Spin until idle. */
CyDelayUs(1u);
}
break;
}
} while(CY_SPC_BUSY);
}
CySpcUnlock();
}
else
{
status = CYRET_LOCKED;
}
return (status);
}
/*******************************************************************************
* Function Name: CySetTemp
********************************************************************************
*
* Summary:
* This is a wraparound for CySetTempInt(). It is used to return second
* successful read of temperature value.
*
* Parameters:
* None
*
* Return:
* status:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if Flash writing already in use
* CYRET_UNKNOWN if there was an SPC error.
*
* uint8 dieTemperature[2]:
* Holds die temperature for the flash writting algorithm. The first byte is
* the sign of the temperature (0 = negative, 1 = positive). The second byte is
* the magnitude.
*
*******************************************************************************/
cystatus CySetTemp(void)
{
cystatus status = CySetTempInt();
if(status == CYRET_SUCCESS)
{
status = CySetTempInt();
}
return (status);
}
/*******************************************************************************
* Function Name: CySetFlashEEBuffer
********************************************************************************
*
* Summary:
* Sets the user supplied temporary buffer to store SPC data while performing
* flash and EEPROM commands. This buffer is only necessary when Flash ECC is
* disabled.
*
* Parameters:
* buffer:
* Address of block of memory to store temporary memory. The size of the block
* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
*
* Return:
* status:
* CYRET_SUCCESS if successful.
* CYRET_BAD_PARAM if the buffer is NULL
*
*******************************************************************************/
cystatus CySetFlashEEBuffer(uint8 * buffer)
{
cystatus status = CYRET_SUCCESS;
CySpcStart();
#if(CYDEV_ECC_ENABLE == 0)
if(NULL == buffer)
{
status = CYRET_BAD_PARAM;
}
else if(CySpcLock() != CYRET_SUCCESS)
{
status = CYRET_LOCKED;
}
else
{
rowBuffer = buffer;
CySpcUnlock();
}
#else
/* To supress the warning */
buffer = buffer;
#endif /* (CYDEV_ECC_ENABLE == 0u) */
return(status);
}
#if(CYDEV_ECC_ENABLE == 1)
/*******************************************************************************
* Function Name: CyWriteRowData
********************************************************************************
*
* Summary:
* Sends a command to the SPC to load and program a row of data in flash.
*
* Parameters:
* arrayID:
* ID of the array to write.
* rowAddress:
* rowAddress of flash row to program.
* rowData:
* Array of bytes to write.
*
* Return:
* status:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
{
uint16 rowSize;
cystatus status;
rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
return(status);
}
#else
/*******************************************************************************
* Function Name: CyWriteRowData
********************************************************************************
*
* Summary:
* Sends a command to the SPC to load and program a row of data in flash.
*
* Parameters:
* arrayID : ID of the array to write.
* rowAddress : rowAddress of flash row to program.
* rowData : Array of bytes to write.
*
* Return:
* status:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
{
uint8 i;
uint32 offset;
uint16 rowSize;
cystatus status;
rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? \
CYDEV_EEPROM_ROW_SIZE : \
(CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
if(rowSize != CYDEV_EEPROM_ROW_SIZE)
{
/* Save the ECC area. */
offset = CYDEV_ECC_BASE + ((uint32) arrayId * CYDEV_ECC_SECTOR_SIZE) +
((uint32) rowAddress * CYDEV_ECC_ROW_SIZE);
for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
{
*(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
}
}
/* Copy the rowdata to the temporary buffer. */
#if(CY_PSOC3)
(void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
#else
(void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
#endif /* (CY_PSOC3) */
status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
return(status);
}
#endif /* (CYDEV_ECC_ENABLE == 0u) */
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
/*******************************************************************************
* Function Name: CyWriteRowConfig
********************************************************************************
*
* Summary:
* Sends a command to the SPC to load and program a row of config data in flash.
* This function is only valid for Flash array IDs (not for EEPROM).
*
* Parameters:
* arrayId:
* ID of the array to write
* rowAddress:
* Address of the sector to erase.
* rowECC:
* Array of bytes to write.
*
* Return:
* status:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)
{
uint32 offset;
uint16 i;
cystatus status;
/* Read the existing flash data. */
offset = ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) +
((uint32) rowAddress * CYDEV_FLS_ROW_SIZE);
#if (CYDEV_FLS_BASE != 0u)
offset += CYDEV_FLS_BASE;
#endif
for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
{
rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
}
#if(CY_PSOC3)
(void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *)((uint32)rowECC), (int16) CYDEV_ECC_ROW_SIZE);
#else
(void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (const void *) rowECC, CYDEV_ECC_ROW_SIZE);
#endif /* (CY_PSOC3) */
status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
return (status);
}
#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
/*******************************************************************************
* Function Name: CyWriteRowFull
********************************************************************************
* Summary:
* Sends a command to the SPC to load and program a row of data in flash.
* rowData array is expected to contain Flash and ECC data if needed.
*
* Parameters:
* arrayId: FLASH or EEPROM array id.
* rowData: pointer to a row of data to write.
* rowNumber: Zero based number of the row.
* rowSize: Size of the row.
*
* Return:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
{
cystatus status;
if(CySpcLock() == CYRET_SUCCESS)
{
/* Load row data into SPC internal latch */
status = CySpcLoadRow(arrayId, rowData, rowSize);
if(CYRET_STARTED == status)
{
while(CY_SPC_BUSY)
{
/* Wait for SPC to finish and get SPC status */
CyDelayUs(1u);
}
/* Hide SPC status */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
else
{
status = CYRET_UNKNOWN;
}
if(CYRET_SUCCESS == status)
{
/* Erase and program flash with the data from SPC interval latch */
status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
if(CYRET_STARTED == status)
{
while(CY_SPC_BUSY)
{
/* Wait for SPC to finish and get SPC status */
CyDelayUs(1u);
}
/* Hide SPC status */
if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
status = CYRET_SUCCESS;
}
else
{
status = CYRET_UNKNOWN;
}
}
}
}
CySpcUnlock();
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CyFlash_SetWaitCycles
********************************************************************************
*
* Summary:
* Sets the number of clock cycles the cache will wait before it samples data
* coming back from Flash. This function must be called before increasing CPU
* clock frequency. It can optionally be called after lowering CPU clock
* frequency in order to improve CPU performance.
*
* Parameters:
* uint8 freq:
* Frequency of operation in Megahertz.
*
* Return:
* None
*
*******************************************************************************/
void CyFlash_SetWaitCycles(uint8 freq)
{
uint8 interruptState;
/* Save current global interrupt enable and disable it */
interruptState = CyEnterCriticalSection();
/***************************************************************************
* The number of clock cycles the cache will wait before it samples data
* coming back from Flash must be equal or greater to to the CPU frequency
* outlined in clock cycles.
***************************************************************************/
#if (CY_PSOC3)
if (freq <= 22u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else if (freq <= 44u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
#endif /* (CY_PSOC3) */
#if (CY_PSOC5A)
if (freq <= 16u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else if (freq <= 33u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else if (freq <= 50u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
#endif /* (CY_PSOC5A) */
#if (CY_PSOC5LP)
if (freq <= 16u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else if (freq <= 33u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else if (freq <= 50u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
#endif /* (CY_PSOC5LP) */
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
}
#if (CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: CyEEPROM_Start
********************************************************************************
*
* Summary:
* Enable the EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyEEPROM_Start(void)
{
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
}
/*******************************************************************************
* Function Name: CyEEPROM_Stop
********************************************************************************
*
* Summary:
* Disable the EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyEEPROM_Stop (void)
{
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
}
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/*******************************************************************************
* Function Name: CyEEPROM_ReadReserve
********************************************************************************
*
* Summary:
* Request access to the EEPROM for reading and wait until access is available.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyEEPROM_ReadReserve(void)
{
/* Make a request for PHUB to have access */
*CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;
while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))
{
/* Wait for acknowledgement from PHUB */
}
}
/*******************************************************************************
* Function Name: CyEEPROM_ReadRelease
********************************************************************************
*
* Summary:
* Release the read reservation of the EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyEEPROM_ReadRelease(void)
{
*CY_FLASH_EE_SCR_PTR |= 0x00u;
}
/* [] END OF FILE */

311
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/*******************************************************************************
* File Name: CyFlash.h
* Version 3.40
*
* Description:
* Provides the function definitions for the FLASH/EEPROM.
*
* Note:
* Documentation of the API's in this file is located in the
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_BOOT_CYFLASH_H)
#define CY_BOOT_CYFLASH_H
#include "cydevice_trm.h"
#include "cytypes.h"
#include "CyLib.h"
#include "CySpc.h"
#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */
extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
/***************************************
* API Constants
***************************************/
#define CY_FLASH_BASE (CYDEV_FLASH_BASE)
#define CY_FLASH_SIZE (CYDEV_FLS_SIZE)
#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE)
#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE)
#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE)
#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
#define CY_EEPROM_BASE (CYDEV_EE_BASE)
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)
#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)
#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
#if !defined(CYDEV_FLS_BASE)
#define CYDEV_FLS_BASE CYDEV_FLASH_BASE
#endif /* !defined(CYDEV_FLS_BASE) */
/***************************************
* Function Prototypes
***************************************/
/* Flash Functions */
void CyFlash_Start(void);
void CyFlash_Stop(void);
cystatus CySetTemp(void);
cystatus CySetFlashEEBuffer(uint8 * buffer);
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \
;
cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData);
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \
;
#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
void CyFlash_SetWaitCycles(uint8 freq) ;
/* EEPROM Functions */
#if (CY_PSOC3 || CY_PSOC5LP)
void CyEEPROM_Start(void) ;
void CyEEPROM_Stop(void) ;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
void CyEEPROM_ReadReserve(void) ;
void CyEEPROM_ReadRelease(void) ;
/***************************************
* Registers
***************************************/
#if (CY_PSOC5A)
/* Active Power Mode Configuration Register 0 */
#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG0)
#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
/* Alternate Active Power Mode Configuration Register 0 */
#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG0)
#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Active Power Mode Configuration Register 12 */
#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
/* Alternate Active Power Mode Configuration Register 12 */
#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/* Cache Control Register */
#if (CY_PSOC3)
#define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR )
#define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR )
#else
#define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL )
#define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL )
#endif /* (CY_PSOC3) */
/* EEPROM Status & Control Register */
#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR)
#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR)
/***************************************
* Register Constants
***************************************/
/* Power Mode Masks */
#if(CY_PSOC5A)
#define CY_FLASH_PM_FLASH_EE_MASK (0x80u)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
#define CY_FLASH_PM_EE_MASK (0x10u)
#define CY_FLASH_PM_FLASH_MASK (0x01u)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/* Frequency Constants */
#if (CY_PSOC3)
#define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)
#define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)
#define CY_FLASH_GREATER_44MHz (0x03u)
#endif /* (CY_PSOC3) */
#if (CY_PSOC5A)
#define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
#define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
#define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
#define CY_FLASH_GREATER_51MHz (0x00u)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC5LP)
#define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
#define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
#define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
#define CY_FLASH_GREATER_51MHz (0x00u)
#endif /* (CY_PSOC5LP) */
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
#define CY_FLASH_EE_STARTUP_DELAY (5u)
#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u)
#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u)
/* Default values for getting temperature. */
#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u)
#define CY_TEMP_TIMER_PERIOD (0xFFFu)
#define CY_TEMP_CLK_DIV_SELECT (0x4u)
#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES))
#define CY_SPC_CLK_PERIOD (120u) /* nS */
#define CY_SYS_ns_PER_TICK (1000u)
#define CY_FRM_EXEC_TIME (1000u) /* nS */
#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \
(CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \
CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME)
#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */
/*******************************************************************************
* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
*******************************************************************************/
#define FLASH_SIZE (CY_FLASH_SIZE)
#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY)
#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS)
#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS)
#define EEPROM_SIZE (CY_EEPROM_SIZE)
#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)
#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)
#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)
#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)
/*******************************************************************************
* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
*******************************************************************************/
#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR)
#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES)
#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD)
#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT)
#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES)
#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD)
#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME)
#define GET_TEMP_TIME (CY_GET_TEMP_TIME)
#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT)
#define ECC_ADDR (0x80u)
#if (CY_PSOC5A)
#define PM_ACT_EEFLASH (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_STBY_EEFLASH (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#if(CY_PSOC5A)
#define PM_FLASH_EE_MASK (CY_FLASH_PM_FLASH_EE_MASK)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
#define PM_EE_MASK (CY_FLASH_PM_EE_MASK)
#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT)
#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK)
#if (CY_PSOC3)
#define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz)
#define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz)
#define GREATER_44MHz (CY_FLASH_GREATER_44MHz)
#endif /* (CY_PSOC3) */
#if (CY_PSOC5A)
#define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)
#define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)
#define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz)
#define GREATER_51MHz (CY_FLASH_GREATER_51MHz)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC5LP)
#define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)
#define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)
#define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz)
#define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz)
#define GREATER_67MHz (CY_FLASH_GREATER_67MHz)
#define GREATER_51MHz (CY_FLASH_GREATER_51MHz)
#endif /* (CY_PSOC5LP) */
#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR)
#endif /* (CY_BOOT_CYFLASH_H) */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: CySpc.c
* Version 3.40
*
* Description:
* Provides an API for the System Performance Component.
* The SPC functions are not meant to be called directly by the user
* application.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "CySpc.h"
#define CY_SPC_KEY_ONE (0xB6u)
#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x))))
/* Command Codes */
#define CY_SPC_CMD_LD_BYTE (0x00u)
#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u)
#define CY_SPC_CMD_LD_ROW (0x02u)
#define CY_SPC_CMD_RD_BYTE (0x03u)
#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u)
#define CY_SPC_CMD_WR_ROW (0x05u)
#define CY_SPC_CMD_WR_USER_NVL (0x06u)
#define CY_SPC_CMD_PRG_ROW (0x07u)
#define CY_SPC_CMD_ER_SECTOR (0x08u)
#define CY_SPC_CMD_ER_ALL (0x09u)
#define CY_SPC_CMD_RD_HIDDEN (0x0Au)
#define CY_SPC_CMD_PRG_PROTECT (0x0Bu)
#define CY_SPC_CMD_CHECKSUM (0x0Cu)
#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du)
#define CY_SPC_CMD_GET_TEMP (0x0Eu)
#define CY_SPC_CMD_GET_ADC (0x0Fu)
#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u)
#define CY_SPC_CMD_SETUP_TS (0x11u)
#define CY_SPC_CMD_DISABLE_TS (0x12u)
#define CY_SPC_CMD_ER_ROW (0x13u)
/* Enable bit in Active and Alternate Active mode templates */
#define PM_SPC_PM_EN (0x08u)
/* Gate calls to the SPC. */
uint8 SpcLockState = CY_SPC_UNLOCKED;
#if(CY_PSOC5LP)
/***************************************************************************
* The wait-state pipeline must be enabled prior to accessing the SPC
* register interface regardless of CPU frequency. The CySpcLock() saves
* current wait-state pipeline state and enables it. The CySpcUnlock()
* function, which must be called after SPC transaction, restores original
* state.
***************************************************************************/
static uint8 spcWaitPipeBypass = 0u;
#endif /* (CY_PSOC5LP) */
/*******************************************************************************
* Function Name: CySpcStart
********************************************************************************
* Summary:
* Starts the SPC.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CySpcStart(void)
{
/* Save current global interrupt enable and disable it */
uint8 interruptState = CyEnterCriticalSection();
CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN;
CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN;
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CySpcStop
********************************************************************************
* Summary:
* Stops the SPC.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CySpcStop(void)
{
/* Save current global interrupt enable and disable it */
uint8 interruptState = CyEnterCriticalSection();
CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN));
CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN));
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: CySpcReadData
********************************************************************************
* Summary:
* Reads data from the SPC.
*
* Parameters:
* uint8 buffer:
* Address to store data read.
*
* uint8 size:
* Number of bytes to read from the SPC.
*
* Return:
* uint8:
* The number of bytes read from the SPC.
*
*******************************************************************************/
uint8 CySpcReadData(uint8 buffer[], uint8 size)
{
uint8 i;
for(i = 0u; i < size; i++)
{
while(!CY_SPC_DATA_READY)
{
CyDelayUs(1u);
}
buffer[i] = CY_SPC_CPU_DATA_REG;
}
return(i);
}
/*******************************************************************************
* Function Name: CySpcLoadMultiByte
********************************************************************************
* Summary:
* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array.
*
* Parameters:
* uint8 array:
* Id of the array.
*
* uint16 address:
* Flash/eeprom addrress
*
* uint8* buffer:
* Data to load to the row latch
*
* uint16 number:
* Number bytes to load.
*
* Return:
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
* CYRET_BAD_PARAM
*
*******************************************************************************/
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)
{
cystatus status = CYRET_STARTED;
uint8 i;
/***************************************************************************
* Check if number is correct for array. Number must be less than
* 32 for Flash or less than 16 for EEPROM.
***************************************************************************/
if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) ||
((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u)))
{
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE;
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
CY_SPC_CPU_DATA_REG = 1u & HI8(address);
CY_SPC_CPU_DATA_REG = LO8(address);
CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u));
for(i = 0u; i < size; i++)
{
CY_SPC_CPU_DATA_REG = buffer[i];
}
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
}
else
{
status = CYRET_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcLoadRow
********************************************************************************
* Summary:
* Loads a row of data into the row latch of a Flash/EEPROM array.
*
* Parameters:
* uint8 array:
* Id of the array.
*
* uint8* buffer:
* Data to be loaded to the row latch
*
* uint8 size:
* The number of data bytes that the SPC expects to be written. Depends on the
* type of the array and, if the array is Flash, whether ECC is being enabled
* or not. There are following values: flash row latch size with ECC enabled,
* flash row latch size with ECC disabled and EEPROM row latch size.
*
* Return:
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
{
cystatus status = CYRET_STARTED;
uint16 i;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
for(i = 0u; i < size; i++)
{
CY_SPC_CPU_DATA_REG = buffer[i];
}
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcWriteRow
********************************************************************************
* Summary:
* Erases then programs a row in Flash/EEPROM with data in row latch.
*
* Parameters:
* uint8 array:
* Id of the array.
*
* uint16 address:
* flash/eeprom addrress
*
* uint8 tempPolarity:
* temperature polarity.
* 1: the Temp Magnitude is interpreted as a positive value
* 0: the Temp Magnitude is interpreted as a negative value
*
* uint8 tempMagnitude:
* temperature magnitude.
*
* Return:
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)
{
cystatus status = CYRET_STARTED;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
CY_SPC_CPU_DATA_REG = HI8(address);
CY_SPC_CPU_DATA_REG = LO8(address);
CY_SPC_CPU_DATA_REG = tempPolarity;
CY_SPC_CPU_DATA_REG = tempMagnitude;
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcEraseSector
********************************************************************************
* Summary:
* Erases all data in the addressed sector (block of 64 rows).
*
* Parameters:
* uint8 array:
* Id of the array.
*
* uint8 sectorNumber:
* Zero based sector number within Flash/EEPROM array
*
* Return:
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber)
{
cystatus status = CYRET_STARTED;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = array;
CY_SPC_CPU_DATA_REG = sectorNumber;
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcGetTemp
********************************************************************************
* Summary:
* Returns the internal die temperature
*
* Parameters:
* uint8 numSamples:
* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples
* respectively.
*
* uint16 timerPeriod:
* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits
* of 16 bit values are ignored.
*
* uint8 clkDivSelect:
* ADC ACLK clock divide value. Valid values are 2 - 225.
*
* Return:
* CYRET_STARTED
* CYRET_CANCELED
* CYRET_LOCKED
*
*******************************************************************************/
#if(CY_PSOC5A)
cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect)
#else
cystatus CySpcGetTemp(uint8 numSamples)
#endif /* (CY_PSOC5A) */
{
cystatus status = CYRET_STARTED;
/* Make sure the SPC is ready to accept command */
if(CY_SPC_IDLE)
{
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP);
CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP;
/* Make sure the command was accepted */
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = numSamples;
#if(CY_PSOC5A)
CY_SPC_CPU_DATA_REG = HI8(timerPeriod);
CY_SPC_CPU_DATA_REG = LO8(timerPeriod);
CY_SPC_CPU_DATA_REG = clkDivSelect;
#endif /* (CY_PSOC5A) */
}
else
{
status = CYRET_CANCELED;
}
}
else
{
status = CYRET_LOCKED;
}
return(status);
}
/*******************************************************************************
* Function Name: CySpcLock
********************************************************************************
* Summary:
* Locks the SPC so it can not be used by someone else:
* - Saves wait-pipeline enable state and enable pipeline (PSoC5)
*
* Parameters:
* Note
*
* Return:
* CYRET_SUCCESS - if the resource was free.
* CYRET_LOCKED - if the SPC is in use.
*
*******************************************************************************/
cystatus CySpcLock(void)
{
cystatus status = CYRET_LOCKED;
uint8 interruptState;
/* Enter critical section */
interruptState = CyEnterCriticalSection();
if(CY_SPC_UNLOCKED == SpcLockState)
{
SpcLockState = CY_SPC_LOCKED;
status = CYRET_SUCCESS;
#if(CY_PSOC5LP)
if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS))
{
/* Enable pipeline registers */
CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS));
/* At least 2 NOP instructions are recommended */
CY_NOP;
CY_NOP;
CY_NOP;
spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS;
}
#endif /* (CY_PSOC5LP) */
}
/* Exit critical section */
CyExitCriticalSection(interruptState);
return(status);
}
/*******************************************************************************
* Function Name: CySpcUnlock
********************************************************************************
* Summary:
* Unlocks the SPC so it can be used by someone else:
* - Restores wait-pipeline enable state (PSoC5)
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CySpcUnlock(void)
{
uint8 interruptState;
/* Enter critical section */
interruptState = CyEnterCriticalSection();
/* Release the SPC object */
SpcLockState = CY_SPC_UNLOCKED;
#if(CY_PSOC5LP)
if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass)
{
/* Force to bypass pipeline registers */
CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS;
/* At least 2 NOP instructions are recommended */
CY_NOP;
CY_NOP;
CY_NOP;
spcWaitPipeBypass = 0u;
}
#endif /* (CY_PSOC5LP) */
/* Exit critical section */
CyExitCriticalSection(interruptState);
}
/* [] END OF FILE */

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/*******************************************************************************
* File Name: CySpc.c
* Version 3.40
*
* Description:
* Provides definitions for the System Performance Component API.
* The SPC functions are not meant to be called directly by the user
* application.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_BOOT_CYSPC_H)
#define CY_BOOT_CYSPC_H
#include "cytypes.h"
#include "CyLib.h"
#include "cydevice_trm.h"
/***************************************
* Global Variables
***************************************/
extern uint8 SpcLockState;
/***************************************
* Function Prototypes
***************************************/
void CySpcStart(void);
void CySpcStop(void);
uint8 CySpcReadData(uint8 buffer[], uint8 size);
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) ;
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude) ;
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
#if(CY_PSOC5A)
cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect);
#else
cystatus CySpcGetTemp(uint8 numSamples);
#endif /* (CY_PSOC5A) */
cystatus CySpcLock(void);
void CySpcUnlock(void);
/***************************************
* API Constants
***************************************/
#define CY_SPC_LOCKED (0x01u)
#define CY_SPC_UNLOCKED (0x00u)
/*******************************************************************************
* The Array ID indicates the unique ID of the SONOS array being accessed:
* - 0x00-0x3E : Flash Arrays
* - 0x3F : Selects all Flash arrays simultaneously
* - 0x40-0x7F : Embedded EEPROM Arrays
*******************************************************************************/
#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u)
#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu)
#define CY_SPC_FIRST_EE_ARRAYID (0x40u)
#define CY_SPC_LAST_EE_ARRAYID (0x7Fu)
#define CY_SPC_STATUS_DATA_READY_MASK (0x01u)
#define CY_SPC_STATUS_IDLE_MASK (0x02u)
#define CY_SPC_STATUS_CODE_MASK (0xFCu)
#define CY_SPC_STATUS_CODE_SHIFT (0x02u)
/* Status codes for the SPC. */
#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */
#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */
#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */
#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */
#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */
#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */
#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */
#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */
#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */
#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */
#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */
#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */
#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */
#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */
#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */
#if(CY_PSOC5LP)
/* Wait-state pipeline */
#define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u)
#endif /* (CY_PSOC5LP) */
/***************************************
* Registers
***************************************/
/* SPC CPU Data Register */
#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA )
#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA )
/* SPC Status Register */
#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR )
#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR )
/* Active Power Mode Configuration Register 0 */
#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 )
#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 )
/* Standby Power Mode Configuration Register 0 */
#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 )
#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 )
#if(CY_PSOC5LP)
/* Wait State Pipeline */
#define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE )
#define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE )
#endif /* (CY_PSOC5LP) */
/***************************************
* Macros
***************************************/
#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK))
/* SPC must be in idle state in order to obtain correct status */
#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \
((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \
((uint8) CY_SPC_STATUS_BUSY))
/*******************************************************************************
* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
*******************************************************************************/
#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID)
#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID)
#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID)
#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID)
#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE)
#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE)
#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE)
#endif /* (CY_BOOT_CYSPC_H) */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: LED1.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "LED1.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: LED1_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void LED1_Write(uint8 value)
{
uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK));
LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK);
}
/*******************************************************************************
* Function Name: LED1_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void LED1_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(LED1_0, mode);
}
/*******************************************************************************
* Function Name: LED1_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro LED1_ReadPS calls this function.
*
*******************************************************************************/
uint8 LED1_Read(void)
{
return (LED1_PS & LED1_MASK) >> LED1_SHIFT;
}
/*******************************************************************************
* Function Name: LED1_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 LED1_ReadDataReg(void)
{
return (LED1_DR & LED1_MASK) >> LED1_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(LED1_INTSTAT)
/*******************************************************************************
* Function Name: LED1_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 LED1_ClearInterrupt(void)
{
return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: LED1.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_LED1_H) /* Pins LED1_H */
#define CY_PINS_LED1_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "LED1_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void LED1_Write(uint8 value) ;
void LED1_SetDriveMode(uint8 mode) ;
uint8 LED1_ReadDataReg(void) ;
uint8 LED1_Read(void) ;
uint8 LED1_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define LED1_DM_RES_UP PIN_DM_RES_UP
#define LED1_DM_RES_DWN PIN_DM_RES_DWN
#define LED1_DM_OD_LO PIN_DM_OD_LO
#define LED1_DM_OD_HI PIN_DM_OD_HI
#define LED1_DM_STRONG PIN_DM_STRONG
#define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define LED1_MASK LED1__MASK
#define LED1_SHIFT LED1__SHIFT
#define LED1_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define LED1_PS (* (reg8 *) LED1__PS)
/* Data Register */
#define LED1_DR (* (reg8 *) LED1__DR)
/* Port Number */
#define LED1_PRT_NUM (* (reg8 *) LED1__PRT)
/* Connect to Analog Globals */
#define LED1_AG (* (reg8 *) LED1__AG)
/* Analog MUX bux enable */
#define LED1_AMUX (* (reg8 *) LED1__AMUX)
/* Bidirectional Enable */
#define LED1_BIE (* (reg8 *) LED1__BIE)
/* Bit-mask for Aliased Register Access */
#define LED1_BIT_MASK (* (reg8 *) LED1__BIT_MASK)
/* Bypass Enable */
#define LED1_BYP (* (reg8 *) LED1__BYP)
/* Port wide control signals */
#define LED1_CTL (* (reg8 *) LED1__CTL)
/* Drive Modes */
#define LED1_DM0 (* (reg8 *) LED1__DM0)
#define LED1_DM1 (* (reg8 *) LED1__DM1)
#define LED1_DM2 (* (reg8 *) LED1__DM2)
/* Input Buffer Disable Override */
#define LED1_INP_DIS (* (reg8 *) LED1__INP_DIS)
/* LCD Common or Segment Drive */
#define LED1_LCD_COM_SEG (* (reg8 *) LED1__LCD_COM_SEG)
/* Enable Segment LCD */
#define LED1_LCD_EN (* (reg8 *) LED1__LCD_EN)
/* Slew Rate Control */
#define LED1_SLW (* (reg8 *) LED1__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define LED1_PRTDSI__CAPS_SEL (* (reg8 *) LED1__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define LED1_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED1__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define LED1_PRTDSI__OE_SEL0 (* (reg8 *) LED1__PRTDSI__OE_SEL0)
#define LED1_PRTDSI__OE_SEL1 (* (reg8 *) LED1__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define LED1_PRTDSI__OUT_SEL0 (* (reg8 *) LED1__PRTDSI__OUT_SEL0)
#define LED1_PRTDSI__OUT_SEL1 (* (reg8 *) LED1__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT)
#if defined(LED1__INTSTAT) /* Interrupt Registers */
#define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT)
#define LED1_SNAP (* (reg8 *) LED1__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_LED1_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: LED1.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_LED1_ALIASES_H) /* Pins LED1_ALIASES_H */
#define CY_PINS_LED1_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define LED1_0 LED1__0__PC
#endif /* End Pins LED1_ALIASES_H */
/* [] END OF FILE */

137
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/*******************************************************************************
* File Name: PARITY_EN.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "PARITY_EN.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: PARITY_EN_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void PARITY_EN_Write(uint8 value)
{
uint8 staticBits = (PARITY_EN_DR & (uint8)(~PARITY_EN_MASK));
PARITY_EN_DR = staticBits | ((uint8)(value << PARITY_EN_SHIFT) & PARITY_EN_MASK);
}
/*******************************************************************************
* Function Name: PARITY_EN_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void PARITY_EN_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(PARITY_EN_0, mode);
}
/*******************************************************************************
* Function Name: PARITY_EN_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro PARITY_EN_ReadPS calls this function.
*
*******************************************************************************/
uint8 PARITY_EN_Read(void)
{
return (PARITY_EN_PS & PARITY_EN_MASK) >> PARITY_EN_SHIFT;
}
/*******************************************************************************
* Function Name: PARITY_EN_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 PARITY_EN_ReadDataReg(void)
{
return (PARITY_EN_DR & PARITY_EN_MASK) >> PARITY_EN_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(PARITY_EN_INTSTAT)
/*******************************************************************************
* Function Name: PARITY_EN_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 PARITY_EN_ClearInterrupt(void)
{
return (PARITY_EN_INTSTAT & PARITY_EN_MASK) >> PARITY_EN_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: PARITY_EN.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_PARITY_EN_H) /* Pins PARITY_EN_H */
#define CY_PINS_PARITY_EN_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "PARITY_EN_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void PARITY_EN_Write(uint8 value) ;
void PARITY_EN_SetDriveMode(uint8 mode) ;
uint8 PARITY_EN_ReadDataReg(void) ;
uint8 PARITY_EN_Read(void) ;
uint8 PARITY_EN_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define PARITY_EN_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define PARITY_EN_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define PARITY_EN_DM_RES_UP PIN_DM_RES_UP
#define PARITY_EN_DM_RES_DWN PIN_DM_RES_DWN
#define PARITY_EN_DM_OD_LO PIN_DM_OD_LO
#define PARITY_EN_DM_OD_HI PIN_DM_OD_HI
#define PARITY_EN_DM_STRONG PIN_DM_STRONG
#define PARITY_EN_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define PARITY_EN_MASK PARITY_EN__MASK
#define PARITY_EN_SHIFT PARITY_EN__SHIFT
#define PARITY_EN_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define PARITY_EN_PS (* (reg8 *) PARITY_EN__PS)
/* Data Register */
#define PARITY_EN_DR (* (reg8 *) PARITY_EN__DR)
/* Port Number */
#define PARITY_EN_PRT_NUM (* (reg8 *) PARITY_EN__PRT)
/* Connect to Analog Globals */
#define PARITY_EN_AG (* (reg8 *) PARITY_EN__AG)
/* Analog MUX bux enable */
#define PARITY_EN_AMUX (* (reg8 *) PARITY_EN__AMUX)
/* Bidirectional Enable */
#define PARITY_EN_BIE (* (reg8 *) PARITY_EN__BIE)
/* Bit-mask for Aliased Register Access */
#define PARITY_EN_BIT_MASK (* (reg8 *) PARITY_EN__BIT_MASK)
/* Bypass Enable */
#define PARITY_EN_BYP (* (reg8 *) PARITY_EN__BYP)
/* Port wide control signals */
#define PARITY_EN_CTL (* (reg8 *) PARITY_EN__CTL)
/* Drive Modes */
#define PARITY_EN_DM0 (* (reg8 *) PARITY_EN__DM0)
#define PARITY_EN_DM1 (* (reg8 *) PARITY_EN__DM1)
#define PARITY_EN_DM2 (* (reg8 *) PARITY_EN__DM2)
/* Input Buffer Disable Override */
#define PARITY_EN_INP_DIS (* (reg8 *) PARITY_EN__INP_DIS)
/* LCD Common or Segment Drive */
#define PARITY_EN_LCD_COM_SEG (* (reg8 *) PARITY_EN__LCD_COM_SEG)
/* Enable Segment LCD */
#define PARITY_EN_LCD_EN (* (reg8 *) PARITY_EN__LCD_EN)
/* Slew Rate Control */
#define PARITY_EN_SLW (* (reg8 *) PARITY_EN__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define PARITY_EN_PRTDSI__CAPS_SEL (* (reg8 *) PARITY_EN__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define PARITY_EN_PRTDSI__DBL_SYNC_IN (* (reg8 *) PARITY_EN__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define PARITY_EN_PRTDSI__OE_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL0)
#define PARITY_EN_PRTDSI__OE_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define PARITY_EN_PRTDSI__OUT_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL0)
#define PARITY_EN_PRTDSI__OUT_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define PARITY_EN_PRTDSI__SYNC_OUT (* (reg8 *) PARITY_EN__PRTDSI__SYNC_OUT)
#if defined(PARITY_EN__INTSTAT) /* Interrupt Registers */
#define PARITY_EN_INTSTAT (* (reg8 *) PARITY_EN__INTSTAT)
#define PARITY_EN_SNAP (* (reg8 *) PARITY_EN__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_PARITY_EN_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: PARITY_EN.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_PARITY_EN_ALIASES_H) /* Pins PARITY_EN_ALIASES_H */
#define CY_PINS_PARITY_EN_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define PARITY_EN_0 PARITY_EN__0__PC
#endif /* End Pins PARITY_EN_ALIASES_H */
/* [] END OF FILE */

34
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ID_aliases.h Normal file
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/*******************************************************************************
* File Name: SCSI_ID.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_ID_ALIASES_H) /* Pins SCSI_ID_ALIASES_H */
#define CY_PINS_SCSI_ID_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_ID_0 SCSI_ID__0__PC
#define SCSI_ID_1 SCSI_ID__1__PC
#define SCSI_ID_2 SCSI_ID__2__PC
#endif /* End Pins SCSI_ID_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_In_DBx.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SCSI_In_DBx.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SCSI_In_DBx__PORT == 15 && ((SCSI_In_DBx__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SCSI_In_DBx_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_In_DBx_Write(uint8 value)
{
uint8 staticBits = (SCSI_In_DBx_DR & (uint8)(~SCSI_In_DBx_MASK));
SCSI_In_DBx_DR = staticBits | ((uint8)(value << SCSI_In_DBx_SHIFT) & SCSI_In_DBx_MASK);
}
/*******************************************************************************
* Function Name: SCSI_In_DBx_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_In_DBx_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SCSI_In_DBx_0, mode);
CyPins_SetPinDriveMode(SCSI_In_DBx_1, mode);
CyPins_SetPinDriveMode(SCSI_In_DBx_2, mode);
CyPins_SetPinDriveMode(SCSI_In_DBx_3, mode);
CyPins_SetPinDriveMode(SCSI_In_DBx_4, mode);
CyPins_SetPinDriveMode(SCSI_In_DBx_5, mode);
CyPins_SetPinDriveMode(SCSI_In_DBx_6, mode);
CyPins_SetPinDriveMode(SCSI_In_DBx_7, mode);
}
/*******************************************************************************
* Function Name: SCSI_In_DBx_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SCSI_In_DBx_ReadPS calls this function.
*
*******************************************************************************/
uint8 SCSI_In_DBx_Read(void)
{
return (SCSI_In_DBx_PS & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;
}
/*******************************************************************************
* Function Name: SCSI_In_DBx_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SCSI_In_DBx_ReadDataReg(void)
{
return (SCSI_In_DBx_DR & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SCSI_In_DBx_INTSTAT)
/*******************************************************************************
* Function Name: SCSI_In_DBx_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SCSI_In_DBx_ClearInterrupt(void)
{
return (SCSI_In_DBx_INTSTAT & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_In_DBx.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_In_DBx_H) /* Pins SCSI_In_DBx_H */
#define CY_PINS_SCSI_In_DBx_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SCSI_In_DBx_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SCSI_In_DBx__PORT == 15 && ((SCSI_In_DBx__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SCSI_In_DBx_Write(uint8 value) ;
void SCSI_In_DBx_SetDriveMode(uint8 mode) ;
uint8 SCSI_In_DBx_ReadDataReg(void) ;
uint8 SCSI_In_DBx_Read(void) ;
uint8 SCSI_In_DBx_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SCSI_In_DBx_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SCSI_In_DBx_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SCSI_In_DBx_DM_RES_UP PIN_DM_RES_UP
#define SCSI_In_DBx_DM_RES_DWN PIN_DM_RES_DWN
#define SCSI_In_DBx_DM_OD_LO PIN_DM_OD_LO
#define SCSI_In_DBx_DM_OD_HI PIN_DM_OD_HI
#define SCSI_In_DBx_DM_STRONG PIN_DM_STRONG
#define SCSI_In_DBx_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SCSI_In_DBx_MASK SCSI_In_DBx__MASK
#define SCSI_In_DBx_SHIFT SCSI_In_DBx__SHIFT
#define SCSI_In_DBx_WIDTH 8u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SCSI_In_DBx_PS (* (reg8 *) SCSI_In_DBx__PS)
/* Data Register */
#define SCSI_In_DBx_DR (* (reg8 *) SCSI_In_DBx__DR)
/* Port Number */
#define SCSI_In_DBx_PRT_NUM (* (reg8 *) SCSI_In_DBx__PRT)
/* Connect to Analog Globals */
#define SCSI_In_DBx_AG (* (reg8 *) SCSI_In_DBx__AG)
/* Analog MUX bux enable */
#define SCSI_In_DBx_AMUX (* (reg8 *) SCSI_In_DBx__AMUX)
/* Bidirectional Enable */
#define SCSI_In_DBx_BIE (* (reg8 *) SCSI_In_DBx__BIE)
/* Bit-mask for Aliased Register Access */
#define SCSI_In_DBx_BIT_MASK (* (reg8 *) SCSI_In_DBx__BIT_MASK)
/* Bypass Enable */
#define SCSI_In_DBx_BYP (* (reg8 *) SCSI_In_DBx__BYP)
/* Port wide control signals */
#define SCSI_In_DBx_CTL (* (reg8 *) SCSI_In_DBx__CTL)
/* Drive Modes */
#define SCSI_In_DBx_DM0 (* (reg8 *) SCSI_In_DBx__DM0)
#define SCSI_In_DBx_DM1 (* (reg8 *) SCSI_In_DBx__DM1)
#define SCSI_In_DBx_DM2 (* (reg8 *) SCSI_In_DBx__DM2)
/* Input Buffer Disable Override */
#define SCSI_In_DBx_INP_DIS (* (reg8 *) SCSI_In_DBx__INP_DIS)
/* LCD Common or Segment Drive */
#define SCSI_In_DBx_LCD_COM_SEG (* (reg8 *) SCSI_In_DBx__LCD_COM_SEG)
/* Enable Segment LCD */
#define SCSI_In_DBx_LCD_EN (* (reg8 *) SCSI_In_DBx__LCD_EN)
/* Slew Rate Control */
#define SCSI_In_DBx_SLW (* (reg8 *) SCSI_In_DBx__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SCSI_In_DBx_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_In_DBx__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SCSI_In_DBx_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_In_DBx__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SCSI_In_DBx_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_In_DBx__PRTDSI__OE_SEL0)
#define SCSI_In_DBx_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_In_DBx__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SCSI_In_DBx_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_In_DBx__PRTDSI__OUT_SEL0)
#define SCSI_In_DBx_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_In_DBx__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SCSI_In_DBx_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_In_DBx__PRTDSI__SYNC_OUT)
#if defined(SCSI_In_DBx__INTSTAT) /* Interrupt Registers */
#define SCSI_In_DBx_INTSTAT (* (reg8 *) SCSI_In_DBx__INTSTAT)
#define SCSI_In_DBx_SNAP (* (reg8 *) SCSI_In_DBx__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SCSI_In_DBx_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_In_DBx.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_In_DBx_ALIASES_H) /* Pins SCSI_In_DBx_ALIASES_H */
#define CY_PINS_SCSI_In_DBx_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_In_DBx_0 SCSI_In_DBx__0__PC
#define SCSI_In_DBx_1 SCSI_In_DBx__1__PC
#define SCSI_In_DBx_2 SCSI_In_DBx__2__PC
#define SCSI_In_DBx_3 SCSI_In_DBx__3__PC
#define SCSI_In_DBx_4 SCSI_In_DBx__4__PC
#define SCSI_In_DBx_5 SCSI_In_DBx__5__PC
#define SCSI_In_DBx_6 SCSI_In_DBx__6__PC
#define SCSI_In_DBx_7 SCSI_In_DBx__7__PC
#define SCSI_In_DBx_SCSI_Out_DB0 SCSI_In_DBx__SCSI_Out_DB0__PC
#define SCSI_In_DBx_SCSI_Out_DB1 SCSI_In_DBx__SCSI_Out_DB1__PC
#define SCSI_In_DBx_SCSI_Out_DB2 SCSI_In_DBx__SCSI_Out_DB2__PC
#define SCSI_In_DBx_SCSI_Out_DB3 SCSI_In_DBx__SCSI_Out_DB3__PC
#define SCSI_In_DBx_SCSI_Out_DB4 SCSI_In_DBx__SCSI_Out_DB4__PC
#define SCSI_In_DBx_SCSI_Out_DB5 SCSI_In_DBx__SCSI_Out_DB5__PC
#define SCSI_In_DBx_SCSI_Out_DB6 SCSI_In_DBx__SCSI_Out_DB6__PC
#define SCSI_In_DBx_SCSI_Out_DB7 SCSI_In_DBx__SCSI_Out_DB7__PC
#endif /* End Pins SCSI_In_DBx_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_In.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_In_ALIASES_H) /* Pins SCSI_In_ALIASES_H */
#define CY_PINS_SCSI_In_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_In_0 SCSI_In__0__PC
#define SCSI_In_1 SCSI_In__1__PC
#define SCSI_In_2 SCSI_In__2__PC
#define SCSI_In_3 SCSI_In__3__PC
#define SCSI_In_4 SCSI_In__4__PC
#define SCSI_In_5 SCSI_In__5__PC
#define SCSI_In_6 SCSI_In__6__PC
#define SCSI_In_7 SCSI_In__7__PC
#define SCSI_In_8 SCSI_In__8__PC
#define SCSI_In_9 SCSI_In__9__PC
#define SCSI_In_DBP SCSI_In__DBP__PC
#define SCSI_In_ATN SCSI_In__ATN__PC
#define SCSI_In_BSY SCSI_In__BSY__PC
#define SCSI_In_ACK SCSI_In__ACK__PC
#define SCSI_In_RST SCSI_In__RST__PC
#define SCSI_In_MSG SCSI_In__MSG__PC
#define SCSI_In_SEL SCSI_In__SEL__PC
#define SCSI_In_CD SCSI_In__CD__PC
#define SCSI_In_REQ SCSI_In__REQ__PC
#define SCSI_In_IO SCSI_In__IO__PC
#endif /* End Pins SCSI_In_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_Out_DBx.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SCSI_Out_DBx.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SCSI_Out_DBx__PORT == 15 && ((SCSI_Out_DBx__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SCSI_Out_DBx_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Out_DBx_Write(uint8 value)
{
uint8 staticBits = (SCSI_Out_DBx_DR & (uint8)(~SCSI_Out_DBx_MASK));
SCSI_Out_DBx_DR = staticBits | ((uint8)(value << SCSI_Out_DBx_SHIFT) & SCSI_Out_DBx_MASK);
}
/*******************************************************************************
* Function Name: SCSI_Out_DBx_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_Out_DBx_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SCSI_Out_DBx_0, mode);
CyPins_SetPinDriveMode(SCSI_Out_DBx_1, mode);
CyPins_SetPinDriveMode(SCSI_Out_DBx_2, mode);
CyPins_SetPinDriveMode(SCSI_Out_DBx_3, mode);
CyPins_SetPinDriveMode(SCSI_Out_DBx_4, mode);
CyPins_SetPinDriveMode(SCSI_Out_DBx_5, mode);
CyPins_SetPinDriveMode(SCSI_Out_DBx_6, mode);
CyPins_SetPinDriveMode(SCSI_Out_DBx_7, mode);
}
/*******************************************************************************
* Function Name: SCSI_Out_DBx_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SCSI_Out_DBx_ReadPS calls this function.
*
*******************************************************************************/
uint8 SCSI_Out_DBx_Read(void)
{
return (SCSI_Out_DBx_PS & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;
}
/*******************************************************************************
* Function Name: SCSI_Out_DBx_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SCSI_Out_DBx_ReadDataReg(void)
{
return (SCSI_Out_DBx_DR & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SCSI_Out_DBx_INTSTAT)
/*******************************************************************************
* Function Name: SCSI_Out_DBx_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SCSI_Out_DBx_ClearInterrupt(void)
{
return (SCSI_Out_DBx_INTSTAT & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_Out_DBx.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_Out_DBx_H) /* Pins SCSI_Out_DBx_H */
#define CY_PINS_SCSI_Out_DBx_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SCSI_Out_DBx_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SCSI_Out_DBx__PORT == 15 && ((SCSI_Out_DBx__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SCSI_Out_DBx_Write(uint8 value) ;
void SCSI_Out_DBx_SetDriveMode(uint8 mode) ;
uint8 SCSI_Out_DBx_ReadDataReg(void) ;
uint8 SCSI_Out_DBx_Read(void) ;
uint8 SCSI_Out_DBx_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SCSI_Out_DBx_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SCSI_Out_DBx_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SCSI_Out_DBx_DM_RES_UP PIN_DM_RES_UP
#define SCSI_Out_DBx_DM_RES_DWN PIN_DM_RES_DWN
#define SCSI_Out_DBx_DM_OD_LO PIN_DM_OD_LO
#define SCSI_Out_DBx_DM_OD_HI PIN_DM_OD_HI
#define SCSI_Out_DBx_DM_STRONG PIN_DM_STRONG
#define SCSI_Out_DBx_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SCSI_Out_DBx_MASK SCSI_Out_DBx__MASK
#define SCSI_Out_DBx_SHIFT SCSI_Out_DBx__SHIFT
#define SCSI_Out_DBx_WIDTH 8u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SCSI_Out_DBx_PS (* (reg8 *) SCSI_Out_DBx__PS)
/* Data Register */
#define SCSI_Out_DBx_DR (* (reg8 *) SCSI_Out_DBx__DR)
/* Port Number */
#define SCSI_Out_DBx_PRT_NUM (* (reg8 *) SCSI_Out_DBx__PRT)
/* Connect to Analog Globals */
#define SCSI_Out_DBx_AG (* (reg8 *) SCSI_Out_DBx__AG)
/* Analog MUX bux enable */
#define SCSI_Out_DBx_AMUX (* (reg8 *) SCSI_Out_DBx__AMUX)
/* Bidirectional Enable */
#define SCSI_Out_DBx_BIE (* (reg8 *) SCSI_Out_DBx__BIE)
/* Bit-mask for Aliased Register Access */
#define SCSI_Out_DBx_BIT_MASK (* (reg8 *) SCSI_Out_DBx__BIT_MASK)
/* Bypass Enable */
#define SCSI_Out_DBx_BYP (* (reg8 *) SCSI_Out_DBx__BYP)
/* Port wide control signals */
#define SCSI_Out_DBx_CTL (* (reg8 *) SCSI_Out_DBx__CTL)
/* Drive Modes */
#define SCSI_Out_DBx_DM0 (* (reg8 *) SCSI_Out_DBx__DM0)
#define SCSI_Out_DBx_DM1 (* (reg8 *) SCSI_Out_DBx__DM1)
#define SCSI_Out_DBx_DM2 (* (reg8 *) SCSI_Out_DBx__DM2)
/* Input Buffer Disable Override */
#define SCSI_Out_DBx_INP_DIS (* (reg8 *) SCSI_Out_DBx__INP_DIS)
/* LCD Common or Segment Drive */
#define SCSI_Out_DBx_LCD_COM_SEG (* (reg8 *) SCSI_Out_DBx__LCD_COM_SEG)
/* Enable Segment LCD */
#define SCSI_Out_DBx_LCD_EN (* (reg8 *) SCSI_Out_DBx__LCD_EN)
/* Slew Rate Control */
#define SCSI_Out_DBx_SLW (* (reg8 *) SCSI_Out_DBx__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SCSI_Out_DBx_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_Out_DBx__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SCSI_Out_DBx_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SCSI_Out_DBx_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OE_SEL0)
#define SCSI_Out_DBx_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SCSI_Out_DBx_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OUT_SEL0)
#define SCSI_Out_DBx_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SCSI_Out_DBx_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_Out_DBx__PRTDSI__SYNC_OUT)
#if defined(SCSI_Out_DBx__INTSTAT) /* Interrupt Registers */
#define SCSI_Out_DBx_INTSTAT (* (reg8 *) SCSI_Out_DBx__INTSTAT)
#define SCSI_Out_DBx_SNAP (* (reg8 *) SCSI_Out_DBx__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SCSI_Out_DBx_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_Out_DBx.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */
#define CY_PINS_SCSI_Out_DBx_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC
#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC
#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC
#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC
#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC
#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC
#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC
#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC
#define SCSI_Out_DBx_SCSI_Out_DB0 SCSI_Out_DBx__SCSI_Out_DB0__PC
#define SCSI_Out_DBx_SCSI_Out_DB1 SCSI_Out_DBx__SCSI_Out_DB1__PC
#define SCSI_Out_DBx_SCSI_Out_DB2 SCSI_Out_DBx__SCSI_Out_DB2__PC
#define SCSI_Out_DBx_SCSI_Out_DB3 SCSI_Out_DBx__SCSI_Out_DB3__PC
#define SCSI_Out_DBx_SCSI_Out_DB4 SCSI_Out_DBx__SCSI_Out_DB4__PC
#define SCSI_Out_DBx_SCSI_Out_DB5 SCSI_Out_DBx__SCSI_Out_DB5__PC
#define SCSI_Out_DBx_SCSI_Out_DB6 SCSI_Out_DBx__SCSI_Out_DB6__PC
#define SCSI_Out_DBx_SCSI_Out_DB7 SCSI_Out_DBx__SCSI_Out_DB7__PC
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_Out.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */
#define CY_PINS_SCSI_Out_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_Out_0 SCSI_Out__0__PC
#define SCSI_Out_1 SCSI_Out__1__PC
#define SCSI_Out_2 SCSI_Out__2__PC
#define SCSI_Out_3 SCSI_Out__3__PC
#define SCSI_Out_4 SCSI_Out__4__PC
#define SCSI_Out_5 SCSI_Out__5__PC
#define SCSI_Out_6 SCSI_Out__6__PC
#define SCSI_Out_7 SCSI_Out__7__PC
#define SCSI_Out_8 SCSI_Out__8__PC
#define SCSI_Out_9 SCSI_Out__9__PC
#define SCSI_Out_DBP SCSI_Out__DBP__PC
#define SCSI_Out_ATN SCSI_Out__ATN__PC
#define SCSI_Out_BSY SCSI_Out__BSY__PC
#define SCSI_Out_ACK SCSI_Out__ACK__PC
#define SCSI_Out_RST SCSI_Out__RST__PC
#define SCSI_Out_MSG SCSI_Out__MSG__PC
#define SCSI_Out_SEL SCSI_Out__SEL__PC
#define SCSI_Out_CD SCSI_Out__CD__PC
#define SCSI_Out_REQ SCSI_Out__REQ__PC
#define SCSI_Out_IO SCSI_Out__IO__PC
#endif /* End Pins SCSI_Out_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SD.h
* Version 2.40
*
* Description:
* Contains the function prototypes, constants and register definition
* of the SPI Master Component.
*
* Note:
* None
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_SPIM_SD_H)
#define CY_SPIM_SD_H
#include "cytypes.h"
#include "cyfitter.h"
#include "CyLib.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component SPI_Master_v2_40 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/***************************************
* Conditional Compilation Parameters
***************************************/
#define SD_INTERNAL_CLOCK (0u)
#if(0u != SD_INTERNAL_CLOCK)
#include "SD_IntClock.h"
#endif /* (0u != SD_INTERNAL_CLOCK) */
#define SD_MODE (1u)
#define SD_DATA_WIDTH (8u)
#define SD_MODE_USE_ZERO (1u)
#define SD_BIDIRECTIONAL_MODE (0u)
/* Internal interrupt handling */
#define SD_TX_BUFFER_SIZE (4u)
#define SD_RX_BUFFER_SIZE (4u)
#define SD_INTERNAL_TX_INT_ENABLED (0u)
#define SD_INTERNAL_RX_INT_ENABLED (0u)
#define SD_SINGLE_REG_SIZE (8u)
#define SD_USE_SECOND_DATAPATH (SD_DATA_WIDTH > SD_SINGLE_REG_SIZE)
#define SD_FIFO_SIZE (4u)
#define SD_TX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_TX_INT_ENABLED) && \
(SD_TX_BUFFER_SIZE > SD_FIFO_SIZE))
#define SD_RX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_RX_INT_ENABLED) && \
(SD_RX_BUFFER_SIZE > SD_FIFO_SIZE))
/***************************************
* Data Struct Definition
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 enableState;
uint8 cntrPeriod;
#if(CY_UDB_V0)
uint8 saveSrTxIntMask;
uint8 saveSrRxIntMask;
#endif /* (CY_UDB_V0) */
} SD_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
void SD_Init(void) ;
void SD_Enable(void) ;
void SD_Start(void) ;
void SD_Stop(void) ;
void SD_EnableTxInt(void) ;
void SD_EnableRxInt(void) ;
void SD_DisableTxInt(void) ;
void SD_DisableRxInt(void) ;
void SD_Sleep(void) ;
void SD_Wakeup(void) ;
void SD_SaveConfig(void) ;
void SD_RestoreConfig(void) ;
void SD_SetTxInterruptMode(uint8 intSrc) ;
void SD_SetRxInterruptMode(uint8 intSrc) ;
uint8 SD_ReadTxStatus(void) ;
uint8 SD_ReadRxStatus(void) ;
void SD_WriteTxData(uint8 txData) \
;
uint8 SD_ReadRxData(void) \
;
uint8 SD_GetRxBufferSize(void) ;
uint8 SD_GetTxBufferSize(void) ;
void SD_ClearRxBuffer(void) ;
void SD_ClearTxBuffer(void) ;
void SD_ClearFIFO(void) ;
void SD_PutArray(const uint8 buffer[], uint8 byteCount) \
;
#if(0u != SD_BIDIRECTIONAL_MODE)
void SD_TxEnable(void) ;
void SD_TxDisable(void) ;
#endif /* (0u != SD_BIDIRECTIONAL_MODE) */
CY_ISR_PROTO(SD_TX_ISR);
CY_ISR_PROTO(SD_RX_ISR);
/**********************************
* Variable with external linkage
**********************************/
extern uint8 SD_initVar;
/***************************************
* API Constants
***************************************/
#define SD_TX_ISR_NUMBER ((uint8) (SD_TxInternalInterrupt__INTC_NUMBER))
#define SD_RX_ISR_NUMBER ((uint8) (SD_RxInternalInterrupt__INTC_NUMBER))
#define SD_TX_ISR_PRIORITY ((uint8) (SD_TxInternalInterrupt__INTC_PRIOR_NUM))
#define SD_RX_ISR_PRIORITY ((uint8) (SD_RxInternalInterrupt__INTC_PRIOR_NUM))
/***************************************
* Initial Parameter Constants
***************************************/
#define SD_INT_ON_SPI_DONE ((uint8) (0u << SD_STS_SPI_DONE_SHIFT))
#define SD_INT_ON_TX_EMPTY ((uint8) (0u << SD_STS_TX_FIFO_EMPTY_SHIFT))
#define SD_INT_ON_TX_NOT_FULL ((uint8) (0u << \
SD_STS_TX_FIFO_NOT_FULL_SHIFT))
#define SD_INT_ON_BYTE_COMP ((uint8) (0u << SD_STS_BYTE_COMPLETE_SHIFT))
#define SD_INT_ON_SPI_IDLE ((uint8) (0u << SD_STS_SPI_IDLE_SHIFT))
/* Disable TX_NOT_FULL if software buffer is used */
#define SD_INT_ON_TX_NOT_FULL_DEF ((SD_TX_SOFTWARE_BUF_ENABLED) ? \
(0u) : (SD_INT_ON_TX_NOT_FULL))
/* TX interrupt mask */
#define SD_TX_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \
SD_INT_ON_TX_EMPTY | \
SD_INT_ON_TX_NOT_FULL_DEF | \
SD_INT_ON_BYTE_COMP | \
SD_INT_ON_SPI_IDLE)
#define SD_INT_ON_RX_FULL ((uint8) (0u << \
SD_STS_RX_FIFO_FULL_SHIFT))
#define SD_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \
SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define SD_INT_ON_RX_OVER ((uint8) (0u << \
SD_STS_RX_FIFO_OVERRUN_SHIFT))
/* RX interrupt mask */
#define SD_RX_INIT_INTERRUPTS_MASK (SD_INT_ON_RX_FULL | \
SD_INT_ON_RX_NOT_EMPTY | \
SD_INT_ON_RX_OVER)
/* Nubmer of bits to receive/transmit */
#define SD_BITCTR_INIT (((uint8) (SD_DATA_WIDTH << 1u)) - 1u)
/***************************************
* Registers
***************************************/
#if(CY_PSOC3 || CY_PSOC5)
#define SD_TXDATA_REG (* (reg8 *) \
SD_BSPIM_sR8_Dp_u0__F0_REG)
#define SD_TXDATA_PTR ( (reg8 *) \
SD_BSPIM_sR8_Dp_u0__F0_REG)
#define SD_RXDATA_REG (* (reg8 *) \
SD_BSPIM_sR8_Dp_u0__F1_REG)
#define SD_RXDATA_PTR ( (reg8 *) \
SD_BSPIM_sR8_Dp_u0__F1_REG)
#else /* PSOC4 */
#if(SD_USE_SECOND_DATAPATH)
#define SD_TXDATA_REG (* (reg16 *) \
SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
#define SD_TXDATA_PTR ( (reg16 *) \
SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
#define SD_RXDATA_REG (* (reg16 *) \
SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
#define SD_RXDATA_PTR ( (reg16 *) \
SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
#else
#define SD_TXDATA_REG (* (reg8 *) \
SD_BSPIM_sR8_Dp_u0__F0_REG)
#define SD_TXDATA_PTR ( (reg8 *) \
SD_BSPIM_sR8_Dp_u0__F0_REG)
#define SD_RXDATA_REG (* (reg8 *) \
SD_BSPIM_sR8_Dp_u0__F1_REG)
#define SD_RXDATA_PTR ( (reg8 *) \
SD_BSPIM_sR8_Dp_u0__F1_REG)
#endif /* (SD_USE_SECOND_DATAPATH) */
#endif /* (CY_PSOC3 || CY_PSOC5) */
#define SD_AUX_CONTROL_DP0_REG (* (reg8 *) \
SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
#define SD_AUX_CONTROL_DP0_PTR ( (reg8 *) \
SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
#if(SD_USE_SECOND_DATAPATH)
#define SD_AUX_CONTROL_DP1_REG (* (reg8 *) \
SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
#define SD_AUX_CONTROL_DP1_PTR ( (reg8 *) \
SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
#endif /* (SD_USE_SECOND_DATAPATH) */
#define SD_COUNTER_PERIOD_REG (* (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)
#define SD_COUNTER_PERIOD_PTR ( (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)
#define SD_COUNTER_CONTROL_REG (* (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
#define SD_COUNTER_CONTROL_PTR ( (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
#define SD_TX_STATUS_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)
#define SD_TX_STATUS_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)
#define SD_RX_STATUS_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)
#define SD_RX_STATUS_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)
#define SD_CONTROL_REG (* (reg8 *) \
SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
#define SD_CONTROL_PTR ( (reg8 *) \
SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
#define SD_TX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)
#define SD_TX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)
#define SD_RX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)
#define SD_RX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)
#define SD_TX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
#define SD_TX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
#define SD_RX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
#define SD_RX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
#if(SD_USE_SECOND_DATAPATH)
#define SD_AUX_CONTROLDP1 (SD_AUX_CONTROL_DP1_REG)
#endif /* (SD_USE_SECOND_DATAPATH) */
/***************************************
* Register Constants
***************************************/
/* Status Register Definitions */
#define SD_STS_SPI_DONE_SHIFT (0x00u)
#define SD_STS_TX_FIFO_EMPTY_SHIFT (0x01u)
#define SD_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u)
#define SD_STS_BYTE_COMPLETE_SHIFT (0x03u)
#define SD_STS_SPI_IDLE_SHIFT (0x04u)
#define SD_STS_RX_FIFO_FULL_SHIFT (0x04u)
#define SD_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u)
#define SD_STS_RX_FIFO_OVERRUN_SHIFT (0x06u)
#define SD_STS_SPI_DONE ((uint8) (0x01u << SD_STS_SPI_DONE_SHIFT))
#define SD_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SD_STS_TX_FIFO_EMPTY_SHIFT))
#define SD_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SD_STS_TX_FIFO_NOT_FULL_SHIFT))
#define SD_STS_BYTE_COMPLETE ((uint8) (0x01u << SD_STS_BYTE_COMPLETE_SHIFT))
#define SD_STS_SPI_IDLE ((uint8) (0x01u << SD_STS_SPI_IDLE_SHIFT))
#define SD_STS_RX_FIFO_FULL ((uint8) (0x01u << SD_STS_RX_FIFO_FULL_SHIFT))
#define SD_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define SD_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SD_STS_RX_FIFO_OVERRUN_SHIFT))
/* TX and RX masks for clear on read bits */
#define SD_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u)
#define SD_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u)
/* StatusI Register Interrupt Enable Control Bits */
/* As defined by the Register map for the AUX Control Register */
#define SD_INT_ENABLE (0x10u) /* Enable interrupt from statusi */
#define SD_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */
#define SD_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */
#define SD_FIFO_CLR (SD_TX_FIFO_CLR | SD_RX_FIFO_CLR)
/* Bit Counter (7-bit) Control Register Bit Definitions */
/* As defined by the Register map for the AUX Control Register */
#define SD_CNTR_ENABLE (0x20u) /* Enable CNT7 */
/* Bi-Directional mode control bit */
#define SD_CTRL_TX_SIGNAL_EN (0x01u)
/* Datapath Auxillary Control Register definitions */
#define SD_AUX_CTRL_FIFO0_CLR (0x01u)
#define SD_AUX_CTRL_FIFO1_CLR (0x02u)
#define SD_AUX_CTRL_FIFO0_LVL (0x04u)
#define SD_AUX_CTRL_FIFO1_LVL (0x08u)
#define SD_STATUS_ACTL_INT_EN_MASK (0x10u)
/* Component disabled */
#define SD_DISABLED (0u)
/***************************************
* Macros
***************************************/
/* Returns true if componentn enabled */
#define SD_IS_ENABLED (0u != (SD_TX_STATUS_ACTL_REG & SD_INT_ENABLE))
/* Retuns TX status register */
#define SD_GET_STATUS_TX(swTxSts) ( (uint8)(SD_TX_STATUS_REG | \
((swTxSts) & SD_TX_STS_CLR_ON_RD_BYTES_MASK)) )
/* Retuns RX status register */
#define SD_GET_STATUS_RX(swRxSts) ( (uint8)(SD_RX_STATUS_REG | \
((swRxSts) & SD_RX_STS_CLR_ON_RD_BYTES_MASK)) )
/***************************************
* Obsolete definitions
***************************************/
/* Following definitions are for version compatibility.
* They are obsolete in SPIM v2_30.
* Please do not use it in new projects
*/
#define SD_WriteByte SD_WriteTxData
#define SD_ReadByte SD_ReadRxData
void SD_SetInterruptMode(uint8 intSrc) ;
uint8 SD_ReadStatus(void) ;
void SD_EnableInt(void) ;
void SD_DisableInt(void) ;
/* Obsolete register names. Not to be used in new designs */
#define SD_TXDATA (SD_TXDATA_REG)
#define SD_RXDATA (SD_RXDATA_REG)
#define SD_AUX_CONTROLDP0 (SD_AUX_CONTROL_DP0_REG)
#define SD_TXBUFFERREAD (SD_txBufferRead)
#define SD_TXBUFFERWRITE (SD_txBufferWrite)
#define SD_RXBUFFERREAD (SD_rxBufferRead)
#define SD_RXBUFFERWRITE (SD_rxBufferWrite)
#define SD_COUNTER_PERIOD (SD_COUNTER_PERIOD_REG)
#define SD_COUNTER_CONTROL (SD_COUNTER_CONTROL_REG)
#define SD_STATUS (SD_TX_STATUS_REG)
#define SD_CONTROL (SD_CONTROL_REG)
#define SD_STATUS_MASK (SD_TX_STATUS_MASK_REG)
#define SD_STATUS_ACTL (SD_TX_STATUS_ACTL_REG)
#define SD_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \
SD_INT_ON_TX_EMPTY | \
SD_INT_ON_TX_NOT_FULL_DEF | \
SD_INT_ON_RX_FULL | \
SD_INT_ON_RX_NOT_EMPTY | \
SD_INT_ON_RX_OVER | \
SD_INT_ON_BYTE_COMP)
/* Following definitions are for version Compatibility.
* They are obsolete in SPIM v2_40.
* Please do not use it in new projects
*/
#define SD_DataWidth (SD_DATA_WIDTH)
#define SD_InternalClockUsed (SD_INTERNAL_CLOCK)
#define SD_InternalTxInterruptEnabled (SD_INTERNAL_TX_INT_ENABLED)
#define SD_InternalRxInterruptEnabled (SD_INTERNAL_RX_INT_ENABLED)
#define SD_ModeUseZero (SD_MODE_USE_ZERO)
#define SD_BidirectionalMode (SD_BIDIRECTIONAL_MODE)
#define SD_Mode (SD_MODE)
#define SD_DATAWIDHT (SD_DATA_WIDTH)
#define SD_InternalInterruptEnabled (0u)
#define SD_TXBUFFERSIZE (SD_TX_BUFFER_SIZE)
#define SD_RXBUFFERSIZE (SD_RX_BUFFER_SIZE)
#define SD_TXBUFFER SD_txBuffer
#define SD_RXBUFFER SD_rxBuffer
#endif /* (CY_SPIM_SD_H) */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SDCard.h
* Version 2.40
*
* Description:
* Contains the function prototypes, constants and register definition
* of the SPI Master Component.
*
* Note:
* None
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_SPIM_SDCard_H)
#define CY_SPIM_SDCard_H
#include "cytypes.h"
#include "cyfitter.h"
#include "CyLib.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component SPI_Master_v2_40 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/***************************************
* Conditional Compilation Parameters
***************************************/
#define SDCard_INTERNAL_CLOCK (0u)
#if(0u != SDCard_INTERNAL_CLOCK)
#include "SDCard_IntClock.h"
#endif /* (0u != SDCard_INTERNAL_CLOCK) */
#define SDCard_MODE (1u)
#define SDCard_DATA_WIDTH (8u)
#define SDCard_MODE_USE_ZERO (1u)
#define SDCard_BIDIRECTIONAL_MODE (0u)
/* Internal interrupt handling */
#define SDCard_TX_BUFFER_SIZE (4u)
#define SDCard_RX_BUFFER_SIZE (4u)
#define SDCard_INTERNAL_TX_INT_ENABLED (1u)
#define SDCard_INTERNAL_RX_INT_ENABLED (1u)
#define SDCard_SINGLE_REG_SIZE (8u)
#define SDCard_USE_SECOND_DATAPATH (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE)
#define SDCard_FIFO_SIZE (4u)
#define SDCard_TX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_TX_INT_ENABLED) && \
(SDCard_TX_BUFFER_SIZE > SDCard_FIFO_SIZE))
#define SDCard_RX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_RX_INT_ENABLED) && \
(SDCard_RX_BUFFER_SIZE > SDCard_FIFO_SIZE))
/***************************************
* Data Struct Definition
***************************************/
/* Sleep Mode API Support */
typedef struct
{
uint8 enableState;
uint8 cntrPeriod;
#if(CY_UDB_V0)
uint8 saveSrTxIntMask;
uint8 saveSrRxIntMask;
#endif /* (CY_UDB_V0) */
} SDCard_BACKUP_STRUCT;
/***************************************
* Function Prototypes
***************************************/
void SDCard_Init(void) ;
void SDCard_Enable(void) ;
void SDCard_Start(void) ;
void SDCard_Stop(void) ;
void SDCard_EnableTxInt(void) ;
void SDCard_EnableRxInt(void) ;
void SDCard_DisableTxInt(void) ;
void SDCard_DisableRxInt(void) ;
void SDCard_Sleep(void) ;
void SDCard_Wakeup(void) ;
void SDCard_SaveConfig(void) ;
void SDCard_RestoreConfig(void) ;
void SDCard_SetTxInterruptMode(uint8 intSrc) ;
void SDCard_SetRxInterruptMode(uint8 intSrc) ;
uint8 SDCard_ReadTxStatus(void) ;
uint8 SDCard_ReadRxStatus(void) ;
void SDCard_WriteTxData(uint8 txData) \
;
uint8 SDCard_ReadRxData(void) \
;
uint8 SDCard_GetRxBufferSize(void) ;
uint8 SDCard_GetTxBufferSize(void) ;
void SDCard_ClearRxBuffer(void) ;
void SDCard_ClearTxBuffer(void) ;
void SDCard_ClearFIFO(void) ;
void SDCard_PutArray(const uint8 buffer[], uint8 byteCount) \
;
#if(0u != SDCard_BIDIRECTIONAL_MODE)
void SDCard_TxEnable(void) ;
void SDCard_TxDisable(void) ;
#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */
CY_ISR_PROTO(SDCard_TX_ISR);
CY_ISR_PROTO(SDCard_RX_ISR);
/**********************************
* Variable with external linkage
**********************************/
extern uint8 SDCard_initVar;
/***************************************
* API Constants
***************************************/
#define SDCard_TX_ISR_NUMBER ((uint8) (SDCard_TxInternalInterrupt__INTC_NUMBER))
#define SDCard_RX_ISR_NUMBER ((uint8) (SDCard_RxInternalInterrupt__INTC_NUMBER))
#define SDCard_TX_ISR_PRIORITY ((uint8) (SDCard_TxInternalInterrupt__INTC_PRIOR_NUM))
#define SDCard_RX_ISR_PRIORITY ((uint8) (SDCard_RxInternalInterrupt__INTC_PRIOR_NUM))
/***************************************
* Initial Parameter Constants
***************************************/
#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT))
#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \
SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT))
#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT))
/* Disable TX_NOT_FULL if software buffer is used */
#define SDCard_INT_ON_TX_NOT_FULL_DEF ((SDCard_TX_SOFTWARE_BUF_ENABLED) ? \
(0u) : (SDCard_INT_ON_TX_NOT_FULL))
/* TX interrupt mask */
#define SDCard_TX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \
SDCard_INT_ON_TX_EMPTY | \
SDCard_INT_ON_TX_NOT_FULL_DEF | \
SDCard_INT_ON_BYTE_COMP | \
SDCard_INT_ON_SPI_IDLE)
#define SDCard_INT_ON_RX_FULL ((uint8) (0u << \
SDCard_STS_RX_FIFO_FULL_SHIFT))
#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \
SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define SDCard_INT_ON_RX_OVER ((uint8) (0u << \
SDCard_STS_RX_FIFO_OVERRUN_SHIFT))
/* RX interrupt mask */
#define SDCard_RX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_RX_FULL | \
SDCard_INT_ON_RX_NOT_EMPTY | \
SDCard_INT_ON_RX_OVER)
/* Nubmer of bits to receive/transmit */
#define SDCard_BITCTR_INIT (((uint8) (SDCard_DATA_WIDTH << 1u)) - 1u)
/***************************************
* Registers
***************************************/
#if(CY_PSOC3 || CY_PSOC5)
#define SDCard_TXDATA_REG (* (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F0_REG)
#define SDCard_TXDATA_PTR ( (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F0_REG)
#define SDCard_RXDATA_REG (* (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F1_REG)
#define SDCard_RXDATA_PTR ( (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F1_REG)
#else /* PSOC4 */
#if(SDCard_USE_SECOND_DATAPATH)
#define SDCard_TXDATA_REG (* (reg16 *) \
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
#define SDCard_TXDATA_PTR ( (reg16 *) \
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
#define SDCard_RXDATA_REG (* (reg16 *) \
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
#define SDCard_RXDATA_PTR ( (reg16 *) \
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
#else
#define SDCard_TXDATA_REG (* (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F0_REG)
#define SDCard_TXDATA_PTR ( (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F0_REG)
#define SDCard_RXDATA_REG (* (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F1_REG)
#define SDCard_RXDATA_PTR ( (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F1_REG)
#endif /* (SDCard_USE_SECOND_DATAPATH) */
#endif /* (CY_PSOC3 || CY_PSOC5) */
#define SDCard_AUX_CONTROL_DP0_REG (* (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
#define SDCard_AUX_CONTROL_DP0_PTR ( (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
#if(SDCard_USE_SECOND_DATAPATH)
#define SDCard_AUX_CONTROL_DP1_REG (* (reg8 *) \
SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
#define SDCard_AUX_CONTROL_DP1_PTR ( (reg8 *) \
SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
#endif /* (SDCard_USE_SECOND_DATAPATH) */
#define SDCard_COUNTER_PERIOD_REG (* (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG)
#define SDCard_COUNTER_PERIOD_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG)
#define SDCard_COUNTER_CONTROL_REG (* (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
#define SDCard_COUNTER_CONTROL_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
#define SDCard_TX_STATUS_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG)
#define SDCard_TX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG)
#define SDCard_RX_STATUS_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)
#define SDCard_RX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)
#define SDCard_CONTROL_REG (* (reg8 *) \
SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
#define SDCard_CONTROL_PTR ( (reg8 *) \
SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
#define SDCard_TX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
#define SDCard_TX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
#define SDCard_RX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG)
#define SDCard_RX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG)
#define SDCard_TX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
#define SDCard_TX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
#define SDCard_RX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
#define SDCard_RX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
#if(SDCard_USE_SECOND_DATAPATH)
#define SDCard_AUX_CONTROLDP1 (SDCard_AUX_CONTROL_DP1_REG)
#endif /* (SDCard_USE_SECOND_DATAPATH) */
/***************************************
* Register Constants
***************************************/
/* Status Register Definitions */
#define SDCard_STS_SPI_DONE_SHIFT (0x00u)
#define SDCard_STS_TX_FIFO_EMPTY_SHIFT (0x01u)
#define SDCard_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u)
#define SDCard_STS_BYTE_COMPLETE_SHIFT (0x03u)
#define SDCard_STS_SPI_IDLE_SHIFT (0x04u)
#define SDCard_STS_RX_FIFO_FULL_SHIFT (0x04u)
#define SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u)
#define SDCard_STS_RX_FIFO_OVERRUN_SHIFT (0x06u)
#define SDCard_STS_SPI_DONE ((uint8) (0x01u << SDCard_STS_SPI_DONE_SHIFT))
#define SDCard_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
#define SDCard_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
#define SDCard_STS_BYTE_COMPLETE ((uint8) (0x01u << SDCard_STS_BYTE_COMPLETE_SHIFT))
#define SDCard_STS_SPI_IDLE ((uint8) (0x01u << SDCard_STS_SPI_IDLE_SHIFT))
#define SDCard_STS_RX_FIFO_FULL ((uint8) (0x01u << SDCard_STS_RX_FIFO_FULL_SHIFT))
#define SDCard_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define SDCard_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SDCard_STS_RX_FIFO_OVERRUN_SHIFT))
/* TX and RX masks for clear on read bits */
#define SDCard_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u)
#define SDCard_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u)
/* StatusI Register Interrupt Enable Control Bits */
/* As defined by the Register map for the AUX Control Register */
#define SDCard_INT_ENABLE (0x10u) /* Enable interrupt from statusi */
#define SDCard_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */
#define SDCard_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */
#define SDCard_FIFO_CLR (SDCard_TX_FIFO_CLR | SDCard_RX_FIFO_CLR)
/* Bit Counter (7-bit) Control Register Bit Definitions */
/* As defined by the Register map for the AUX Control Register */
#define SDCard_CNTR_ENABLE (0x20u) /* Enable CNT7 */
/* Bi-Directional mode control bit */
#define SDCard_CTRL_TX_SIGNAL_EN (0x01u)
/* Datapath Auxillary Control Register definitions */
#define SDCard_AUX_CTRL_FIFO0_CLR (0x01u)
#define SDCard_AUX_CTRL_FIFO1_CLR (0x02u)
#define SDCard_AUX_CTRL_FIFO0_LVL (0x04u)
#define SDCard_AUX_CTRL_FIFO1_LVL (0x08u)
#define SDCard_STATUS_ACTL_INT_EN_MASK (0x10u)
/* Component disabled */
#define SDCard_DISABLED (0u)
/***************************************
* Macros
***************************************/
/* Returns true if componentn enabled */
#define SDCard_IS_ENABLED (0u != (SDCard_TX_STATUS_ACTL_REG & SDCard_INT_ENABLE))
/* Retuns TX status register */
#define SDCard_GET_STATUS_TX(swTxSts) ( (uint8)(SDCard_TX_STATUS_REG | \
((swTxSts) & SDCard_TX_STS_CLR_ON_RD_BYTES_MASK)) )
/* Retuns RX status register */
#define SDCard_GET_STATUS_RX(swRxSts) ( (uint8)(SDCard_RX_STATUS_REG | \
((swRxSts) & SDCard_RX_STS_CLR_ON_RD_BYTES_MASK)) )
/***************************************
* Obsolete definitions
***************************************/
/* Following definitions are for version compatibility.
* They are obsolete in SPIM v2_30.
* Please do not use it in new projects
*/
#define SDCard_WriteByte SDCard_WriteTxData
#define SDCard_ReadByte SDCard_ReadRxData
void SDCard_SetInterruptMode(uint8 intSrc) ;
uint8 SDCard_ReadStatus(void) ;
void SDCard_EnableInt(void) ;
void SDCard_DisableInt(void) ;
/* Obsolete register names. Not to be used in new designs */
#define SDCard_TXDATA (SDCard_TXDATA_REG)
#define SDCard_RXDATA (SDCard_RXDATA_REG)
#define SDCard_AUX_CONTROLDP0 (SDCard_AUX_CONTROL_DP0_REG)
#define SDCard_TXBUFFERREAD (SDCard_txBufferRead)
#define SDCard_TXBUFFERWRITE (SDCard_txBufferWrite)
#define SDCard_RXBUFFERREAD (SDCard_rxBufferRead)
#define SDCard_RXBUFFERWRITE (SDCard_rxBufferWrite)
#define SDCard_COUNTER_PERIOD (SDCard_COUNTER_PERIOD_REG)
#define SDCard_COUNTER_CONTROL (SDCard_COUNTER_CONTROL_REG)
#define SDCard_STATUS (SDCard_TX_STATUS_REG)
#define SDCard_CONTROL (SDCard_CONTROL_REG)
#define SDCard_STATUS_MASK (SDCard_TX_STATUS_MASK_REG)
#define SDCard_STATUS_ACTL (SDCard_TX_STATUS_ACTL_REG)
#define SDCard_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \
SDCard_INT_ON_TX_EMPTY | \
SDCard_INT_ON_TX_NOT_FULL_DEF | \
SDCard_INT_ON_RX_FULL | \
SDCard_INT_ON_RX_NOT_EMPTY | \
SDCard_INT_ON_RX_OVER | \
SDCard_INT_ON_BYTE_COMP)
/* Following definitions are for version Compatibility.
* They are obsolete in SPIM v2_40.
* Please do not use it in new projects
*/
#define SDCard_DataWidth (SDCard_DATA_WIDTH)
#define SDCard_InternalClockUsed (SDCard_INTERNAL_CLOCK)
#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED)
#define SDCard_InternalRxInterruptEnabled (SDCard_INTERNAL_RX_INT_ENABLED)
#define SDCard_ModeUseZero (SDCard_MODE_USE_ZERO)
#define SDCard_BidirectionalMode (SDCard_BIDIRECTIONAL_MODE)
#define SDCard_Mode (SDCard_MODE)
#define SDCard_DATAWIDHT (SDCard_DATA_WIDTH)
#define SDCard_InternalInterruptEnabled (0u)
#define SDCard_TXBUFFERSIZE (SDCard_TX_BUFFER_SIZE)
#define SDCard_RXBUFFERSIZE (SDCard_RX_BUFFER_SIZE)
#define SDCard_TXBUFFER SDCard_txBuffer
#define SDCard_RXBUFFER SDCard_rxBuffer
#endif /* (CY_SPIM_SDCard_H) */
/* [] END OF FILE */

189
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/*******************************************************************************
* File Name: SDCard_INT.c
* Version 2.40
*
* Description:
* This file provides all Interrupt Service Routine (ISR) for the SPI Master
* component.
*
* Note:
* None.
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SDCard_PVT.h"
/* User code required at start of ISR */
/* `#START SDCard_ISR_START_DEF` */
/* `#END` */
/*******************************************************************************
* Function Name: SDCard_TX_ISR
********************************************************************************
*
* Summary:
* Interrupt Service Routine for TX portion of the SPI Master.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* SDCard_txBufferWrite - used for the account of the bytes which
* have been written down in the TX software buffer.
* SDCard_txBufferRead - used for the account of the bytes which
* have been read from the TX software buffer, modified when exist data to
* sending and FIFO Not Full.
* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store
* data to sending.
* All described above Global variables are used when Software Buffer is used.
*
*******************************************************************************/
CY_ISR(SDCard_TX_ISR)
{
#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
uint8 tmpStatus;
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
/* User code required at start of ISR */
/* `#START SDCard_TX_ISR_START` */
/* `#END` */
#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
/* Check if TX data buffer is not empty and there is space in TX FIFO */
while(SDCard_txBufferRead != SDCard_txBufferWrite)
{
tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);
SDCard_swStatusTx = tmpStatus;
if(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL))
{
if(0u == SDCard_txBufferFull)
{
SDCard_txBufferRead++;
if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE)
{
SDCard_txBufferRead = 0u;
}
}
else
{
SDCard_txBufferFull = 0u;
}
/* Move data from the Buffer to the FIFO */
CY_SET_REG8(SDCard_TXDATA_PTR,
SDCard_txBuffer[SDCard_txBufferRead]);
}
else
{
break;
}
}
if(SDCard_txBufferRead == SDCard_txBufferWrite)
{
/* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */
SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL);
}
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
/* User code required at end of ISR (Optional) */
/* `#START SDCard_TX_ISR_END` */
/* `#END` */
}
/*******************************************************************************
* Function Name: SDCard_RX_ISR
********************************************************************************
*
* Summary:
* Interrupt Service Routine for RX portion of the SPI Master.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* SDCard_rxBufferWrite - used for the account of the bytes which
* have been written down in the RX software buffer modified when FIFO contains
* new data.
* SDCard_rxBufferRead - used for the account of the bytes which
* have been read from the RX software buffer, modified when overflow occurred.
* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store
* received data, modified when FIFO contains new data.
* All described above Global variables are used when Software Buffer is used.
*
*******************************************************************************/
CY_ISR(SDCard_RX_ISR)
{
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
uint8 tmpStatus;
uint8 rxData;
#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
/* User code required at start of ISR */
/* `#START SDCard_RX_ISR_START` */
/* `#END` */
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
SDCard_swStatusRx = tmpStatus;
/* Check if RX data FIFO has some data to be moved into the RX Buffer */
while(0u != (SDCard_swStatusRx & SDCard_STS_RX_FIFO_NOT_EMPTY))
{
rxData = CY_GET_REG8(SDCard_RXDATA_PTR);
/* Set next pointer. */
SDCard_rxBufferWrite++;
if(SDCard_rxBufferWrite >= SDCard_RX_BUFFER_SIZE)
{
SDCard_rxBufferWrite = 0u;
}
if(SDCard_rxBufferWrite == SDCard_rxBufferRead)
{
SDCard_rxBufferRead++;
if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE)
{
SDCard_rxBufferRead = 0u;
}
SDCard_rxBufferFull = 1u;
}
/* Move data from the FIFO to the Buffer */
SDCard_rxBuffer[SDCard_rxBufferWrite] = rxData;
tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
SDCard_swStatusRx = tmpStatus;
}
#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
/* User code required at end of ISR (Optional) */
/* `#START SDCard_RX_ISR_END` */
/* `#END` */
}
/* [] END OF FILE */

180
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/*******************************************************************************
* File Name: SDCard_PM.c
* Version 2.40
*
* Description:
* This file contains the setup, control and status commands to support
* component operations in low power mode.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SDCard_PVT.h"
static SDCard_BACKUP_STRUCT SDCard_backup =
{
SDCard_DISABLED,
SDCard_BITCTR_INIT,
#if(CY_UDB_V0)
SDCard_TX_INIT_INTERRUPTS_MASK,
SDCard_RX_INIT_INTERRUPTS_MASK
#endif /* CY_UDB_V0 */
};
/*******************************************************************************
* Function Name: SDCard_SaveConfig
********************************************************************************
*
* Summary:
* Saves SPIM configuration.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global Variables:
* SDCard_backup - modified when non-retention registers are saved.
*
* Reentrant:
* No.
*
*******************************************************************************/
void SDCard_SaveConfig(void)
{
/* Store Status Mask registers */
#if(CY_UDB_V0)
SDCard_backup.cntrPeriod = SDCard_COUNTER_PERIOD_REG;
SDCard_backup.saveSrTxIntMask = SDCard_TX_STATUS_MASK_REG;
SDCard_backup.saveSrRxIntMask = SDCard_RX_STATUS_MASK_REG;
#endif /* (CY_UDB_V0) */
}
/*******************************************************************************
* Function Name: SDCard_RestoreConfig
********************************************************************************
*
* Summary:
* Restores SPIM configuration.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global Variables:
* SDCard_backup - used when non-retention registers are restored.
*
* Side Effects:
* If this API is called without first calling SaveConfig then in the following
* registers will be default values from Customizer:
* SDCard_STATUS_MASK_REG and SDCard_COUNTER_PERIOD_REG.
*
*******************************************************************************/
void SDCard_RestoreConfig(void)
{
/* Restore the data, saved by SaveConfig() function */
#if(CY_UDB_V0)
SDCard_COUNTER_PERIOD_REG = SDCard_backup.cntrPeriod;
SDCard_TX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrTxIntMask);
SDCard_RX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrRxIntMask);
#endif /* (CY_UDB_V0) */
}
/*******************************************************************************
* Function Name: SDCard_Sleep
********************************************************************************
*
* Summary:
* Prepare SPIM Component goes to sleep.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global Variables:
* SDCard_backup - modified when non-retention registers are saved.
*
* Reentrant:
* No.
*
*******************************************************************************/
void SDCard_Sleep(void)
{
/* Save components enable state */
SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED);
SDCard_Stop();
SDCard_SaveConfig();
}
/*******************************************************************************
* Function Name: SDCard_Wakeup
********************************************************************************
*
* Summary:
* Prepare SPIM Component to wake up.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global Variables:
* SDCard_backup - used when non-retention registers are restored.
* SDCard_txBufferWrite - modified every function call - resets to
* zero.
* SDCard_txBufferRead - modified every function call - resets to
* zero.
* SDCard_rxBufferWrite - modified every function call - resets to
* zero.
* SDCard_rxBufferRead - modified every function call - resets to
* zero.
*
* Reentrant:
* No.
*
*******************************************************************************/
void SDCard_Wakeup(void)
{
SDCard_RestoreConfig();
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
SDCard_rxBufferFull = 0u;
SDCard_rxBufferRead = 0u;
SDCard_rxBufferWrite = 0u;
#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
SDCard_txBufferFull = 0u;
SDCard_txBufferRead = 0u;
SDCard_txBufferWrite = 0u;
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
/* Clear any data from the RX and TX FIFO */
SDCard_ClearFIFO();
/* Restore components block enable state */
if(0u != SDCard_backup.enableState)
{
SDCard_Enable();
}
}
/* [] END OF FILE */

53
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/*******************************************************************************
* File Name: .h
* Version 2.40
*
* Description:
* This private header file contains internal definitions for the SPIM
* component. Do not use these definitions directly in your application.
*
* Note:
*
********************************************************************************
* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_SPIM_PVT_SDCard_H)
#define CY_SPIM_PVT_SDCard_H
#include "SDCard.h"
/**********************************
* Functions with external linkage
**********************************/
/**********************************
* Variables with external linkage
**********************************/
extern volatile uint8 SDCard_swStatusTx;
extern volatile uint8 SDCard_swStatusRx;
#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
extern volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];
extern volatile uint8 SDCard_txBufferRead;
extern volatile uint8 SDCard_txBufferWrite;
extern volatile uint8 SDCard_txBufferFull;
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
extern volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];
extern volatile uint8 SDCard_rxBufferRead;
extern volatile uint8 SDCard_rxBufferWrite;
extern volatile uint8 SDCard_rxBufferFull;
#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
#endif /* CY_SPIM_PVT_SDCard_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SD_CD.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SD_CD.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SD_CD_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SD_CD_Write(uint8 value)
{
uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK));
SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK);
}
/*******************************************************************************
* Function Name: SD_CD_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SD_CD_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SD_CD_0, mode);
}
/*******************************************************************************
* Function Name: SD_CD_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SD_CD_ReadPS calls this function.
*
*******************************************************************************/
uint8 SD_CD_Read(void)
{
return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT;
}
/*******************************************************************************
* Function Name: SD_CD_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SD_CD_ReadDataReg(void)
{
return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SD_CD_INTSTAT)
/*******************************************************************************
* Function Name: SD_CD_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SD_CD_ClearInterrupt(void)
{
return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SD_CD.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SD_CD_H) /* Pins SD_CD_H */
#define CY_PINS_SD_CD_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SD_CD_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SD_CD_Write(uint8 value) ;
void SD_CD_SetDriveMode(uint8 mode) ;
uint8 SD_CD_ReadDataReg(void) ;
uint8 SD_CD_Read(void) ;
uint8 SD_CD_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SD_CD_DM_RES_UP PIN_DM_RES_UP
#define SD_CD_DM_RES_DWN PIN_DM_RES_DWN
#define SD_CD_DM_OD_LO PIN_DM_OD_LO
#define SD_CD_DM_OD_HI PIN_DM_OD_HI
#define SD_CD_DM_STRONG PIN_DM_STRONG
#define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SD_CD_MASK SD_CD__MASK
#define SD_CD_SHIFT SD_CD__SHIFT
#define SD_CD_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SD_CD_PS (* (reg8 *) SD_CD__PS)
/* Data Register */
#define SD_CD_DR (* (reg8 *) SD_CD__DR)
/* Port Number */
#define SD_CD_PRT_NUM (* (reg8 *) SD_CD__PRT)
/* Connect to Analog Globals */
#define SD_CD_AG (* (reg8 *) SD_CD__AG)
/* Analog MUX bux enable */
#define SD_CD_AMUX (* (reg8 *) SD_CD__AMUX)
/* Bidirectional Enable */
#define SD_CD_BIE (* (reg8 *) SD_CD__BIE)
/* Bit-mask for Aliased Register Access */
#define SD_CD_BIT_MASK (* (reg8 *) SD_CD__BIT_MASK)
/* Bypass Enable */
#define SD_CD_BYP (* (reg8 *) SD_CD__BYP)
/* Port wide control signals */
#define SD_CD_CTL (* (reg8 *) SD_CD__CTL)
/* Drive Modes */
#define SD_CD_DM0 (* (reg8 *) SD_CD__DM0)
#define SD_CD_DM1 (* (reg8 *) SD_CD__DM1)
#define SD_CD_DM2 (* (reg8 *) SD_CD__DM2)
/* Input Buffer Disable Override */
#define SD_CD_INP_DIS (* (reg8 *) SD_CD__INP_DIS)
/* LCD Common or Segment Drive */
#define SD_CD_LCD_COM_SEG (* (reg8 *) SD_CD__LCD_COM_SEG)
/* Enable Segment LCD */
#define SD_CD_LCD_EN (* (reg8 *) SD_CD__LCD_EN)
/* Slew Rate Control */
#define SD_CD_SLW (* (reg8 *) SD_CD__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SD_CD_PRTDSI__CAPS_SEL (* (reg8 *) SD_CD__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SD_CD_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CD__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SD_CD_PRTDSI__OE_SEL0 (* (reg8 *) SD_CD__PRTDSI__OE_SEL0)
#define SD_CD_PRTDSI__OE_SEL1 (* (reg8 *) SD_CD__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SD_CD_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL0)
#define SD_CD_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SD_CD_PRTDSI__SYNC_OUT (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT)
#if defined(SD_CD__INTSTAT) /* Interrupt Registers */
#define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT)
#define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SD_CD_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SD_CD.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SD_CD_ALIASES_H) /* Pins SD_CD_ALIASES_H */
#define CY_PINS_SD_CD_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SD_CD_0 SD_CD__0__PC
#endif /* End Pins SD_CD_ALIASES_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SD_CS.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SD_CS.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SD_CS_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SD_CS_Write(uint8 value)
{
uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK));
SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK);
}
/*******************************************************************************
* Function Name: SD_CS_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SD_CS_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SD_CS_0, mode);
}
/*******************************************************************************
* Function Name: SD_CS_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SD_CS_ReadPS calls this function.
*
*******************************************************************************/
uint8 SD_CS_Read(void)
{
return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT;
}
/*******************************************************************************
* Function Name: SD_CS_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SD_CS_ReadDataReg(void)
{
return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SD_CS_INTSTAT)
/*******************************************************************************
* Function Name: SD_CS_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SD_CS_ClearInterrupt(void)
{
return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

130
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/*******************************************************************************
* File Name: SD_CS.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SD_CS_H) /* Pins SD_CS_H */
#define CY_PINS_SD_CS_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SD_CS_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SD_CS_Write(uint8 value) ;
void SD_CS_SetDriveMode(uint8 mode) ;
uint8 SD_CS_ReadDataReg(void) ;
uint8 SD_CS_Read(void) ;
uint8 SD_CS_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SD_CS_DM_RES_UP PIN_DM_RES_UP
#define SD_CS_DM_RES_DWN PIN_DM_RES_DWN
#define SD_CS_DM_OD_LO PIN_DM_OD_LO
#define SD_CS_DM_OD_HI PIN_DM_OD_HI
#define SD_CS_DM_STRONG PIN_DM_STRONG
#define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SD_CS_MASK SD_CS__MASK
#define SD_CS_SHIFT SD_CS__SHIFT
#define SD_CS_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SD_CS_PS (* (reg8 *) SD_CS__PS)
/* Data Register */
#define SD_CS_DR (* (reg8 *) SD_CS__DR)
/* Port Number */
#define SD_CS_PRT_NUM (* (reg8 *) SD_CS__PRT)
/* Connect to Analog Globals */
#define SD_CS_AG (* (reg8 *) SD_CS__AG)
/* Analog MUX bux enable */
#define SD_CS_AMUX (* (reg8 *) SD_CS__AMUX)
/* Bidirectional Enable */
#define SD_CS_BIE (* (reg8 *) SD_CS__BIE)
/* Bit-mask for Aliased Register Access */
#define SD_CS_BIT_MASK (* (reg8 *) SD_CS__BIT_MASK)
/* Bypass Enable */
#define SD_CS_BYP (* (reg8 *) SD_CS__BYP)
/* Port wide control signals */
#define SD_CS_CTL (* (reg8 *) SD_CS__CTL)
/* Drive Modes */
#define SD_CS_DM0 (* (reg8 *) SD_CS__DM0)
#define SD_CS_DM1 (* (reg8 *) SD_CS__DM1)
#define SD_CS_DM2 (* (reg8 *) SD_CS__DM2)
/* Input Buffer Disable Override */
#define SD_CS_INP_DIS (* (reg8 *) SD_CS__INP_DIS)
/* LCD Common or Segment Drive */
#define SD_CS_LCD_COM_SEG (* (reg8 *) SD_CS__LCD_COM_SEG)
/* Enable Segment LCD */
#define SD_CS_LCD_EN (* (reg8 *) SD_CS__LCD_EN)
/* Slew Rate Control */
#define SD_CS_SLW (* (reg8 *) SD_CS__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SD_CS_PRTDSI__CAPS_SEL (* (reg8 *) SD_CS__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SD_CS_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CS__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SD_CS_PRTDSI__OE_SEL0 (* (reg8 *) SD_CS__PRTDSI__OE_SEL0)
#define SD_CS_PRTDSI__OE_SEL1 (* (reg8 *) SD_CS__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SD_CS_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL0)
#define SD_CS_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SD_CS_PRTDSI__SYNC_OUT (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT)
#if defined(SD_CS__INTSTAT) /* Interrupt Registers */
#define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT)
#define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SD_CS_H */
/* [] END OF FILE */

32
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/*******************************************************************************
* File Name: SD_CS.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SD_CS_ALIASES_H) /* Pins SD_CS_ALIASES_H */
#define CY_PINS_SD_CS_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SD_CS_0 SD_CS__0__PC
#endif /* End Pins SD_CS_ALIASES_H */
/* [] END OF FILE */

63
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c Normal file
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/*******************************************************************************
* File Name: SD_Clk_Ctl.c
* Version 1.70
*
* Description:
* This file contains API to enable firmware control of a Control Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SD_Clk_Ctl.h"
#if !defined(SD_Clk_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SD_Clk_Ctl_Write
********************************************************************************
*
* Summary:
* Write a byte to the Control Register.
*
* Parameters:
* control: The value to be assigned to the Control Register.
*
* Return:
* None.
*
*******************************************************************************/
void SD_Clk_Ctl_Write(uint8 control)
{
SD_Clk_Ctl_Control = control;
}
/*******************************************************************************
* Function Name: SD_Clk_Ctl_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Control Register.
*
* Parameters:
* None.
*
* Return:
* Returns the current value in the Control Register.
*
*******************************************************************************/
uint8 SD_Clk_Ctl_Read(void)
{
return SD_Clk_Ctl_Control;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

42
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h Normal file
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/*******************************************************************************
* File Name: SD_Clk_Ctl.h
* Version 1.70
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CONTROL_REG_SD_Clk_Ctl_H) /* CY_CONTROL_REG_SD_Clk_Ctl_H */
#define CY_CONTROL_REG_SD_Clk_Ctl_H
#include "cytypes.h"
/***************************************
* Function Prototypes
***************************************/
void SD_Clk_Ctl_Write(uint8 control) ;
uint8 SD_Clk_Ctl_Read(void) ;
/***************************************
* Registers
***************************************/
/* Control Register */
#define SD_Clk_Ctl_Control (* (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG )
#define SD_Clk_Ctl_Control_PTR ( (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG )
#endif /* End CY_CONTROL_REG_SD_Clk_Ctl_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SD_DAT1.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SD_DAT1.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SD_DAT1__PORT == 15 && ((SD_DAT1__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SD_DAT1_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SD_DAT1_Write(uint8 value)
{
uint8 staticBits = (SD_DAT1_DR & (uint8)(~SD_DAT1_MASK));
SD_DAT1_DR = staticBits | ((uint8)(value << SD_DAT1_SHIFT) & SD_DAT1_MASK);
}
/*******************************************************************************
* Function Name: SD_DAT1_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SD_DAT1_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SD_DAT1_0, mode);
}
/*******************************************************************************
* Function Name: SD_DAT1_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SD_DAT1_ReadPS calls this function.
*
*******************************************************************************/
uint8 SD_DAT1_Read(void)
{
return (SD_DAT1_PS & SD_DAT1_MASK) >> SD_DAT1_SHIFT;
}
/*******************************************************************************
* Function Name: SD_DAT1_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SD_DAT1_ReadDataReg(void)
{
return (SD_DAT1_DR & SD_DAT1_MASK) >> SD_DAT1_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SD_DAT1_INTSTAT)
/*******************************************************************************
* Function Name: SD_DAT1_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SD_DAT1_ClearInterrupt(void)
{
return (SD_DAT1_INTSTAT & SD_DAT1_MASK) >> SD_DAT1_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SD_DAT1.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SD_DAT1_H) /* Pins SD_DAT1_H */
#define CY_PINS_SD_DAT1_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SD_DAT1_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SD_DAT1__PORT == 15 && ((SD_DAT1__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SD_DAT1_Write(uint8 value) ;
void SD_DAT1_SetDriveMode(uint8 mode) ;
uint8 SD_DAT1_ReadDataReg(void) ;
uint8 SD_DAT1_Read(void) ;
uint8 SD_DAT1_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SD_DAT1_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SD_DAT1_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SD_DAT1_DM_RES_UP PIN_DM_RES_UP
#define SD_DAT1_DM_RES_DWN PIN_DM_RES_DWN
#define SD_DAT1_DM_OD_LO PIN_DM_OD_LO
#define SD_DAT1_DM_OD_HI PIN_DM_OD_HI
#define SD_DAT1_DM_STRONG PIN_DM_STRONG
#define SD_DAT1_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SD_DAT1_MASK SD_DAT1__MASK
#define SD_DAT1_SHIFT SD_DAT1__SHIFT
#define SD_DAT1_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SD_DAT1_PS (* (reg8 *) SD_DAT1__PS)
/* Data Register */
#define SD_DAT1_DR (* (reg8 *) SD_DAT1__DR)
/* Port Number */
#define SD_DAT1_PRT_NUM (* (reg8 *) SD_DAT1__PRT)
/* Connect to Analog Globals */
#define SD_DAT1_AG (* (reg8 *) SD_DAT1__AG)
/* Analog MUX bux enable */
#define SD_DAT1_AMUX (* (reg8 *) SD_DAT1__AMUX)
/* Bidirectional Enable */
#define SD_DAT1_BIE (* (reg8 *) SD_DAT1__BIE)
/* Bit-mask for Aliased Register Access */
#define SD_DAT1_BIT_MASK (* (reg8 *) SD_DAT1__BIT_MASK)
/* Bypass Enable */
#define SD_DAT1_BYP (* (reg8 *) SD_DAT1__BYP)
/* Port wide control signals */
#define SD_DAT1_CTL (* (reg8 *) SD_DAT1__CTL)
/* Drive Modes */
#define SD_DAT1_DM0 (* (reg8 *) SD_DAT1__DM0)
#define SD_DAT1_DM1 (* (reg8 *) SD_DAT1__DM1)
#define SD_DAT1_DM2 (* (reg8 *) SD_DAT1__DM2)
/* Input Buffer Disable Override */
#define SD_DAT1_INP_DIS (* (reg8 *) SD_DAT1__INP_DIS)
/* LCD Common or Segment Drive */
#define SD_DAT1_LCD_COM_SEG (* (reg8 *) SD_DAT1__LCD_COM_SEG)
/* Enable Segment LCD */
#define SD_DAT1_LCD_EN (* (reg8 *) SD_DAT1__LCD_EN)
/* Slew Rate Control */
#define SD_DAT1_SLW (* (reg8 *) SD_DAT1__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SD_DAT1_PRTDSI__CAPS_SEL (* (reg8 *) SD_DAT1__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SD_DAT1_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_DAT1__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SD_DAT1_PRTDSI__OE_SEL0 (* (reg8 *) SD_DAT1__PRTDSI__OE_SEL0)
#define SD_DAT1_PRTDSI__OE_SEL1 (* (reg8 *) SD_DAT1__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SD_DAT1_PRTDSI__OUT_SEL0 (* (reg8 *) SD_DAT1__PRTDSI__OUT_SEL0)
#define SD_DAT1_PRTDSI__OUT_SEL1 (* (reg8 *) SD_DAT1__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SD_DAT1_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT1__PRTDSI__SYNC_OUT)
#if defined(SD_DAT1__INTSTAT) /* Interrupt Registers */
#define SD_DAT1_INTSTAT (* (reg8 *) SD_DAT1__INTSTAT)
#define SD_DAT1_SNAP (* (reg8 *) SD_DAT1__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SD_DAT1_H */
/* [] END OF FILE */

32
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/*******************************************************************************
* File Name: SD_DAT1.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SD_DAT1_ALIASES_H) /* Pins SD_DAT1_ALIASES_H */
#define CY_PINS_SD_DAT1_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SD_DAT1_0 SD_DAT1__0__PC
#endif /* End Pins SD_DAT1_ALIASES_H */
/* [] END OF FILE */

137
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/*******************************************************************************
* File Name: SD_DAT2.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SD_DAT2.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SD_DAT2__PORT == 15 && ((SD_DAT2__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SD_DAT2_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SD_DAT2_Write(uint8 value)
{
uint8 staticBits = (SD_DAT2_DR & (uint8)(~SD_DAT2_MASK));
SD_DAT2_DR = staticBits | ((uint8)(value << SD_DAT2_SHIFT) & SD_DAT2_MASK);
}
/*******************************************************************************
* Function Name: SD_DAT2_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SD_DAT2_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SD_DAT2_0, mode);
}
/*******************************************************************************
* Function Name: SD_DAT2_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SD_DAT2_ReadPS calls this function.
*
*******************************************************************************/
uint8 SD_DAT2_Read(void)
{
return (SD_DAT2_PS & SD_DAT2_MASK) >> SD_DAT2_SHIFT;
}
/*******************************************************************************
* Function Name: SD_DAT2_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SD_DAT2_ReadDataReg(void)
{
return (SD_DAT2_DR & SD_DAT2_MASK) >> SD_DAT2_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SD_DAT2_INTSTAT)
/*******************************************************************************
* Function Name: SD_DAT2_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SD_DAT2_ClearInterrupt(void)
{
return (SD_DAT2_INTSTAT & SD_DAT2_MASK) >> SD_DAT2_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SD_DAT2.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SD_DAT2_H) /* Pins SD_DAT2_H */
#define CY_PINS_SD_DAT2_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SD_DAT2_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SD_DAT2__PORT == 15 && ((SD_DAT2__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SD_DAT2_Write(uint8 value) ;
void SD_DAT2_SetDriveMode(uint8 mode) ;
uint8 SD_DAT2_ReadDataReg(void) ;
uint8 SD_DAT2_Read(void) ;
uint8 SD_DAT2_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SD_DAT2_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SD_DAT2_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SD_DAT2_DM_RES_UP PIN_DM_RES_UP
#define SD_DAT2_DM_RES_DWN PIN_DM_RES_DWN
#define SD_DAT2_DM_OD_LO PIN_DM_OD_LO
#define SD_DAT2_DM_OD_HI PIN_DM_OD_HI
#define SD_DAT2_DM_STRONG PIN_DM_STRONG
#define SD_DAT2_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SD_DAT2_MASK SD_DAT2__MASK
#define SD_DAT2_SHIFT SD_DAT2__SHIFT
#define SD_DAT2_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SD_DAT2_PS (* (reg8 *) SD_DAT2__PS)
/* Data Register */
#define SD_DAT2_DR (* (reg8 *) SD_DAT2__DR)
/* Port Number */
#define SD_DAT2_PRT_NUM (* (reg8 *) SD_DAT2__PRT)
/* Connect to Analog Globals */
#define SD_DAT2_AG (* (reg8 *) SD_DAT2__AG)
/* Analog MUX bux enable */
#define SD_DAT2_AMUX (* (reg8 *) SD_DAT2__AMUX)
/* Bidirectional Enable */
#define SD_DAT2_BIE (* (reg8 *) SD_DAT2__BIE)
/* Bit-mask for Aliased Register Access */
#define SD_DAT2_BIT_MASK (* (reg8 *) SD_DAT2__BIT_MASK)
/* Bypass Enable */
#define SD_DAT2_BYP (* (reg8 *) SD_DAT2__BYP)
/* Port wide control signals */
#define SD_DAT2_CTL (* (reg8 *) SD_DAT2__CTL)
/* Drive Modes */
#define SD_DAT2_DM0 (* (reg8 *) SD_DAT2__DM0)
#define SD_DAT2_DM1 (* (reg8 *) SD_DAT2__DM1)
#define SD_DAT2_DM2 (* (reg8 *) SD_DAT2__DM2)
/* Input Buffer Disable Override */
#define SD_DAT2_INP_DIS (* (reg8 *) SD_DAT2__INP_DIS)
/* LCD Common or Segment Drive */
#define SD_DAT2_LCD_COM_SEG (* (reg8 *) SD_DAT2__LCD_COM_SEG)
/* Enable Segment LCD */
#define SD_DAT2_LCD_EN (* (reg8 *) SD_DAT2__LCD_EN)
/* Slew Rate Control */
#define SD_DAT2_SLW (* (reg8 *) SD_DAT2__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SD_DAT2_PRTDSI__CAPS_SEL (* (reg8 *) SD_DAT2__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SD_DAT2_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_DAT2__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SD_DAT2_PRTDSI__OE_SEL0 (* (reg8 *) SD_DAT2__PRTDSI__OE_SEL0)
#define SD_DAT2_PRTDSI__OE_SEL1 (* (reg8 *) SD_DAT2__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SD_DAT2_PRTDSI__OUT_SEL0 (* (reg8 *) SD_DAT2__PRTDSI__OUT_SEL0)
#define SD_DAT2_PRTDSI__OUT_SEL1 (* (reg8 *) SD_DAT2__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SD_DAT2_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT2__PRTDSI__SYNC_OUT)
#if defined(SD_DAT2__INTSTAT) /* Interrupt Registers */
#define SD_DAT2_INTSTAT (* (reg8 *) SD_DAT2__INTSTAT)
#define SD_DAT2_SNAP (* (reg8 *) SD_DAT2__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SD_DAT2_H */
/* [] END OF FILE */

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