Cleanup old logic

Xga

Gerbers/profile.gbr

@@ -13,186 +13,10 @@ G01*
 
 D10*
 X0Y0D02*
-X1016000Y0D01*
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-X0Y406400D01*
+X965200Y0D01*
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-X64994Y14041D01*
-X63999Y13970D01*
-X63001Y13970D01*
 M02*

Gerbers/soldermask_bottom.gbr

@@ -9,314 +9,292 @@ G75*
 5,1,8,0,0,1.08239X$1,22.5*%
 G01*
 %ADD10C,1.422400*%
-%ADD11C,5.181600*%
-%ADD12P,1.649562X8X292.500000*%
-%ADD13C,2.895600*%
-%ADD14C,1.422400*%
-%ADD15P,1.539592X8X22.500000*%
-%ADD16P,1.649562X8X112.500000*%
-%ADD17P,1.539592X8X292.500000*%
-%ADD18P,1.539592X8X202.500000*%
-%ADD19P,1.759533X8X292.500000*%
+%ADD11C,1.524000*%
+%ADD12C,1.625600*%
+%ADD13C,1.009600*%
+%ADD14R,1.701800X1.270000*%
+%ADD15C,1.609600*%
 
 
 D10*
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-X622300Y286004D01*
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 D11*
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 D12*
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-D11*
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-D12*
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 D10*
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-D16*
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 D15*
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-X127000Y190500D03*
-X177800Y190500D03*
-X127000Y215900D03*
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Gerbers/solderpaste_bottom.gbr

@@ -8,6 +8,14 @@ G75*
 %AMOC8*
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 M02*

Gerbers/solderpaste_top.gbr

@@ -10,110 +10,815 @@ G75*
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 M02*

README.md

@@ -1,28 +1,32 @@
 # SE-VGA
-Simple CPLD project to mirror the Mac SE video over VGA. No scaling is performed -- the Mac 512x342 video is displayed letterboxed (black borders) in a 640x480 frame. Plugs into SE PDS slot and snoops writes to the frame buffer memory locations. Writes are cached and copied to VRAM.
+Simple CPLD project to mirror the Mac SE video over VGA. The image is pixel-doubled to 1024x684 and displayed letterboxed (black borders) in a 1024x768 video frame. Device snoops writes to the frame buffer memory locations and caches the data to its own VRAM for display. Plugs into the PDS slot in a Mac SE, or plugs in place of the CPU on Mac SE, Plus, or 512k models (128k Mac could be made to work with some adjustment to the CPLD configuration, but is not a configuration supported by the memory selection jumpers). Tested and working on a Mac SE and a Mac Plus, both with 4MB of RAM.
 
-Circuit uses a single AFT1508AS-100AU CPLD, a pair of 256kbit (32kx8) 15ns SRAM, and a 25.175MHz can oscillator, along with some passives.
+Circuit uses a single AFT1508AS-7AX100 CPLD, a pair of 256kbit (32kx8) 15ns or faster SRAM, a 13MHz crystal with 5x clock multiplier for 65MHz pixel clock, along with some passives.
 
 ## Bill of Materials
 
 | Qty | Manufacturer    | Part No.           | Name               | Description                                   |
 |:---:|:----------------|:-------------------|:-------------------|:----------------------------------------------|
-|  2  | Renesas         | 71256SA12TPG       | VRAM-ALT, VRAM-MAIN| 32kx8 15ns SRAM                               | 
-|  1  | Microchip       | ATF1508AS-7AX100   | LOGIC              | ATF1508AS or EPM7128 CPLD                     |
-|  1  | CTS             | MXO45HS-3C-25M1750 | CLK                | 25.175MHz oscillator                          |
+|  2  | ISSI            | IS61C256AL-12TLI   | VRAM-ALT, VRAM-MAIN| 32kx8 12ns SRAM, TSOP-28                      | 
+|  1  | Microchip       | ATF1508AS-7AX100   | LOGIC              | ATF1508AS or EPM7128 CPLD, TQFP-100           |
+|  1  | Renesas / IDT   | 511MLF             | CLK                | Programmable Clock Multiplier, SO-8           |
+|  1  | ECS             | ECS-130-20-46X     | XTAL               | 13MHz Crystal, HC-46X or HC-49UP              |
 |  1  | TE Connectivity | 650473-5           | PDS                | DIN 41612 Right-angle 3x32 pin male connector |
-|  5  |                 |                    | C1, C2, C3, C4, C5 | 0.1uF Decoupling Capacitor                    |
+|  5  |                 |                    | C1, C2, C3, C4, C5 | 0.1uF Decoupling Capacitor, 0805              |
 |  2  |                 |                    | C6, C7             | 10uF Electrolytic Capacitor                   |
-|  2  |                 |                    | R7, R8, R9         | 4k7 pullup resistor (value not critical)      |
-|  3  |                 |                    | R1, R2, R3         | 470 ohm resistor                              |
-|  3  |                 |                    | R4, R5, R6         | 75 ohm resistor                               |
+|  2  |                 |                    | C8, C9             | 20pF Capacitor, 0805                          |
+|  2  |                 |                    | R3, R4, R5         | 10k pullup resistor, 0805 or axial            |
+|  3  |                 |                    | R2                 | 460 ohm resistor, 0805 or axial               |
+|  3  |                 |                    | R1                 | 75 ohm resistor, 0805 or axial                |
 |  1  |                 |                    | PGM                | 2x5 pin header for CPLD JTAG programming      |
-|  1  |                 |                    | VGA                | 6x1 pin header for VGA adapter                |
+|  1  |                 |                    | VGA                | 2x5 pin header for VGA adapter                |
 |  1  |                 |                    | RAMSIZE            | 3x2 jumper                                    |
+|  1  |                 |                    | BRD                | 64-pin DIP header, male                       |
+|  1  |                 |                    | CPU                | 64-pin DIP socket, female                     |
 
 ## Frame Buffer Addressing
 
-The Mac SE primary framebuffer starts at 0x5900 below the top of RAM. Since it's not in a static location for every system, the system's memory configuration is needed. This is set by three ramSize jumpers, which mask CPU address bits 21, 20, 19. Not all possible ramSize selections are valid memory sizes when using 30-pin SIMMs in the Mac SE. In theory, these combinations could be possible when using PDS memory expansion cards, but this is unlikely. The chart below indicates the valid & invalid ramSize configurations and the corresponding installed SIMM combinations.
+The Mac primary framebuffer starts at 0x5900 below the top of RAM. Since it's not in a static location for every system, the system's memory configuration is needed. This is set by three ramSize jumpers, which mask CPU address bits 21, 20, 19. Not all possible ramSize selections are valid memory sizes when using 30-pin SIMMs in the Mac SE. In theory, these combinations could be possible when using PDS memory expansion cards, but this is unlikely. The chart below indicates the valid & invalid ramSize configurations and the corresponding installed SIMM combinations.
 
 |ramSize|Main Framebuffer|Alt Framebuffer|RAM Top Address + 1|RAM Size|Installed SIMMs               |
 |:-----:|:--------------:|:-------------:|:-----------------:|:------:|------------------------------|
@@ -36,7 +40,6 @@ The Mac SE primary framebuffer starts at 0x5900 below the top of RAM. Since it's
 | 000   | 0x07a700       | 0x072700      | 0x080000          | 0.5MB  | `[256kB 256kB][ ---   --- ]` |
 
 ## CPLD Pin Assignments
-Logic uses nearly all available resources in the CPLD (104 of 128 macrocells).
 
 |signal|Direction|Pin|
 |---|---|---|
@@ -124,11 +127,10 @@ Logic uses nearly all available resources in the CPLD (104 of 128 macrocells).
 |TMS|Input|PIN_15
 
 ## Known Issues
-First run schematic and gerbers used three pairs of resistor dividers for R, G, B output channels. A better approach would be to use a single divider and tie all three output channels together. Also 470 ohm is a bit too high, so the image is quite dark.
-
-The resistor footprints are too small for 1/4W parts. Might work with 1/8W parts.
-
-Timing for the SE window is a bit off. It appears to be starting the window a couple pixels early on the left, and it might be cutting off the last pixel or two on the right.
-
-## Wish List
-I would like to bump up the pixel clock to 65MHz and run the output video at 1024x768@60. This would allow the SE frame to be pixel doubled to 1024x684, which would only leave black bars on the top and bottom, instead of on all four sides. This could also be a useful starting point for a future project to output video for an early iPad display for units missing a CRT. 
+- ~~First run schematic and gerbers used three pairs of resistor dividers for R, G, B output channels. A better approach would be to use a single divider and tie all three output channels together. Also 470 ohm is a bit too high, so the image is quite dark.~~ Removed extraneous resistor dividers. Changed 470ohm resistor to 460.
+- ~~The resistor footprints are too small for 1/4W parts. Might work with 1/8W parts.~~ Added footprints for 0805 resistors. 
+- ~~Timing for the SE window is a bit off. It appears to be starting the window a couple pixels early on the left, and it might be cutting off the last pixel or two on the right.~~
+- The ninth vertical line is missing from the output image, and there is a black line two pixels from the right side of the screen.
+- There is still a timing issue with VRAM writes. Some writes seem to get missed.
+- Additional decoupling is needed when using the board in 512k/Plus Macs. Without decoupling on every VCC pin of the CPLD and decoupling for the 68000 CPU, overall system stability is severely impacted. 
+- Support for alternate frame buffer is currently disabled. 

cpusnoop.sv

@@ -1,245 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * CPU Bus Snoop
- * techav
- * 2021-04-06
- ******************************************************************************
- * Watches for writes to frame buffer memory addresses and copies that data
- * into VRAM
- *****************************************************************************/
-
-module cpusnoop (
-    input wire              nReset,     // System Reset signal
-    input wire              pixClock,   // 25.175MHz Pixel Clock
-    input logic [2:0]       seq,        // Sequence count (low 3 bits of hCount)
-    input logic [22:0]      cpuAddr,    // CPU Address bus
-    input logic [15:0]      cpuData,    // CPU Data bus
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input wire              cpuClk,     // CPU Clock
-    output logic [14:0]     vramAddr,   // VRAM Address Bus
-    output logic [7:0]      vramDataOut,// VRAM Data Bus Output
-    output wire             nvramWE,    // VRAM Write strobe
-    output wire             nvramCE0,   // VRAM Main select
-    output wire             nvramCE1,   // VRAM Alt select
-    output wire             vidBufSelOut,// VRAM Video Buffer selection
-    input logic [2:0]       ramSize     // CPU RAM size selection
-);
-
-    wire pendWriteLo;           // low byte write to VRAM pending
-    wire pendWriteHi;           // high byte write to VRAM pending
-    logic [13:0] addrCache;     // store address for cpu writes to framebuffer
-    logic [7:0] dataCacheLo;    // store data for cpu writes to low byte
-    logic [7:0] dataCacheHi;    // store data for cpu writes to high byte
-    wire cpuBufSel;             // is CPU accessing frame buffer?
-    logic [2:0] cycleState;     // state machine state
-    reg cpuCycleEnded;          // mark cpu has ended its cycle
-    reg cpuCycleBufSel;         // which frame buffer was selected for the cpu cycle
-    reg vidBufSel;              // which frame buffer was selected for video output
-
-    // define state machine states
-    parameter
-        S0  =   0,
-        S1  =   1,
-        S2  =   2,
-        S3  =   3,
-        S4  =   4,
-        S5  =   5;
-    
-    // when cpu addresses the framebuffer, set our enable signal
-    /* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
-     * $8000 below the main frame buffer
-     * ramSize is used to mask the CPU Address bits [21:19] to select the amount
-     * of memory installed in the computer. Not all possible ramSize selections
-     * are valid memory sizes when using 30-pin SIMMs in the Mac SE. 
-     * They may be possible using PDS RAM expansion cards.
-     * ramSize  mainBuffer  altBuffer     ramTop+1    ramSize  Valid?       Installed SIMMs
-     *    $7     $3fa700     $3f2700       $400000     4.0MB     Y     [ 1MB   1MB ][ 1MB   1MB ]
-     *    $6     $37a700     $372700       $380000     3.5MB     N
-     *    $5     $2fa700     $2f2700       $300000     3.0MB     N
-     *    $4     $27a700     $272700       $280000     2.5MB     Y     [ 1MB   1MB ][256kB 256kB]
-     *    $3     $1fa700     $1f2700       $200000     2.0MB     Y     [ 1MB   1MB ][ ---   --- ]
-     *    $2     $17a700     $172700       $180000     1.5MB     N  
-     *    $1     $0fa700     $0f2700       $100000     1.0MB     Y     [256kB 256kB][256kB 256kB]
-     *    $0     $07a700     $072700       $080000     0.5MB     Y     [256kB 256kB][ ---   --- ]
-     */
-    always_comb begin
-        // remember cpuAddr is shifted right by one since 68000 does not output A0
-        if(cpuAddr[22:21] == 2'b00                  // initial constant
-                && ramSize == cpuAddr[20:18]        // ram size selection
-                && cpuAddr[17:15] == 3'b111         // trailing constant
-                                                    // next bit is main/alt select
-                && (cpuAddr[13:0] >= 14'h1380       // bottom of buffer range (0x2700>>1)
-                    && cpuAddr[13:0] <= 14'h3e3f)   // top of buffer range (0x7C70>>1)
-                ) begin
-            cpuBufSel <= 1'b1;
-        end else begin
-            cpuBufSel <= 1'b0;
-        end
-    end
-
-    // keep an eye out for cpu ending its cycle
-    always @(negedge pixClock or negedge nReset) begin
-        if(!nReset) cpuCycleEnded <= 0;
-        else if(cycleState == S2) cpuCycleEnded <= 0;
-        else if(ncpuUDS && ncpuLDS
-                    && (cycleState == S3 
-                        || cycleState == S4 
-                        || cycleState == S5
-                        || cycleState == S1)
-                    ) begin
-            cpuCycleEnded <= 1;
-        end else cpuCycleEnded <= cpuCycleEnded;
-    end
-    
-    // CPU Write to VRAM state machine
-    always @(negedge pixClock or negedge nReset) begin
-        if(!nReset) begin
-            cycleState <= S0;
-            pendWriteHi <= 0;
-            pendWriteLo <= 0;
-            addrCache <= 0;
-            dataCacheHi <= 0;
-            dataCacheLo <= 0;
-        end else begin
-            case (cycleState)
-                S0 : begin
-                    // idle state, wait for valid address and ncpuAS asserted
-                    if(ncpuAS == 0 
-                            && cpuBufSel == 1 
-                            && cpuRnW == 0 
-                            && (ncpuLDS == 0 
-                                || ncpuUDS == 0)) begin
-                        pendWriteHi <= !ncpuUDS;
-                        pendWriteLo <= !ncpuLDS;
-                        dataCacheHi <= cpuData[15:8];
-                        dataCacheLo <= cpuData[7:0];
-                        // Valid CPU-VRAM cycle, so subtract constant $1380 from the 
-                        // cpu address and store the result in addrCache register.
-                        // Constant $1380 corresponds to $2700 shifted right by 1.
-                        // Once the selection bits above are masked out, we're left
-                        // with buffer addresses starting at $2700
-                        // e.g. with 4MB of RAM, fram buffer starts at $3FA700
-                        //   buffer address: 0011 1111 1010 0111 0000 0000 = $3FA700
-                        //   vram addr mask: 0000 0000 0011 1111 1111 1111 - $003FFF
-                        //   vram address:   0000 0000 0010 0111 0000 0000 = $002700
-                        // Since CPU is 16-bit and does not provide A0, our cpuAddr
-                        // signals are shifted right by one, so we need to do the same
-                        // to our offset before subtracting it from cpuAddr
-                        //   offset:         0000 0000 0010 0111 0000 0000 = $002700
-                        //   shifted offset: 0000 0000 0001 0011 1000 0000 = $001380
-                        addrCache <= cpuAddr[13:0] - 14'h1380;
-                        // The next address bit selects which frame buffer the CPU
-                        // is writing to for this cycle. 1 = Main ; 0 = Alt
-                        // Invert & save for later
-                        cpuCycleBufSel <= !cpuAddr[14];
-                        
-                        cycleState <= S2;
-                    end else if(ncpuAS == 0 
-                                    && cpuRnW == 0 
-                                    && ncpuUDS == 0 
-                                    && cpuAddr[22:18] == 5'h1D 
-                                    && cpuAddr[11:7] == 5'h1F) begin
-                        // the CPU is addressing VIA Port A. We need to check what
-                        // bit 6 is set to to determine which buffer is selected
-                        // for video output. 1 = Main ; 0 = Alt
-                        vidBufSel <= !cpuData[14];
-                        // now that we've saved the buffer selection, go to state
-                        // S5 to wait for the CPU to end the bus cycle.
-                        cycleState <= S5;
-                    end else begin
-                        cycleState <= S0;
-                    end
-                end
-                S2 : begin
-                    // wait for sequence
-                    if(pendWriteLo && !seq[0]) cycleState <= S3;
-                    else if (pendWriteHi && !seq[0]) cycleState <= S4;
-                    else if (!pendWriteHi && !pendWriteLo) cycleState <= S0;    // in case something weird happens
-                    else cycleState <= S2;
-                end
-                S3 : begin
-                    // write CPU low byte to VRAM
-                    if (seq == 0) begin
-                        cycleState <= S3;   // we shouldn't be here during a read cycle, so delay
-                    end else if(pendWriteHi == 1) begin
-                        cycleState <= S1;   // move on to delay before second write cycle
-                    end else begin
-                        cycleState <= S5;
-                    end
-                    pendWriteLo <= 0;
-                end
-                S4 : begin
-                    // write CPU high byte to VRAM
-                    if (seq == 0) begin
-                        cycleState <= S4;   // we shouldn't be here during a read cycle, so delay
-                    end else begin
-                        cycleState <= S5;
-                    end
-                    pendWriteHi <= 0;
-                end
-                S5 : begin
-                    // wait for CPU to negate both ncpuUDS and ncpuLDS
-                    if(cpuCycleEnded == 1) begin
-                        cycleState <= S0;
-                    end else begin
-                        cycleState <= S5;
-                    end
-                end
-                S1 : begin
-                    // delay moving to second write cycle
-                    if (!seq[0]) cycleState <= S4;
-                    else cycleState <= S1;
-                end
-                default: begin
-                    // how did we end up here? reset to S0
-                    cycleState <= S0;
-                end
-            endcase
-        end
-    end
-
-    always_comb begin
-        // output VRAM address
-        // we actually do an endian swap here assigning the low-order bit of
-        // the VRAM address because the video shift register in the SE loads
-        // a full 16-bit word and shifts out starting with the MSB.
-        // An endian swap here ensures that when we load the VRAM for output
-        // the bits are in the right order. 
-        vramAddr[14:1] <= addrCache[13:0];
-        if(cycleState == S4) begin
-            vramAddr[0] <= 0;
-        end else begin
-            vramAddr[0] <= 1;
-        end
-
-        // Assert VRAM Write signal during CPU Cycle states S3 & S4
-        // Also assert VRAM chip enable signals based on which buffer the CPU
-        // addressed for the VRAM write cycle
-        if(seq != 0 && (cycleState == S3 || cycleState == S4)) begin
-            nvramWE <= 0;
-            nvramCE0 <= cpuCycleBufSel;
-            nvramCE1 <= !cpuCycleBufSel;
-        end else begin
-            nvramWE <= 1;
-            nvramCE0 <= 1;
-            nvramCE1 <= 1;
-        end
-
-        // Output our internal data cache registers on CPU Cycle states S3 & S4
-        // Otherwise, just output 0. This will be muxed for the VRAM data bus
-        // in the next module outside of here.
-        if(cycleState == S3) begin
-            vramDataOut <= dataCacheLo;
-        end else if(cycleState == S4) begin
-            vramDataOut <= dataCacheHi;
-        end else begin
-            vramDataOut <= 0;
-        end
-    end
-
-    assign vidBufSelOut = vidBufSel;
-
-endmodule

se-vga.sv

@@ -1,124 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * Top-level module 
- * techav
- * 2021-04-06
- ******************************************************************************
- * Pulls together all the smaller modules to form the SE-VGA adapter
- *****************************************************************************/
-
-module sevga (
-    input wire              nReset,     // System reset signal
-    input wire              pixClk,     // 25.175MHz pixel clock
-    output wire             nhSync,     // HSync signal
-    output wire             nvSync,     // VSync signal
-    output wire             vidOut,     // 1-bit Monochrome video signal
-
-    output logic [14:0]     vramAddr,   // VRAM Address bus
-    inout logic [7:0]       vramData,   // VRAM Data bus
-    output wire             nvramOE,    // VRAM Read strobe
-    output wire             nvramWE,    // VRAM Write strobe
-    output wire             nvramCE0,   // VRAM Main chip select signal
-    output wire             nvramCE1,   // VRAM Alt chip select signal
-
-    input logic [23:1]      cpuAddr,    // CPU Address bus
-    input logic [15:0]      cpuData,    // CPU Data bus
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input logic [2:0]       ramSize     // Select installed RAM size
-);
-
-logic [9:0] hCount;
-logic [9:0] vCount;
-wire hActive;
-wire hSEActive;
-wire vActive;
-wire vSEActive;
-wire nvramWEpre;            // VRAM Write signal from cpu snoop
-wire nvramCE0pre;
-wire nvramCE1pre;
-wire vidBufSel;
-
-logic [14:0] vidVramAddr;
-logic [14:0] cpuVramAddr;
-logic [7:0] vidVramData;
-wire [7:0] cpuVramData;
-
-// link module that generates all our timing signals
-vgagen vgatiming(
-    .nReset(nReset),
-    .pixClk(pixClk),
-    .hCount(hCount),
-    .hActive(hActive),
-    .hSEActive(hSEActive),
-    .nhSync(nhSync),
-    .vCount(vCount),
-    .vActive(vActive),
-    .vSEActive(vSEActive),
-    .nvSync(nvSync)
-);
-
-// link module that fetches & outputs video data
-vgaout vidvram(
-    .pixClock(pixClk),
-    .nReset(nReset),
-    .hCount(hCount),
-    .vCount(vCount),
-    .hSEActive(hSEActive),
-    .vSEActive(vSEActive),
-    .vramData(vidVramData),
-    .vramAddr(vidVramAddr),
-    .nvramOE(nvramOE),
-    .vidOut(vidOut)
-);
-
-// link module that snoops cpu writes
-cpusnoop cpusnp(    
-    .nReset(nReset),
-    .pixClock(pixClk),
-    .seq(hCount[2:0]),
-    .cpuAddr(cpuAddr),
-    .cpuData(cpuData),
-    .ncpuAS(ncpuAS),
-    .ncpuUDS(ncpuUDS),
-    .ncpuLDS(ncpuLDS),
-    .cpuRnW(cpuRnW),
-    .cpuClk(cpuClk),
-    .vramAddr(cpuVramAddr),
-    .vramDataOut(cpuVramData),
-    .nvramWE(nvramWEpre),
-    .nvramCE0(nvramCE0pre),
-    .nvramCE1(nvramCE1pre),
-    .vidBufSelOut(vidBufSel),
-    .ramSize(ramSize)
-);
-
-always_comb begin
-    // vramAddr muxing
-    if(nvramWEpre == 1'b0) begin
-        vramAddr <= cpuVramAddr;
-    end else if(nvramOE == 0) begin
-        vramAddr <= vidVramAddr;
-    end else begin
-        vramAddr <= 0;
-    end
-end
-
-always_comb begin
-    if(nvramWEpre == 1'b0) begin
-        vramData <= cpuVramData;
-    end else begin
-        vramData <= 8'bZZZZZZZZ;
-    end
-    vidVramData <= vramData;
-end
-
-assign nvramCE0 = (nvramWEpre | nvramCE0pre) & (nvramOE | vidBufSel);
-assign nvramCE1 = (nvramWEpre | nvramCE1pre) & (nvramOE | ~vidBufSel);
-
-//assign nvramWE = nvramWEpre | pixClk;
-assign nvramWE = nvramWEpre;
-
-endmodule

se-xga.sv

@@ -0,0 +1,342 @@
+/******************************************************************************
+ * SE-VGA
+ * Top-level module 
+ * techav
+ * 2021-10-12
+ ******************************************************************************
+ * This is ... mostly working. It has some write glitches and a vertical line
+ * five pixels from the left side of the screen.
+ *****************************************************************************/
+
+module sevga (
+    input wire              nReset,     // System reset signal
+    input wire              pixClk,     // 65MHz pixel clock
+    output wire             nhSync,     // HSync signal
+    output wire             nvSync,     // VSync signal
+    output wire             vidOut,     // 1-bit Monochrome video signal
+
+    output logic [14:0]     vramAddr,   // VRAM Address bus
+    inout logic [7:0]       vramData,   // VRAM Data bus
+    output wire             nvramOE,    // VRAM Read strobe
+    output wire             nvramWE,    // VRAM Write strobe
+    output wire             nvramCE0,   // VRAM Main chip select signal
+    output wire             nvramCE1,   // VRAM Alt chip select signal
+
+    input logic [23:1]      cpuAddr,    // CPU Address bus
+    input logic [15:0]      cpuData,    // CPU Data bus
+    input wire              ncpuAS,     // CPU Address Strobe signal
+    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
+    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
+    input wire              cpuRnW,     // CPU Read/Write select signal
+    input logic [2:0]       ramSize     // Select installed RAM size
+);
+
+/******************************************************************************
+ * Initial Video Signal Timing
+ * The following four functions establish the basic XGA signal timing and 
+ * assert the horizontal and vertical sync signals as appropriate.
+ * These functions are the minimum required for a signal presence detect test.
+ *****************************************************************************/
+logic [10:0] hCount;    // 0..1343
+logic [9:0] vCount;     // 0..805
+wire nhSyncInner;
+
+// Primary video sync counters -- Now more synchronous!
+always @(negedge pixClk) begin
+    if(hCount < 11'd1343) hCount <= hCount + 11'd1;
+    else begin
+        hCount <= 11'd0;
+        if(vCount < 10'd805) vCount <= vCount + 10'd1;
+        else vCount <= 10'd0;
+    end
+end
+
+// horizontal and vertical sync signals
+always_comb begin
+    //if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
+    if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
+    else nhSyncInner <= 1;
+    nhSync <= nhSyncInner;
+
+    if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
+    else nvSync <= 1;
+end
+
+/******************************************************************************
+ * Useful signals
+ * Here we break out a few useful signals, derived from the timing above, that
+ * will help us elsewhere.
+ *****************************************************************************/
+wire hActive, vActive;      // active video signals. vidout black when negated
+wire vidActive;             // active when both hActive and vActive asserted
+wire hLoad;                 // load pixel data from vram when asserted
+
+assign vidActive = hActive & vActive;
+
+always_comb begin
+    if(hCount >= 3 && hCount < 1027) hActive <= 1;
+    else hActive <= 0;
+
+    if(vCount >= 0 && vCount < 684) vActive <= 1;
+    else vActive <= 0;
+
+    if(hCount >= 0 && hCount < 1024 && vActive) hLoad <= 1;
+    else hLoad <= 0;
+end
+
+/******************************************************************************
+ * Primary State Machine
+ * This is the primary state machine which runs the entire system, handling
+ * VRAM reads, VRAM writes, VIA writes, and idle states
+ *****************************************************************************/
+
+// used to align primary state machine with horizontal counter
+wire [3:0] vSeq = hCount[3:0];
+
+// define state machine states (Gray code)
+parameter
+    S0  =   4'b0000,    // VRAM Read 0
+    S1  =   4'b0001,    // VRAM Read 1
+    S2  =   4'b0011,    // Idle
+    S3  =   4'b0010,    // VRAM Write Upper 0
+    S4  =   4'b0110,    // VRAM Write Upper 1
+    S5  =   4'b0111,    // VRAM Write Lower 0
+    S6  =   4'b0101,    // VRAM Write Lower 1
+    S7  =   4'b0100,    // VIA Write
+    S8  =   4'b1100,    // VSync (to be added later)
+    S9  =   4'b1101,    // undefined
+    S10 =   4'b1111,    // undefined
+    S11 =   4'b1110,    // undefined
+    S12 =   4'b1010,    // undefined
+    S13 =   4'b1011,    // undefined
+    S14 =   4'b1001,    // undefined
+    S15 =   4'b1000;    // undefined
+
+logic [3:0] pState;
+
+// And here is the much simplified primary state machine
+always @(negedge pixClk or negedge nReset) begin
+    if(!nReset) pState <= S2;   // resync on reset by jumping to idle state
+    else begin
+        case(pState)
+            S0: pState <= S1;   // first VRAM read state, always move to S1
+            S3: pState <= S4;   // first UDS write state, always move to S4
+            S5: pState <= S6;   // first LDS write state, always move to S6
+            /*S7: begin
+                
+                pState <= S2;
+            end*/
+            S2: begin
+                // here is where everything actually happens.
+                if(vSeq == 4'hF) pState <= S0;   // time for a read state
+                else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
+                else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
+                else if(cpuVIAReq    && !cpuVIASrv    && vSeq < 4'hE) pState <= S7;
+                else pState <= S2;
+            end
+            default: pState <= S2; // everyone ends up at S2 (idle)
+        endcase
+    end
+end
+
+// primary VRAM signal combination, based on the primary state machine
+always_comb begin
+    // VRAM Read Strobe
+    if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
+    else nvramOE <= 1;
+
+    // VRAM Write Strobe
+    if(pState == S3 || pState == S5) nvramWE <= 0;
+    else nvramWE <= 1;
+    
+    // VRAM Chip Enable Signals
+    case(pState)
+        S0, S1: begin
+            if(hLoad) begin
+                nvramCE0 <= ~vidBufSel;
+                nvramCE1 <= vidBufSel;
+            end else begin
+                nvramCE0 <= 1;
+                nvramCE1 <= 1;
+            end
+        end
+        S3, S4, S5, S6: begin
+            nvramCE0 <= ~cpuBufSel;
+            nvramCE1 <= cpuBufSel;
+        end
+        default: begin
+            nvramCE0 <= 1;
+            nvramCE1 <= 1;
+        end
+    endcase
+
+    // VRAM Address Bus
+    case(pState)
+        S0, S1: begin
+            // address bus for read cycles
+            if(hLoad) begin
+                vramAddr[14:6] <= vCount[9:1];
+                vramAddr[5:0] <= hCount[9:4];
+            end else begin
+                vramAddr <= 0;
+            end
+        end
+        S3, S4: begin
+            // address bus for upper write cycles
+            vramAddr[14:1] <= cpuAddrShift;
+            vramAddr[0] <= 0;
+        end
+        S5, S6: begin
+            // address bus for lower write cycles
+            vramAddr[14:1] <= cpuAddrShift;
+            vramAddr[0] <= 1;
+        end
+        default: begin
+            // address bus for idle cycles
+            vramAddr <= 0;
+        end
+    endcase
+
+    // VRAM Data bus
+    case(pState)
+        S3, S4 : vramData <= cpuData[15:8];
+        S5, S6 : vramData <= cpuData[7:0];
+        default: vramData <= 8'hZ;
+    endcase
+end
+
+/******************************************************************************
+ * Video Output Sequencing
+ * Here is the primary video output shift register sequencing.
+ * With these functions in place, it should be possible to strap the VRAM data
+ * signals and see the strapped pattern output on screen.
+ *****************************************************************************/
+logic [8:0] vidData;        // the video data we are displaying
+
+// output shift register
+always @(posedge pixClk) begin
+    if(pState == S1 && hLoad) begin
+        // store VRAM data in shift register
+        vidData[7:0] <= vramData;
+    end else if(!hCount[0] && vidActive) begin
+        // shift out video data
+        vidData[8:1] <= vidData[7:0];
+        vidData[0] <= 1;
+    end
+end
+
+// final video output
+always_comb begin
+    if(vidActive) vidOut <= ~vidData[8];
+    else vidOut <= 0;
+end
+
+/******************************************************************************
+ * CPU Bus Snooping
+ * Watch the CPU bus for writes to the video buffer regions of memory and write
+ * that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
+ * High-order bytes are passed to VRAM on tick states and low-order bytes are 
+ * passed to VRAM on tock states. After the VRAM writes are complete, state
+ * machine waits for the CPU cycle to end before returning to idle.
+ *****************************************************************************/
+
+/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
+ * $8000 below the main frame buffer
+ * ramSize is used to mask the CPU Address bits [21:19] to select the amount
+ * of memory installed in the computer. Not all possible ramSize selections
+ * are valid memory sizes when using 30-pin SIMMs in the Mac SE. 
+ * They may be possible using PDS RAM expansion cards.
+ * ramSize mainBuffer altBuffer ramTop+1 ramSize Valid?      Installed SIMMs
+ *    $7    $3fa700    $3f2700   $400000  4.0MB    Y    [ 1MB   1MB ][ 1MB   1MB ]
+ *    $6    $37a700    $372700   $380000  3.5MB    N
+ *    $5    $2fa700    $2f2700   $300000  3.0MB    N
+ *    $4    $27a700    $272700   $280000  2.5MB    Y    [ 1MB   1MB ][256kB 256kB]
+ *    $3    $1fa700    $1f2700   $200000  2.0MB    Y    [ 1MB   1MB ][ ---   --- ]
+ *    $2    $17a700    $172700   $180000  1.5MB    N  
+ *    $1    $0fa700    $0f2700   $100000  1.0MB    Y    [256kB 256kB][256kB 256kB]
+ *    $0    $07a700    $072700   $080000  0.5MB    Y    [256kB 256kB][ ---   --- ]
+ */
+
+// keep track of pending CPU write requests and whether they have been serviced
+wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
+reg  cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
+wire cpuBufSel;
+wire cpuBufAddr;
+reg vidBufSel;
+wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
+wire cpuBufRange;
+
+// these are some helpful signals that shortcut the CPU buffer & VIA addresses
+always_comb begin
+    /*if(cpuAddr[14:1] >= 14'h1380
+        && cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
+    else cpuBufRange <= 0;*/
+    cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
+    if(!ncpuAS && !cpuRnW
+            && !cpuAddr[23] && !cpuAddr[22]     // first two bits always 0
+            && !(cpuAddr[21] ^ ramSize[2])      // compare with RAM Size bits
+            && !(cpuAddr[20] ^ ramSize[1])
+            && !(cpuAddr[19] ^ ramSize[0])
+            && cpuAddr[18] && cpuAddr[17]       // next three bits always 1
+            && cpuAddr[16]                      // skip 15, it selects buffers
+            && cpuBufRange                      // only select buffer addresses
+    ) begin
+        cpuBufAddr <= 1;
+    end else begin
+        cpuBufAddr <= 0;
+    end
+    cpuBufSel <= ~cpuAddr[15];                   // address bit 15 selects buffer
+
+    if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
+    else cpuUWriteReq <= 0;
+    if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
+    else cpuLWriteReq <= 0;
+
+    // VIA is in address block $E8,0000 - $EF,FFFF
+    // VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
+    // VIA Output Register A is selected when RS[3:0]==$F
+    /*if(!ncpuAS && !cpuRnW && !ncpuUDS
+            && cpuAddr[23] && cpuAddr[22]       // VIA Address Select
+            && cpuAddr[21] && !cpuAddr[20]
+            && cpuAddr[19]
+            && cpuAddr[12] && cpuAddr[11]       // VIA ORA
+            && cpuAddr[10] && cpuAddr[9]
+    ) cpuVIAReq <= 1;
+    else cpuVIAReq <= 0;*/
+    // Mac ROM addresses Data Register A as vBase+vBufA:
+    // $EF,E1FE + (512*15) = $EF,FFFE
+    // shift right by one because no A0 and we get $77,FFFF
+    // This bit is giving me hell, so let's expand it
+    if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
+            && cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
+    else cpuVIAReq <= 0;
+end
+
+// if there's an active CPU request and we've reached the state for servicing
+// that CPU request, then set a flag to mark that we have serviced it
+always @(posedge pixClk or posedge ncpuAS) begin
+    if(ncpuAS) begin
+        cpuUWriteSrv <= 0;
+        cpuLWriteSrv <= 0;
+        cpuVIASrv    <= 0;
+    end else begin
+        if(ncpuAS) begin
+            cpuUWriteSrv <= 0;
+            cpuLWriteSrv <= 0;
+            cpuVIASrv    <= 0;
+        end else begin
+            if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
+            if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
+            if(cpuVIAReq    && pState == S7) cpuVIASrv    <= 1;
+        end
+    end
+end
+
+// store the video buffer selection bit
+always @(posedge pixClk or negedge nReset) begin
+    if(!nReset) vidBufSel <= 0;
+    // fine. no video buffer select. we use Main only.
+    //else if(pState == S7) vidBufSel <= ~cpuData[14];
+end
+
+endmodule

vgacount.sv

@@ -1,74 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA signal counter
- * techav
- * 2021-04-06
- ******************************************************************************
- * Low-level VGA signal counter
- *****************************************************************************/
-
-`ifndef VGACOUNT
-    `define VGACOUNT
-
-module vgacount (
-    input wire              nReset,         // system reset signal
-    input wire              clock,          // counter increment clock
-    output logic [9:0]      count,          // count output
-    output wire             nSync,          // sync pulse
-    output wire             activeVid,      // active video signal
-    output wire             activeSE        // secondary active video signal (SE)
-);
-
-parameter   COUNTMAX=800,       // Total dot count per line or line count per frame
-            SYNCBEGIN=592,      // Dot/Line count where sync pulse begins
-            SYNCEND=688,        // Dot/Line count +1 where sync pulse ends
-            ACTBEGIN=576,       // Dot/Line count where VGA active video begins
-            ACTEND=736,         // Dot/Line count +1 where VGA active video ends
-            SEACTBEGIN=512;     // Dot/Line count +1 where SE video window ends
-
-logic [9:0] counter;
-
-// primary counter
-always @(negedge clock or negedge nReset) begin
-    if(nReset == 1'b0) begin
-        counter <= 10'h0;
-    end else begin
-        if (counter < COUNTMAX) begin
-            counter <= counter + 10'h1;
-        end else begin
-            counter <= 10'h0;
-        end
-    end
-end
-
-
-// combinatorial logic derived from the counters
-always_comb begin
-    // output the count signals
-    count <= counter;
-
-    // Sync pulse
-    if(count >= SYNCBEGIN && count < SYNCEND) begin
-        nSync <= 1'b0;
-    end else begin
-        nSync <= 1'b1;
-    end
-
-    // VGA active video range
-    if(count >= ACTBEGIN && count < ACTEND) begin
-        activeVid <= 1'b0;
-    end else begin
-        activeVid <= 1'b1;
-    end
-
-    // SE active video window within VGA active video range
-    if(count >= SEACTBEGIN) begin
-        activeSE <= 1'b0;
-    end else begin
-        activeSE <= 1'b1;
-    end
-end
-
-endmodule
-
-`endif

vgagen.sv

@@ -1,35 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA timing generator
- * techav
- * 2021-04-06
- ******************************************************************************
- * Generates VGA timing signals & counters
- *****************************************************************************/
-
-`ifndef VGAGEN
-    `define VGAGEN
-
-`include "vgacount.sv"
-
-module vgagen (
-    input wire             nReset,     // master reset signal
-    input wire             pixClk,     // 25.175MHz pixel clock
-    output logic [9:0]     hCount,     // horizontal pixel count
-    output wire            hActive,    // horizontal VGA active video signal
-    output wire            hSEActive,  // horizontal SE active video signal
-    output wire            nhSync,     // horizontal sync pulse signal
-    output logic [9:0]     vCount,     // vertical line count
-    output wire            vActive,    // vertical VGA active video signal
-    output wire            vSEActive,  // vertical SE active video signal
-    output wire            nvSync      // vertical sync pulse signal
-);
-
-// Generate horizontal signal timing
-vgacount #(800,592,688,576,736,512) hoz(nReset,pixClk,hCount,nhSync,hActive,hSEActive);
-// Generate vertical signal timing
-vgacount #(525,421,423,411,456,342) ver(nReset,nhSync,vCount,nvSync,vActive,vSEActive);
-
-endmodule
-
-`endif

vgaout.sv

@@ -1,68 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA video output
- * techav
- * 2021-04-06
- ******************************************************************************
- * Fetches video data from VRAM and shifts out
- *****************************************************************************/
-
-`include "vgashiftout.sv"
-
-module vgaout (
-    input wire          pixClock,
-    input wire          nReset,
-    input logic [9:0]   hCount,
-    input logic [9:0]   vCount,
-    input wire          hSEActive,
-    input wire          vSEActive,
-    input logic [7:0]   vramData,
-    output logic [14:0] vramAddr,
-    output wire         nvramOE,
-    output wire         vidOut
-);
-
-wire vidMuxOut; // pixel data shift out
-wire vidActive; // combined active video signal
-
-wire nVidLoad;  // Load VRAM data into shifter
-vgaShiftOut vOut(
-    .nReset(nReset),
-    .clk(pixClock),
-    .nLoad(nVidLoad),
-    .parIn(vramData),
-    .out(vidMuxOut)
-);
-
-always_comb begin
-    if(hCount[2:0] == 0) nVidLoad <= 0;
-    else nVidLoad <= 1;
-
-    // combined video active signal
-    if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
-        vidActive <= 1'b1;
-    end else begin
-        vidActive <= 1'b0;
-    end
-
-    // video data output
-    if(vidActive == 1'b1) begin
-        vidOut <= ~vidMuxOut;
-    end else begin
-        vidOut <= 1'b0;
-    end
-
-    // vram read signal
-    if(vidActive == 1'b1 && hCount[2:0] == 0) begin
-        nvramOE <= 1'b0;
-    end else begin
-        nvramOE <= 1'b1;
-    end
-
-    // vram address signals
-    // these will be mux'd with cpu addresses externally
-    vramAddr[14:6] <= vCount[8:0];
-    vramAddr[5:0]  <= hCount[8:3];
-end
-    
-endmodule

vgashiftout.sv

@@ -1,84 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA Shift Out
- * techav
- * 2021-04-06
- ******************************************************************************
- * 2-stage shift register for storing & shifting out pixel data
- *****************************************************************************/
-
-`ifndef VGASHIFTOUT
-    `define VGASHIFTOUT
-
-module vgaShiftOut (
-    input wire nReset, clk, nLoad,
-    input logic [7:0] parIn,
-    output wire out
-);
-
-reg [8:0] shiftReg;
-
-always @(negedge clk or negedge nReset) begin
-    if(!nReset) shiftReg <= 0;
-    else begin
-        if(!nLoad) begin
-            shiftReg[8] <= shiftReg[7];
-            shiftReg[7:0] <= parIn;
-        end else begin
-            shiftReg[8:1] <= shiftReg[7:0];
-            shiftReg[0] <= 0;
-        end
-    end
-end
-
-assign out = shiftReg[8];
-
-endmodule
-
-/*
-module vgaShiftOut (
-    input wire nReset,
-    input wire clk,
-    input wire shiftEn,
-    input wire nLoad1,
-    input wire nLoad2,
-    input logic [7:0] parIn,
-    output wire out
-);
-
-    reg [7:0] inReg;
-    reg [7:0] outReg;
-
-    // load data into first stage register on rising edge of pixel clock
-    // if nLoad1 is asserted
-    always @(posedge clk or negedge nReset) begin
-        if(!nReset) inReg <= 0;
-        else if(!nLoad1) inReg <= parIn;
-    end
-
-    // load data into second stage register on falling edge of pixel clock
-    // if nLoad2 is asserted, otherwise if shiftEn is asserted, then shift
-    // video data out. Shift in 0 to fill empty registers
-    always @(negedge clk or negedge nReset) begin
-        if(!nReset) outReg <= 0;
-        else begin
-            if(!nLoad2) outReg <= inReg;
-            else if(shiftEn) begin
-                outReg[7] <= outReg[6];
-                outReg[6] <= outReg[5];
-                outReg[5] <= outReg[4];
-                outReg[4] <= outReg[3];
-                outReg[3] <= outReg[2];
-                outReg[2] <= outReg[1];
-                outReg[1] <= outReg[0];
-                outReg[0] <= 0;
-            end
-        end
-    end
-
-    // high-order bit of the shift register (second stage) is the serial output
-    assign out = outReg[7];
-endmodule
-*/
-
-`endif

vgatest.sv

@@ -1,75 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA Output Test
- * techav
- * 2021-05-14
- ******************************************************************************
- * Test configuration for testily testing testy test hardware. 
- * This is not a part of the actual configuration. It is a separate top-level
- * entity for testing modules and hardware. Outputs a 512x342 pixel window of
- * alternating black and white pixels in a 640x480 resolution screen.
- *****************************************************************************/
-
-// all the same I's and O's as our proper configuration
-module vgatest (
-    input wire              nReset,     // System reset signal
-    input wire              pixClk,     // 25.175MHz pixel clock
-    output wire             nhSync,     // HSync signal
-    output wire             nvSync,     // VSync signal
-    output wire             vidOut,     // 1-bit Monochrome video signal
-
-    output logic [14:0]     vramAddr,   // VRAM Address bus
-    //inout logic [7:0]       vramData,   // VRAM Data bus
-    input logic [7:0]       vramData,
-    output wire             nvramOE,    // VRAM Read strobe
-    output wire             nvramWE,    // VRAM Write strobe
-    output wire             nvramCE0,   // VRAM Main chip select signal
-    output wire             nvramCE1,   // VRAM Alt chip select signal
-
-    input logic [23:1]      cpuAddr,    // CPU Address bus
-    //input logic [15:0]      cpuData,    // CPU Data bus
-    output logic [15:0]     cpuData,
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input logic [2:0]       ramSize     // Select installed RAM size
-);
-
-logic [9:0] hCount, vCount;
-wire hActive, hSEActive;
-wire vActive, vSEActive;
-
-vgagen vgatiming(
-    .nReset(nReset),
-    .pixClk(pixClk),
-    .hCount(hCount),
-    .hActive(hActive),
-    .hSEActive(hSEActive),
-    .nhSync(nhSync),
-    .vCount(vCount),
-    .vActive(vActive),
-    .vSEActive(vSEActive),
-    .nvSync(nvSync)
-);
-
-reg outTog;
-
-always @(negedge pixClk or negedge nReset) begin
-    if(nReset == 0) begin
-        outTog <= 0;
-    end else begin
-        outTog <= !outTog;
-    end
-end
-
-assign vidOut = outTog & hSEActive & vSEActive;
-assign vramAddr = 0;
-assign nvramOE = 1;
-assign nvramWE = 1;
-assign nvramCE0 = 1;
-assign nvramCE1 = 1;
-assign cpuData[7:0] = ~vramData;
-assign cpuData[15:8] = vramData;
-
-endmodule