2023-03-20 05:13:11 +00:00
Release 14.7 - xst P.20131013 (nt64)
2021-10-29 10:04:59 +00:00
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.31 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.33 secs
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--> Reading design: WarpSE.prj
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TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
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Input File Name : "WarpSE.prj"
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Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
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Output File Name : "WarpSE"
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Output Format : NGC
Target Device : XC9500XL CPLDs
---- Source Options
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Top Module Name : WarpSE
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Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
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Optimization Effort : 1
Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
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Compiling verilog file "../RAM.v" in library work
Compiling verilog file "../IOBS.v" in library work
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Module <RAM> compiled
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Compiling verilog file "../IOBM.v" in library work
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Module <IOBS> compiled
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Compiling verilog file "../FSB.v" in library work
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Module <IOBM> compiled
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Compiling verilog file "../CS.v" in library work
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Module <FSB> compiled
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Compiling verilog file "../CNT.v" in library work
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Module <CS> compiled
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Compiling verilog file "../WarpSE.v" in library work
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Module <CNT> compiled
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Module <WarpSE> compiled
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No errors in compilation
Analysis of file <"WarpSE.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <WarpSE> in library <work>.
Analyzing hierarchy for module <CS> in library <work>.
Analyzing hierarchy for module <RAM> in library <work>.
Analyzing hierarchy for module <IOBS> in library <work>.
Analyzing hierarchy for module <IOBM> in library <work>.
Analyzing hierarchy for module <CNT> in library <work>.
Analyzing hierarchy for module <FSB> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <WarpSE>.
Module <WarpSE> is correct for synthesis.
Analyzing module <CS> in library <work>.
Module <CS> is correct for synthesis.
Analyzing module <RAM> in library <work>.
Module <RAM> is correct for synthesis.
Analyzing module <IOBS> in library <work>.
Module <IOBS> is correct for synthesis.
Analyzing module <IOBM> in library <work>.
Module <IOBM> is correct for synthesis.
Analyzing module <CNT> in library <work>.
Module <CNT> is correct for synthesis.
Analyzing module <FSB> in library <work>.
Module <FSB> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <CS>.
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Related source file is "../CS.v".
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Found 1-bit register for signal <nOverlay>.
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Unit <CS> synthesized.
Synthesizing Unit <RAM>.
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Related source file is "../RAM.v".
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Found finite state machine <FSM_0> for signal <RS>.
-----------------------------------------------------------------------
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| States | 8 |
| Transitions | 14 |
| Inputs | 6 |
| Outputs | 8 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 000 |
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| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <nCAS>.
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Found 1-bit register for signal <nOE>.
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Found 1-bit register for signal <RAMReady>.
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Found 1-bit register for signal <BACTr>.
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Found 1-bit register for signal <DTACKr>.
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Found 1-bit register for signal <RASEL>.
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Found 1-bit register for signal <RASEN>.
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Found 1-bit register for signal <RASrf>.
Found 1-bit register for signal <RASrr>.
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Found 1-bit register for signal <RefDone>.
Summary:
inferred 1 Finite State Machine(s).
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inferred 9 D-type flip-flop(s).
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Unit <RAM> synthesized.
Synthesizing Unit <IOBS>.
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Related source file is "../IOBS.v".
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Found finite state machine <FSM_1> for signal <TS>.
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-----------------------------------------------------------------------
| States | 4 |
| Transitions | 10 |
| Inputs | 5 |
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| Outputs | 5 |
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| Clock | CLK (rising_edge) |
| Power Up State | 00 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <IORDREQ>.
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Found 1-bit register for signal <IOL0>.
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Found 1-bit register for signal <IOWRREQ>.
Found 1-bit register for signal <IONPReady>.
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Found 1-bit register for signal <IOU0>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <ALE1>.
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Found 1-bit register for signal <nBERR_FSB>.
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Found 1-bit register for signal <Clear1>.
Found 1-bit register for signal <IOACTr>.
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Found 1-bit register for signal <IODONEr>.
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Found 1-bit register for signal <IOL1>.
Found 1-bit register for signal <IORW1>.
Found 1-bit register for signal <IOU1>.
Found 1-bit register for signal <Load1>.
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Found 1-bit register for signal <Sent>.
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Summary:
inferred 1 Finite State Machine(s).
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inferred 10 D-type flip-flop(s).
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Unit <IOBS> synthesized.
Synthesizing Unit <IOBM>.
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Related source file is "../IOBM.v".
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Found finite state machine <FSM_2> for signal <IOS>.
-----------------------------------------------------------------------
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| States | 7 |
| Transitions | 13 |
| Inputs | 5 |
| Outputs | 7 |
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| Clock | C16M (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
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Found 1-bit register for signal <IOBERR>.
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Found 1-bit register for signal <nASout>.
Found 1-bit register for signal <IOACT>.
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Found 1-bit register for signal <IODONE>.
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Found 1-bit register for signal <nLDS>.
Found 1-bit register for signal <nUDS>.
Found 1-bit register for signal <nDinLE>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <nVMA>.
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Found 1-bit register for signal <C8Mr>.
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Found 1-bit register for signal <DoutOE>.
Found 1-bit register for signal <Er>.
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Found 4-bit up counter for signal <ES>.
Found 1-bit register for signal <IORDREQr>.
Found 1-bit register for signal <IOS0>.
Found 1-bit register for signal <IOWRREQr>.
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Found 1-bit register for signal <VPAr>.
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Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
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inferred 15 D-type flip-flop(s).
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Unit <IOBM> synthesized.
Synthesizing Unit <CNT>.
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Related source file is "../CNT.v".
Found finite state machine <FSM_3> for signal <IS>.
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-----------------------------------------------------------------------
| States | 4 |
| Transitions | 8 |
| Inputs | 2 |
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| Outputs | 5 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 00 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
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Found 1-bit register for signal <RefUrg>.
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Found 1-bit register for signal <RefReq>.
Found 1-bit register for signal <nBR_IOB>.
Found 1-bit register for signal <nRESout>.
Found 1-bit register for signal <AoutOE>.
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Found 1-bit register for signal <QoSReady>.
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Found 2-bit adder for signal <$add0000> created at line 67.
Found 12-bit adder for signal <$add0001> created at line 68.
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Found 2-bit register for signal <Er>.
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Found 12-bit register for signal <LTimer>.
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Found 1-bit register for signal <LTimerTC>.
Found 1-bit register for signal <nIPL2r>.
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Found 4-bit up counter for signal <Timer>.
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Found 1-bit register for signal <TimerTC>.
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Found 4-bit up counter for signal <WS>.
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Summary:
inferred 1 Finite State Machine(s).
inferred 2 Counter(s).
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inferred 11 D-type flip-flop(s).
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inferred 2 Adder/Subtractor(s).
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Unit <CNT> synthesized.
Synthesizing Unit <FSB>.
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Related source file is "../FSB.v".
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Found 1-bit register for signal <nVPA>.
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Found 1-bit register for signal <nDTACK>.
Found 1-bit register for signal <ASrf>.
Summary:
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inferred 3 D-type flip-flop(s).
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Unit <FSB> synthesized.
Synthesizing Unit <WarpSE>.
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Related source file is "../WarpSE.v".
WARNING:Xst:647 - Input <C20MEN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <SW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <nBG_IOB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 1-bit tristate buffer for signal <nAS_IOB>.
Found 1-bit tristate buffer for signal <nLDS_IOB>.
Found 1-bit tristate buffer for signal <nRES>.
Found 1-bit tristate buffer for signal <nUDS_IOB>.
Found 1-bit tristate buffer for signal <nVMA_IOB>.
Summary:
inferred 5 Tristate(s).
Unit <WarpSE> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
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# Adders/Subtractors : 2
12-bit adder : 1
2-bit adder : 1
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# Counters : 3
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4-bit up counter : 3
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# Registers : 68
1-bit register : 67
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2-bit register : 1
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# Tristates : 5
1-bit tristate buffer : 5
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_3> for best encoding.
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Optimizing FSM <cnt/IS/FSM> on signal <IS[1:2]> with johnson encoding.
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-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 11
11 | 10
-------------------
Analyzing FSM <FSM_2> for best encoding.
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Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:7]> with one-hot encoding.
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-------------------
State | Encoding
-------------------
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000 | 0000001
010 | 0000010
011 | 0000100
100 | 0001000
101 | 0010000
110 | 0100000
111 | 1000000
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-------------------
Analyzing FSM <FSM_1> for best encoding.
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Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
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-------------------
State | Encoding
-------------------
00 | 00
11 | 01
10 | 11
01 | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <ram/RS/FSM> on signal <RS[1:8]> with one-hot encoding.
-------------------
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State | Encoding
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-------------------
000 | 00000001
100 | 00000010
001 | 00000100
010 | 00001000
011 | 00010000
101 | 00100000
110 | 01000000
111 | 10000000
-------------------
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=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 4
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# Adders/Subtractors : 2
12-bit adder : 1
2-bit adder : 1
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# Counters : 3
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4-bit up counter : 3
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# Registers : 48
Flip-Flops : 48
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=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <WarpSE> ...
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Optimizing unit <CS> ...
implementation constraint: INIT=r : nOverlay
Optimizing unit <RAM> ...
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implementation constraint: INIT=s : RS_FSM_FFd8
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implementation constraint: INIT=r : RASEL
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implementation constraint: INIT=r : RASrr
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implementation constraint: INIT=r : RASEN
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implementation constraint: INIT=r : RS_FSM_FFd1
implementation constraint: INIT=r : RS_FSM_FFd2
implementation constraint: INIT=r : RS_FSM_FFd3
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implementation constraint: INIT=r : RS_FSM_FFd4
implementation constraint: INIT=r : RS_FSM_FFd5
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implementation constraint: INIT=r : RS_FSM_FFd6
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implementation constraint: INIT=r : RS_FSM_FFd7
implementation constraint: INIT=r : RASrf
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Optimizing unit <IOBS> ...
implementation constraint: INIT=r : IOACTr
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implementation constraint: INIT=r : TS_FSM_FFd2
implementation constraint: INIT=r : Sent
implementation constraint: INIT=r : TS_FSM_FFd1
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Optimizing unit <FSB> ...
implementation constraint: INIT=r : ASrf
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Optimizing unit <IOBM> ...
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implementation constraint: INIT=s : IOS_FSM_FFd7
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implementation constraint: INIT=r : DoutOE
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implementation constraint: INIT=r : IOS_FSM_FFd6
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implementation constraint: INIT=r : IOS_FSM_FFd1
implementation constraint: INIT=r : IOS_FSM_FFd2
implementation constraint: INIT=r : IOS_FSM_FFd3
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implementation constraint: INIT=r : IOS_FSM_FFd4
implementation constraint: INIT=r : IOS_FSM_FFd5
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Optimizing unit <CNT> ...
implementation constraint: INIT=r : Timer_1
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implementation constraint: INIT=r : IS_FSM_FFd2
implementation constraint: INIT=r : IS_FSM_FFd1
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implementation constraint: INIT=r : Timer_2
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implementation constraint: INIT=r : Timer_0
implementation constraint: INIT=r : WS_3
implementation constraint: INIT=r : WS_0
implementation constraint: INIT=r : WS_1
implementation constraint: INIT=r : WS_2
implementation constraint: INIT=r : Timer_3
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=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : WarpSE.ngr
Top Level Output File Name : WarpSE
Output Format : NGC
Optimization Goal : Speed
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Keep Hierarchy : Yes
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Target Technology : XC9500XL CPLDs
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 75
Cell Usage :
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# BELS : 672
# AND2 : 211
# AND3 : 29
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# AND4 : 12
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# AND5 : 2
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# AND7 : 2
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# AND8 : 4
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# GND : 6
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# INV : 262
# OR2 : 105
# OR3 : 14
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# OR4 : 4
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# VCC : 1
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# XOR2 : 20
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# FlipFlops/Latches : 100
# FD : 68
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# FDC : 2
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# FDCE : 29
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# FDP : 1
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# IO Buffers : 70
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# IBUF : 35
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# IOBUFE : 1
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# OBUF : 30
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# OBUFE : 4
=========================================================================
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Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.44 secs
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-->
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Total memory usage is 266948 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 3 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
