add from other repo
This commit is contained in:
Zane Kaminski
commit
6986fad3ae
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|
@ -0,0 +1,29 @@
|
|||
# For PCBs designed using KiCad: http://www.kicad-pcb.org/
|
||||
# Format documentation: http://kicad-pcb.org/help/file-formats/
|
||||
|
||||
# Temporary files
|
||||
*.000
|
||||
*.bak
|
||||
*.bck
|
||||
*.kicad_pcb-bak
|
||||
*.sch-bak
|
||||
*~
|
||||
_autosave-*
|
||||
*.tmp
|
||||
*-rescue.lib
|
||||
*-save.pro
|
||||
*-save.kicad_pcb
|
||||
fp-info-cache
|
||||
|
||||
# Netlist files (exported from Eeschema)
|
||||
*.net
|
||||
|
||||
# Autorouter files (exported from Pcbnew)
|
||||
*.dsn
|
||||
*.ses
|
||||
|
||||
# Exported BOM files
|
||||
*.xml
|
||||
*.csv
|
||||
|
||||
*.DS_Store
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 8 10
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
Wire Wire Line
|
||||
3950 2500 3950 2250
|
||||
Wire Wire Line
|
||||
3950 2750 3950 2500
|
||||
Connection ~ 3950 2500
|
||||
Wire Wire Line
|
||||
3850 2500 3850 2350
|
||||
Wire Wire Line
|
||||
3850 2650 3850 2500
|
||||
Connection ~ 3850 2500
|
||||
Wire Wire Line
|
||||
3850 2500 3950 2500
|
||||
Wire Wire Line
|
||||
4050 2750 3950 2750
|
||||
Wire Wire Line
|
||||
3950 2250 4050 2250
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6141AC14
|
||||
P 3750 2650
|
||||
AR Path="/6141AC14" Ref="R?" Part="1"
|
||||
AR Path="/61BD72BF/6141AC14" Ref="R?" Part="1"
|
||||
AR Path="/61350D21/6141AC14" Ref="R2" Part="1"
|
||||
AR Path="/61BE63BD/6141AC14" Ref="R?" Part="1"
|
||||
AR Path="/61BE8523/6141AC14" Ref="R?" Part="1"
|
||||
AR Path="/61A87B62/6141AC14" Ref="R?" Part="1"
|
||||
F 0 "R2" V 3600 2650 50 0000 C CNN
|
||||
F 1 "22" V 3700 2650 50 0000 C BNN
|
||||
F 2 "stdpads:R_0603" H 3750 2650 50 0001 C CNN
|
||||
F 3 "~" H 3750 2650 50 0001 C CNN
|
||||
1 3750 2650
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 6141A918
|
||||
P 3750 2350
|
||||
AR Path="/6141A918" Ref="R?" Part="1"
|
||||
AR Path="/61BD72BF/6141A918" Ref="R?" Part="1"
|
||||
AR Path="/61350D21/6141A918" Ref="R1" Part="1"
|
||||
AR Path="/61BE63BD/6141A918" Ref="R?" Part="1"
|
||||
AR Path="/61BE8523/6141A918" Ref="R?" Part="1"
|
||||
AR Path="/61A87B62/6141A918" Ref="R?" Part="1"
|
||||
F 0 "R1" V 3600 2350 50 0000 C CNN
|
||||
F 1 "22" V 3700 2350 50 0000 C BNN
|
||||
F 2 "stdpads:R_0603" H 3750 2350 50 0001 C CNN
|
||||
F 3 "~" H 3750 2350 50 0001 C CNN
|
||||
1 3750 2350
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 613B7144
|
||||
P 3500 4350
|
||||
AR Path="/613B7144" Ref="#PWR?" Part="1"
|
||||
AR Path="/61350D21/613B7144" Ref="#PWR0123" Part="1"
|
||||
AR Path="/61BE63BD/613B7144" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BE8523/613B7144" Ref="#PWR?" Part="1"
|
||||
AR Path="/61A87B62/613B7144" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0123" H 3500 4100 50 0001 C CNN
|
||||
F 1 "GND" H 3500 4200 50 0000 C CNN
|
||||
F 2 "" H 3500 4350 50 0001 C CNN
|
||||
F 3 "" H 3500 4350 50 0001 C CNN
|
||||
1 3500 4350
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 613B713D
|
||||
P 3500 4250
|
||||
AR Path="/613B713D" Ref="C?" Part="1"
|
||||
AR Path="/61350D21/613B713D" Ref="C6" Part="1"
|
||||
AR Path="/61BE63BD/613B713D" Ref="C?" Part="1"
|
||||
AR Path="/61BE8523/613B713D" Ref="C?" Part="1"
|
||||
AR Path="/61A87B62/613B713D" Ref="C?" Part="1"
|
||||
F 0 "C6" H 3550 4300 50 0000 L CNN
|
||||
F 1 "2u2" H 3550 4200 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 3500 4250 50 0001 C CNN
|
||||
F 3 "~" H 3500 4250 50 0001 C CNN
|
||||
1 3500 4250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3100 4150 3500 4150
|
||||
Wire Wire Line
|
||||
3100 4350 3500 4350
|
||||
$Comp
|
||||
L power:+3V3 #PWR?
|
||||
U 1 1 613B7131
|
||||
P 3100 4150
|
||||
AR Path="/613B7131" Ref="#PWR?" Part="1"
|
||||
AR Path="/61350D21/613B7131" Ref="#PWR0122" Part="1"
|
||||
AR Path="/61BE63BD/613B7131" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BE8523/613B7131" Ref="#PWR?" Part="1"
|
||||
AR Path="/61A87B62/613B7131" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0122" H 3100 4000 50 0001 C CNN
|
||||
F 1 "+3V3" H 3100 4300 50 0000 C CNN
|
||||
F 2 "" H 3100 4150 50 0001 C CNN
|
||||
F 3 "" H 3100 4150 50 0001 C CNN
|
||||
1 3100 4150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 3100 4150
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 613B711A
|
||||
P 3100 4250
|
||||
AR Path="/613B711A" Ref="C?" Part="1"
|
||||
AR Path="/61350D21/613B711A" Ref="C5" Part="1"
|
||||
AR Path="/61BE63BD/613B711A" Ref="C?" Part="1"
|
||||
AR Path="/61BE8523/613B711A" Ref="C?" Part="1"
|
||||
AR Path="/61A87B62/613B711A" Ref="C?" Part="1"
|
||||
F 0 "C5" H 3150 4300 50 0000 L CNN
|
||||
F 1 "2u2" H 3150 4200 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 3100 4250 50 0001 C CNN
|
||||
F 3 "~" H 3100 4250 50 0001 C CNN
|
||||
1 3100 4250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text HLabel 3650 2650 0 50 Output ~ 0
|
||||
RCLK
|
||||
Text HLabel 3650 2350 0 50 Output ~ 0
|
||||
MCLK
|
||||
$Comp
|
||||
L GW_Logic:Oscillator_4P U?
|
||||
U 1 1 61BF03AA
|
||||
P 4400 2250
|
||||
AR Path="/61BF03AA" Ref="U?" Part="1"
|
||||
AR Path="/61BD72BF/61BF03AA" Ref="U?" Part="1"
|
||||
AR Path="/61350D21/61BF03AA" Ref="U4" Part="1"
|
||||
AR Path="/61BE63BD/61BF03AA" Ref="U?" Part="1"
|
||||
AR Path="/61BE8523/61BF03AA" Ref="U?" Part="1"
|
||||
AR Path="/61A87B62/61BF03AA" Ref="U?" Part="1"
|
||||
F 0 "U4" H 4400 2550 50 0000 C BNN
|
||||
F 1 "20M" H 4400 2500 50 0000 C CNN
|
||||
F 2 "stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm" H 4400 2250 50 0001 C CNN
|
||||
F 3 "" H 4400 2250 50 0001 C CNN
|
||||
1 4400 2250
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L GW_Logic:Oscillator_4P U?
|
||||
U 1 1 61BF03A4
|
||||
P 4400 2750
|
||||
AR Path="/61BF03A4" Ref="U?" Part="1"
|
||||
AR Path="/61BD72BF/61BF03A4" Ref="U?" Part="1"
|
||||
AR Path="/61350D21/61BF03A4" Ref="U5" Part="1"
|
||||
AR Path="/61BE63BD/61BF03A4" Ref="U?" Part="1"
|
||||
AR Path="/61BE8523/61BF03A4" Ref="U?" Part="1"
|
||||
AR Path="/61A87B62/61BF03A4" Ref="U?" Part="1"
|
||||
F 0 "U5" H 4400 3050 50 0000 C BNN
|
||||
F 1 "25M" H 4400 3000 50 0000 C CNN
|
||||
F 2 "stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm" H 4400 2750 50 0001 C CNN
|
||||
F 3 "" H 4400 2750 50 0001 C CNN
|
||||
1 4400 2750
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3V3 #PWR?
|
||||
U 1 1 61BF039E
|
||||
P 4050 2150
|
||||
AR Path="/5F723173/61BF039E" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BF039E" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BD72BF/61BF039E" Ref="#PWR?" Part="1"
|
||||
AR Path="/61350D21/61BF039E" Ref="#PWR0117" Part="1"
|
||||
AR Path="/61BE63BD/61BF039E" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BE8523/61BF039E" Ref="#PWR?" Part="1"
|
||||
AR Path="/61A87B62/61BF039E" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0117" H 4050 2000 50 0001 C CNN
|
||||
F 1 "+3V3" H 4050 2300 50 0000 C CNN
|
||||
F 2 "" H 4050 2150 50 0001 C CNN
|
||||
F 3 "" H 4050 2150 50 0001 C CNN
|
||||
1 4050 2150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3V3 #PWR?
|
||||
U 1 1 61BF0398
|
||||
P 4050 2650
|
||||
AR Path="/5F723173/61BF0398" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BF0398" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BD72BF/61BF0398" Ref="#PWR?" Part="1"
|
||||
AR Path="/61350D21/61BF0398" Ref="#PWR0116" Part="1"
|
||||
AR Path="/61BE63BD/61BF0398" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BE8523/61BF0398" Ref="#PWR?" Part="1"
|
||||
AR Path="/61A87B62/61BF0398" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0116" H 4050 2500 50 0001 C CNN
|
||||
F 1 "+3V3" H 4050 2800 50 0000 C CNN
|
||||
F 2 "" H 4050 2650 50 0001 C CNN
|
||||
F 3 "" H 4050 2650 50 0001 C CNN
|
||||
1 4050 2650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 61BF038C
|
||||
P 4750 2750
|
||||
AR Path="/5F72F108/61BF038C" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BF038C" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BD72BF/61BF038C" Ref="#PWR?" Part="1"
|
||||
AR Path="/61350D21/61BF038C" Ref="#PWR0114" Part="1"
|
||||
AR Path="/61BE63BD/61BF038C" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BE8523/61BF038C" Ref="#PWR?" Part="1"
|
||||
AR Path="/61A87B62/61BF038C" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0114" H 4750 2500 50 0001 C CNN
|
||||
F 1 "GND" H 4750 2600 50 0000 C CNN
|
||||
F 2 "" H 4750 2750 50 0001 C CNN
|
||||
F 3 "" H 4750 2750 50 0001 C CNN
|
||||
1 4750 2750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 61BF0386
|
||||
P 4750 2250
|
||||
AR Path="/5F72F108/61BF0386" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BF0386" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BD72BF/61BF0386" Ref="#PWR?" Part="1"
|
||||
AR Path="/61350D21/61BF0386" Ref="#PWR0113" Part="1"
|
||||
AR Path="/61BE63BD/61BF0386" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BE8523/61BF0386" Ref="#PWR?" Part="1"
|
||||
AR Path="/61A87B62/61BF0386" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0113" H 4750 2000 50 0001 C CNN
|
||||
F 1 "GND" H 4750 2100 50 0000 C CNN
|
||||
F 2 "" H 4750 2250 50 0001 C CNN
|
||||
F 3 "" H 4750 2250 50 0001 C CNN
|
||||
1 4750 2250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text HLabel 4750 2150 2 50 Input ~ 0
|
||||
CK20EN
|
||||
Text HLabel 4750 2650 2 50 Input ~ 0
|
||||
CK25EN
|
||||
Connection ~ 3500 4350
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,551 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 7 10
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
Text HLabel 10400 2900 2 50 Output ~ 0
|
||||
Mac~AS~
|
||||
Text HLabel 10400 2300 2 50 Output ~ 0
|
||||
Mac~VMA~
|
||||
Text HLabel 10400 2600 2 50 Input ~ 0
|
||||
Mac~DTACK~
|
||||
Text HLabel 10400 2500 2 50 Input ~ 0
|
||||
Mac~VPA~
|
||||
Text HLabel 10400 2400 2 50 Input ~ 0
|
||||
Mac~BERR~
|
||||
Text HLabel 8400 3600 0 50 Input ~ 0
|
||||
MacE
|
||||
Text Label 8400 2000 2 50 ~ 0
|
||||
A22
|
||||
Text Label 8400 1900 2 50 ~ 0
|
||||
A21
|
||||
Text Label 8400 1800 2 50 ~ 0
|
||||
A20
|
||||
Text Label 8400 1700 2 50 ~ 0
|
||||
A19
|
||||
Text Label 8400 1600 2 50 ~ 0
|
||||
A18
|
||||
Text Label 8400 1500 2 50 ~ 0
|
||||
A17
|
||||
Text Label 8400 1400 2 50 ~ 0
|
||||
A16
|
||||
Text HLabel 8400 3400 0 50 Input ~ 0
|
||||
C8M
|
||||
Text HLabel 8400 2100 0 50 Input ~ 0
|
||||
C16M
|
||||
Text HLabel 10400 1100 2 50 Output ~ 0
|
||||
ROM~CS~
|
||||
Text HLabel 10400 2800 2 50 Output ~ 0
|
||||
Mac~UDS~
|
||||
Text HLabel 10400 2700 2 50 Output ~ 0
|
||||
Mac~LDS~
|
||||
Text HLabel 8400 3900 0 50 Input ~ 0
|
||||
AccR~W~
|
||||
Text HLabel 8400 4600 0 50 Output ~ 0
|
||||
Dout~OE~
|
||||
Text HLabel 8400 4500 0 50 Output ~ 0
|
||||
Aout~OE~
|
||||
Text HLabel 8400 4700 0 50 Output ~ 0
|
||||
Din~OE~
|
||||
Text HLabel 10400 3200 2 50 Output ~ 0
|
||||
DinLE
|
||||
Text HLabel 10400 4600 2 50 Output ~ 0
|
||||
~RAS~
|
||||
Text HLabel 10400 4700 2 50 Output ~ 0
|
||||
L~WE~
|
||||
Text HLabel 10400 4800 2 50 Output ~ 0
|
||||
U~WE~
|
||||
Text HLabel 8400 5000 0 50 Output ~ 0
|
||||
Acc~VPA~
|
||||
Text HLabel 8400 4100 0 50 Input ~ 0
|
||||
Acc~AS~
|
||||
Text HLabel 8400 4000 0 50 Input ~ 0
|
||||
Acc~LDS~
|
||||
Text HLabel 8400 4200 0 50 Input ~ 0
|
||||
Acc~UDS~
|
||||
Text HLabel 8400 4900 0 50 Output ~ 0
|
||||
Acc~BERR~
|
||||
Text HLabel 8400 3800 0 50 Output ~ 0
|
||||
Acc~DTACK
|
||||
Text Label 8400 1300 2 50 ~ 0
|
||||
A15
|
||||
Text Label 8400 1200 2 50 ~ 0
|
||||
A14
|
||||
Text Label 8400 1100 2 50 ~ 0
|
||||
A13
|
||||
Text Label 8400 3200 2 50 ~ 0
|
||||
A12
|
||||
Text Label 8400 3100 2 50 ~ 0
|
||||
A11
|
||||
Text Label 8400 3000 2 50 ~ 0
|
||||
A10
|
||||
Text Label 8400 2900 2 50 ~ 0
|
||||
A9
|
||||
Text Label 8400 2800 2 50 ~ 0
|
||||
A8
|
||||
Text Label 8400 2700 2 50 ~ 0
|
||||
A7
|
||||
Text Label 8400 2600 2 50 ~ 0
|
||||
A6
|
||||
Text Label 8400 2500 2 50 ~ 0
|
||||
A5
|
||||
Entry Wire Line
|
||||
10700 3700 10600 3800
|
||||
Entry Wire Line
|
||||
10700 3800 10600 3900
|
||||
Entry Wire Line
|
||||
10700 3600 10600 3700
|
||||
Wire Wire Line
|
||||
10400 3700 10600 3700
|
||||
Wire Wire Line
|
||||
10400 4500 10600 4500
|
||||
Text Label 10400 4500 0 50 ~ 0
|
||||
RA11
|
||||
Text Label 10400 3700 0 50 ~ 0
|
||||
RA8
|
||||
Wire Wire Line
|
||||
8400 3200 8100 3200
|
||||
Wire Wire Line
|
||||
8400 3100 8100 3100
|
||||
Wire Wire Line
|
||||
8400 3000 8100 3000
|
||||
Wire Wire Line
|
||||
8400 2800 8100 2800
|
||||
Wire Wire Line
|
||||
8400 2700 8100 2700
|
||||
Wire Wire Line
|
||||
8400 2600 8100 2600
|
||||
Wire Wire Line
|
||||
8400 2500 8100 2500
|
||||
Wire Wire Line
|
||||
8400 1100 8100 1100
|
||||
Wire Wire Line
|
||||
8400 2900 8100 2900
|
||||
Wire Bus Line
|
||||
8000 1000 7950 1000
|
||||
Entry Wire Line
|
||||
8000 1700 8100 1800
|
||||
Entry Wire Line
|
||||
8000 1800 8100 1900
|
||||
Wire Wire Line
|
||||
8400 2000 8100 2000
|
||||
Wire Wire Line
|
||||
8400 1900 8100 1900
|
||||
Entry Wire Line
|
||||
8000 1400 8100 1500
|
||||
Entry Wire Line
|
||||
8000 1600 8100 1700
|
||||
Wire Wire Line
|
||||
8400 1800 8100 1800
|
||||
Wire Wire Line
|
||||
8400 1600 8100 1600
|
||||
Entry Wire Line
|
||||
8000 1200 8100 1300
|
||||
Entry Wire Line
|
||||
8000 1300 8100 1400
|
||||
Wire Wire Line
|
||||
8400 1500 8100 1500
|
||||
Wire Wire Line
|
||||
8400 1400 8100 1400
|
||||
Entry Wire Line
|
||||
8000 1000 8100 1100
|
||||
Entry Wire Line
|
||||
8000 1100 8100 1200
|
||||
Wire Wire Line
|
||||
8400 1300 8100 1300
|
||||
Wire Wire Line
|
||||
8400 1200 8100 1200
|
||||
Entry Wire Line
|
||||
8000 1900 8100 2000
|
||||
Text HLabel 7950 1000 0 50 Input ~ 0
|
||||
A[23..1]
|
||||
Entry Wire Line
|
||||
8000 1500 8100 1600
|
||||
Wire Wire Line
|
||||
8400 1700 8100 1700
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616131D5
|
||||
P 4700 7450
|
||||
AR Path="/616131D5" Ref="C?" Part="1"
|
||||
AR Path="/5F723173/616131D5" Ref="C27" Part="1"
|
||||
F 0 "C27" H 4750 7500 50 0000 L CNN
|
||||
F 1 "2u2" H 4750 7400 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 4700 7450 50 0001 C CNN
|
||||
F 3 "~" H 4700 7450 50 0001 C CNN
|
||||
1 4700 7450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4300 7350 4700 7350
|
||||
Connection ~ 4700 7350
|
||||
Wire Wire Line
|
||||
4700 7350 5100 7350
|
||||
Wire Wire Line
|
||||
4300 7550 4700 7550
|
||||
Connection ~ 4700 7550
|
||||
Wire Wire Line
|
||||
4700 7550 5100 7550
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616131E1
|
||||
P 5100 7450
|
||||
AR Path="/616131E1" Ref="C?" Part="1"
|
||||
AR Path="/5F723173/616131E1" Ref="C28" Part="1"
|
||||
F 0 "C28" H 5150 7500 50 0000 L CNN
|
||||
F 1 "2u2" H 5150 7400 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 5100 7450 50 0001 C CNN
|
||||
F 3 "~" H 5100 7450 50 0001 C CNN
|
||||
1 5100 7450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 5100 7350
|
||||
Wire Wire Line
|
||||
5100 7350 5500 7350
|
||||
Connection ~ 5100 7550
|
||||
Wire Wire Line
|
||||
5100 7550 5500 7550
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616131EB
|
||||
P 5500 7450
|
||||
AR Path="/616131EB" Ref="C?" Part="1"
|
||||
AR Path="/5F723173/616131EB" Ref="C29" Part="1"
|
||||
F 0 "C29" H 5550 7500 50 0000 L CNN
|
||||
F 1 "2u2" H 5550 7400 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 5500 7450 50 0001 C CNN
|
||||
F 3 "~" H 5500 7450 50 0001 C CNN
|
||||
1 5500 7450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 5500 7350
|
||||
Wire Wire Line
|
||||
5500 7350 5900 7350
|
||||
Connection ~ 5500 7550
|
||||
Wire Wire Line
|
||||
5500 7550 5900 7550
|
||||
$Comp
|
||||
L power:+3V3 #PWR?
|
||||
U 1 1 616131F5
|
||||
P 4300 7350
|
||||
AR Path="/616131F5" Ref="#PWR?" Part="1"
|
||||
AR Path="/5F723173/616131F5" Ref="#PWR0158" Part="1"
|
||||
F 0 "#PWR0158" H 4300 7200 50 0001 C CNN
|
||||
F 1 "+3V3" H 4300 7500 50 0000 C CNN
|
||||
F 2 "" H 4300 7350 50 0001 C CNN
|
||||
F 3 "" H 4300 7350 50 0001 C CNN
|
||||
1 4300 7350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 4300 7350
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616131FC
|
||||
P 4300 7450
|
||||
AR Path="/616131FC" Ref="C?" Part="1"
|
||||
AR Path="/5F723173/616131FC" Ref="C26" Part="1"
|
||||
F 0 "C26" H 4350 7500 50 0000 L CNN
|
||||
F 1 "2u2" H 4350 7400 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 4300 7450 50 0001 C CNN
|
||||
F 3 "~" H 4300 7450 50 0001 C CNN
|
||||
1 4300 7450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 61613208
|
||||
P 6300 7450
|
||||
AR Path="/61613208" Ref="C?" Part="1"
|
||||
AR Path="/5F723173/61613208" Ref="C31" Part="1"
|
||||
F 0 "C31" H 6350 7500 50 0000 L CNN
|
||||
F 1 "2u2" H 6350 7400 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 6300 7450 50 0001 C CNN
|
||||
F 3 "~" H 6300 7450 50 0001 C CNN
|
||||
1 6300 7450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 6161320E
|
||||
P 5900 7450
|
||||
AR Path="/6161320E" Ref="C?" Part="1"
|
||||
AR Path="/5F723173/6161320E" Ref="C30" Part="1"
|
||||
F 0 "C30" H 5950 7500 50 0000 L CNN
|
||||
F 1 "2u2" H 5950 7400 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 5900 7450 50 0001 C CNN
|
||||
F 3 "~" H 5900 7450 50 0001 C CNN
|
||||
1 5900 7450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 5900 7350
|
||||
Wire Wire Line
|
||||
5900 7350 6300 7350
|
||||
Connection ~ 6300 7550
|
||||
Connection ~ 5900 7550
|
||||
Wire Wire Line
|
||||
5900 7550 6300 7550
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 616151A9
|
||||
P 6700 7550
|
||||
AR Path="/616151A9" Ref="#PWR?" Part="1"
|
||||
AR Path="/5F723173/616151A9" Ref="#PWR0159" Part="1"
|
||||
F 0 "#PWR0159" H 6700 7300 50 0001 C CNN
|
||||
F 1 "GND" H 6700 7400 50 0000 C CNN
|
||||
F 2 "" H 6700 7550 50 0001 C CNN
|
||||
F 3 "" H 6700 7550 50 0001 C CNN
|
||||
1 6700 7550
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616151AF
|
||||
P 6700 7450
|
||||
AR Path="/616151AF" Ref="C?" Part="1"
|
||||
AR Path="/5F723173/616151AF" Ref="C32" Part="1"
|
||||
F 0 "C32" H 6750 7500 50 0000 L CNN
|
||||
F 1 "2u2" H 6750 7400 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 6700 7450 50 0001 C CNN
|
||||
F 3 "~" H 6700 7450 50 0001 C CNN
|
||||
1 6700 7450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6300 7350 6700 7350
|
||||
Connection ~ 6700 7550
|
||||
Wire Wire Line
|
||||
6300 7550 6700 7550
|
||||
Connection ~ 6300 7350
|
||||
$Comp
|
||||
L power:+3V3 #PWR0160
|
||||
U 1 1 6164065B
|
||||
P 9100 800
|
||||
F 0 "#PWR0160" H 9100 650 50 0001 C CNN
|
||||
F 1 "+3V3" H 9100 950 50 0000 C CNN
|
||||
F 2 "" H 9100 800 50 0001 C CNN
|
||||
F 3 "" H 9100 800 50 0001 C CNN
|
||||
1 9100 800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0161
|
||||
U 1 1 6164325E
|
||||
P 9800 6200
|
||||
F 0 "#PWR0161" H 9800 5950 50 0001 C CNN
|
||||
F 1 "GND" H 9800 6050 50 0000 C CNN
|
||||
F 2 "" H 9800 6200 50 0001 C CNN
|
||||
F 3 "" H 9800 6200 50 0001 C CNN
|
||||
1 9800 6200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text HLabel 8400 3700 0 50 Input ~ 0
|
||||
FCLK
|
||||
Text HLabel 8400 2400 0 50 Output ~ 0
|
||||
~RESET~r
|
||||
Text HLabel 10400 3100 2 50 Output ~ 0
|
||||
ADoutLE0
|
||||
Text HLabel 10400 3000 2 50 Output ~ 0
|
||||
ADoutLE1
|
||||
Text HLabel 8400 2300 0 50 Output ~ 0
|
||||
~RESET~r
|
||||
Text HLabel 8400 4800 0 50 Input ~ 0
|
||||
~RESET~
|
||||
Entry Wire Line
|
||||
10700 4400 10600 4500
|
||||
Wire Bus Line
|
||||
10700 3300 10750 3300
|
||||
Text HLabel 10750 3300 2 50 Output ~ 0
|
||||
RA[11..0]
|
||||
Connection ~ 9700 6200
|
||||
Wire Wire Line
|
||||
9600 6200 9500 6200
|
||||
Connection ~ 9600 6200
|
||||
Connection ~ 9500 6200
|
||||
Wire Wire Line
|
||||
9500 6200 9400 6200
|
||||
Wire Wire Line
|
||||
9400 6200 9300 6200
|
||||
Connection ~ 9400 6200
|
||||
Connection ~ 9300 6200
|
||||
Wire Wire Line
|
||||
9300 6200 9200 6200
|
||||
Wire Wire Line
|
||||
9200 6200 9100 6200
|
||||
Connection ~ 9200 6200
|
||||
Connection ~ 9800 6200
|
||||
Wire Wire Line
|
||||
9700 6200 9600 6200
|
||||
Wire Wire Line
|
||||
9800 6200 9700 6200
|
||||
Connection ~ 9600 800
|
||||
Wire Wire Line
|
||||
9600 800 9700 800
|
||||
Wire Wire Line
|
||||
9500 800 9600 800
|
||||
Connection ~ 9500 800
|
||||
Connection ~ 9400 800
|
||||
Wire Wire Line
|
||||
9400 800 9500 800
|
||||
Wire Wire Line
|
||||
9300 800 9400 800
|
||||
Connection ~ 9300 800
|
||||
Connection ~ 9200 800
|
||||
Connection ~ 9100 800
|
||||
Wire Wire Line
|
||||
9200 800 9300 800
|
||||
Wire Wire Line
|
||||
9100 800 9200 800
|
||||
$Comp
|
||||
L CPLD_Xilinx:XC95144XL-TQ100 U1
|
||||
U 1 1 6318B3C7
|
||||
P 9400 3500
|
||||
F 0 "U1" H 9400 3800 50 0000 C CNN
|
||||
F 1 "XC95144XL-TQ100" H 9400 3700 50 0000 C CNN
|
||||
F 2 "stdpads:TQFP-100_14x14mm_P0.5mm" H 9400 3500 50 0001 C CNN
|
||||
F 3 "https://www.xilinx.com/support/documentation/data_sheets/ds056.pdf" H 9400 3500 50 0001 C CNN
|
||||
1 9400 3500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 8400 5400 2 50 ~ 0
|
||||
A4
|
||||
Text Label 8400 5300 2 50 ~ 0
|
||||
A3
|
||||
Text Label 8400 5200 2 50 ~ 0
|
||||
A2
|
||||
Text Label 8400 5100 2 50 ~ 0
|
||||
A1
|
||||
Entry Wire Line
|
||||
8000 2800 8100 2900
|
||||
Entry Wire Line
|
||||
8000 3000 8100 3100
|
||||
Entry Wire Line
|
||||
8000 2600 8100 2700
|
||||
Entry Wire Line
|
||||
8000 2700 8100 2800
|
||||
Entry Wire Line
|
||||
8000 2400 8100 2500
|
||||
Entry Wire Line
|
||||
8000 2500 8100 2600
|
||||
Entry Wire Line
|
||||
8000 2900 8100 3000
|
||||
Entry Wire Line
|
||||
8000 3100 8100 3200
|
||||
Text Label 8400 3500 2 50 ~ 0
|
||||
A23
|
||||
Entry Wire Line
|
||||
8000 5000 8100 5100
|
||||
Entry Wire Line
|
||||
8000 5200 8100 5300
|
||||
Entry Wire Line
|
||||
8000 5100 8100 5200
|
||||
Entry Wire Line
|
||||
8000 5300 8100 5400
|
||||
Wire Wire Line
|
||||
8100 5400 8400 5400
|
||||
Wire Wire Line
|
||||
8100 5100 8400 5100
|
||||
Wire Wire Line
|
||||
8100 5300 8400 5300
|
||||
Wire Wire Line
|
||||
8100 5200 8400 5200
|
||||
Wire Wire Line
|
||||
8400 3500 8100 3500
|
||||
Entry Wire Line
|
||||
8000 3400 8100 3500
|
||||
Wire Wire Line
|
||||
10600 3800 10400 3800
|
||||
Text Label 10400 3900 0 50 ~ 0
|
||||
RA9
|
||||
Text Label 10400 3800 0 50 ~ 0
|
||||
RA10
|
||||
Wire Wire Line
|
||||
10400 3900 10600 3900
|
||||
Entry Wire Line
|
||||
10700 1500 10600 1600
|
||||
Entry Wire Line
|
||||
10700 1600 10600 1700
|
||||
Entry Wire Line
|
||||
10700 1800 10600 1900
|
||||
Entry Wire Line
|
||||
10700 1700 10600 1800
|
||||
Entry Wire Line
|
||||
10700 3400 10600 3500
|
||||
Entry Wire Line
|
||||
10700 3300 10600 3400
|
||||
Entry Wire Line
|
||||
10700 3500 10600 3600
|
||||
Wire Wire Line
|
||||
10400 3400 10600 3400
|
||||
Text Label 10400 3400 0 50 ~ 0
|
||||
RA1
|
||||
Text Label 10400 3600 0 50 ~ 0
|
||||
RA0
|
||||
Wire Wire Line
|
||||
10600 3600 10400 3600
|
||||
Text Label 10400 1800 0 50 ~ 0
|
||||
RA2
|
||||
Text Label 10400 1600 0 50 ~ 0
|
||||
RA3
|
||||
Text Label 10400 1500 0 50 ~ 0
|
||||
RA4
|
||||
Text Label 10400 1700 0 50 ~ 0
|
||||
RA5
|
||||
Text Label 10400 1900 0 50 ~ 0
|
||||
RA6
|
||||
Text Label 10400 3500 0 50 ~ 0
|
||||
RA7
|
||||
Wire Wire Line
|
||||
10400 3500 10600 3500
|
||||
Wire Wire Line
|
||||
10400 1900 10600 1900
|
||||
Wire Wire Line
|
||||
10400 1700 10600 1700
|
||||
Wire Wire Line
|
||||
10400 1500 10600 1500
|
||||
Wire Wire Line
|
||||
10400 1600 10600 1600
|
||||
Wire Wire Line
|
||||
10400 1800 10600 1800
|
||||
Text HLabel 10400 1300 2 50 Output ~ 0
|
||||
~OE~
|
||||
Text HLabel 10400 1200 2 50 Output ~ 0
|
||||
~CAS~
|
||||
Text HLabel 8400 4300 0 50 Output ~ 0
|
||||
ROM~WE~
|
||||
Wire Bus Line
|
||||
10700 1400 10750 1400
|
||||
Text HLabel 10750 1400 2 50 Output ~ 0
|
||||
RA[11..0]
|
||||
Entry Wire Line
|
||||
10700 1400 10600 1500
|
||||
Text HLabel 10400 4900 2 50 Input ~ 0
|
||||
SW0
|
||||
Text HLabel 10400 4200 2 50 Input ~ 0
|
||||
SW1
|
||||
Text HLabel 10400 4100 2 50 Output ~ 0
|
||||
CKEN
|
||||
Text HLabel 10400 5600 2 50 Input ~ 0
|
||||
TDI
|
||||
Text HLabel 10400 5700 2 50 Input ~ 0
|
||||
TMS
|
||||
Text HLabel 10400 5800 2 50 Input ~ 0
|
||||
TCK
|
||||
Text HLabel 10400 5900 2 50 Output ~ 0
|
||||
TDO
|
||||
Wire Bus Line
|
||||
10700 1400 10700 1800
|
||||
Wire Bus Line
|
||||
10700 3300 10700 4400
|
||||
Wire Bus Line
|
||||
8000 1000 8000 5300
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 6 10
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
Wire Wire Line
|
||||
4050 3400 4050 3300
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 61A8BBE0
|
||||
P 4050 3100
|
||||
AR Path="/61A8BBE0" Ref="R?" Part="1"
|
||||
AR Path="/61BD72BF/61A8BBE0" Ref="R?" Part="1"
|
||||
AR Path="/61350D21/61A8BBE0" Ref="R?" Part="1"
|
||||
AR Path="/61BE63BD/61A8BBE0" Ref="R?" Part="1"
|
||||
AR Path="/61BE8523/61A8BBE0" Ref="R?" Part="1"
|
||||
AR Path="/61A87B62/61A8BBE0" Ref="R4" Part="1"
|
||||
AR Path="/61B15767/61A8BBE0" Ref="R?" Part="1"
|
||||
F 0 "R4" H 4109 3146 50 0000 L CNN
|
||||
F 1 "10k" H 4109 3055 50 0000 L CNN
|
||||
F 2 "stdpads:R_0603" H 4050 3100 50 0001 C CNN
|
||||
F 3 "~" H 4050 3100 50 0001 C CNN
|
||||
1 4050 3100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R_Small R?
|
||||
U 1 1 61A8BBE6
|
||||
P 3750 3100
|
||||
AR Path="/61A8BBE6" Ref="R?" Part="1"
|
||||
AR Path="/61BD72BF/61A8BBE6" Ref="R?" Part="1"
|
||||
AR Path="/61350D21/61A8BBE6" Ref="R?" Part="1"
|
||||
AR Path="/61BE63BD/61A8BBE6" Ref="R?" Part="1"
|
||||
AR Path="/61BE8523/61A8BBE6" Ref="R?" Part="1"
|
||||
AR Path="/61A87B62/61A8BBE6" Ref="R3" Part="1"
|
||||
AR Path="/61B15767/61A8BBE6" Ref="R?" Part="1"
|
||||
F 0 "R3" H 3809 3146 50 0000 L CNN
|
||||
F 1 "10k" H 3809 3055 50 0000 L CNN
|
||||
F 2 "stdpads:R_0603" H 3750 3100 50 0001 C CNN
|
||||
F 3 "~" H 3750 3100 50 0001 C CNN
|
||||
1 3750 3100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3650 3300 4050 3300
|
||||
Wire Wire Line
|
||||
3750 3500 4050 3500
|
||||
Wire Wire Line
|
||||
3750 3200 3750 3400
|
||||
Wire Wire Line
|
||||
4050 3300 4050 3200
|
||||
Connection ~ 4050 3300
|
||||
Wire Wire Line
|
||||
3750 3000 4050 3000
|
||||
Connection ~ 4050 3000
|
||||
Wire Wire Line
|
||||
4650 3400 4650 3500
|
||||
$Comp
|
||||
L power:+3V3 #PWR?
|
||||
U 1 1 61A8C306
|
||||
P 4050 3000
|
||||
AR Path="/5F723173/61A8C306" Ref="#PWR?" Part="1"
|
||||
AR Path="/61A8C306" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BD72BF/61A8C306" Ref="#PWR?" Part="1"
|
||||
AR Path="/61350D21/61A8C306" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BE63BD/61A8C306" Ref="#PWR?" Part="1"
|
||||
AR Path="/61BE8523/61A8C306" Ref="#PWR?" Part="1"
|
||||
AR Path="/61A87B62/61A8C306" Ref="#PWR0115" Part="1"
|
||||
AR Path="/61B15767/61A8C306" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0115" H 4050 2850 50 0001 C CNN
|
||||
F 1 "+3V3" H 4050 3150 50 0000 C CNN
|
||||
F 2 "" H 4050 3000 50 0001 C CNN
|
||||
F 3 "" H 4050 3000 50 0001 C CNN
|
||||
1 4050 3000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0118
|
||||
U 1 1 61A8CA42
|
||||
P 4650 3500
|
||||
AR Path="/61A87B62/61A8CA42" Ref="#PWR0118" Part="1"
|
||||
AR Path="/61B15767/61A8CA42" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0118" H 4650 3250 50 0001 C CNN
|
||||
F 1 "GND" H 4650 3350 50 0000 C CNN
|
||||
F 2 "" H 4650 3500 50 0001 C CNN
|
||||
F 3 "" H 4650 3500 50 0001 C CNN
|
||||
1 4650 3500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 4650 3500
|
||||
$Comp
|
||||
L Switch:SW_DIP_x02 SW?
|
||||
U 1 1 61A8BBD9
|
||||
P 4350 3500
|
||||
AR Path="/61A8BBD9" Ref="SW?" Part="1"
|
||||
AR Path="/61BD72BF/61A8BBD9" Ref="SW?" Part="1"
|
||||
AR Path="/61350D21/61A8BBD9" Ref="SW?" Part="1"
|
||||
AR Path="/61BE63BD/61A8BBD9" Ref="SW?" Part="1"
|
||||
AR Path="/61BE8523/61A8BBD9" Ref="SW?" Part="1"
|
||||
AR Path="/61A87B62/61A8BBD9" Ref="SW1" Part="1"
|
||||
AR Path="/61B15767/61A8BBD9" Ref="SW?" Part="1"
|
||||
F 0 "SW1" H 4350 3750 50 0000 C CNN
|
||||
F 1 "OSCSEL" H 4350 3350 50 0000 C CNN
|
||||
F 2 "stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm" H 4350 3500 50 0001 C CNN
|
||||
F 3 "~" H 4350 3500 50 0001 C CNN
|
||||
1 4350 3500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3750 3400 3650 3400
|
||||
Connection ~ 3750 3400
|
||||
Wire Wire Line
|
||||
3750 3400 3750 3500
|
||||
Text HLabel 3650 3300 0 50 Output ~ 0
|
||||
SW0
|
||||
Text HLabel 3650 3400 0 50 Output ~ 0
|
||||
SW1
|
||||
$EndSCHEMATC
|
||||
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|
||||
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|
||||
<title>Garrett's Workshop - Warp-SE Timing</title>
|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
</head>
|
||||
|
||||
<body onload="WaveDrom.ProcessAll()">
|
||||
<h1>Garrett's Workshop Warp-SE 20 MHz 68HC000 Accelerator Documentation</h1>
|
||||
|
||||
<h2>System Block Diagram</h2>
|
||||
<img src="CPLD.png" style="width:100%;" />
|
||||
|
||||
<h2>Relevant Timing Parameters</h2>
|
||||
<p>Some relevant timing parameters to which the bus timings were designed are as follows:</p>
|
||||
<table>
|
||||
<tr><th>Parameter</th><th>Value</th><th>Description</th></tr>
|
||||
<tr><td>tPD_CPLD</td> <td>10ns</td> <td>asynchronous propagation delay</td></tr>
|
||||
<tr><td>tCO_CPLD</td> <td>6ns</td> <td>clock-to-output delay</td></tr>
|
||||
<tr><td>tSU_CPLD</td> <td>6ns</td> <td>global clock setup time</td></tr>
|
||||
<tr><td>tRAS_DRAM</td> <td>60ns</td> <td>RAS pulse width / access time</td></tr>
|
||||
<tr><td>tASR_DRAM</td> <td>0ns</td> <td>row address setup time before RAS</td></tr>
|
||||
<tr><td>tRAH_DRAM</td> <td>10ns</td> <td>row address hold time after RAS</td></tr>
|
||||
<tr><td>tRCD_DRAM</td> <td>20ns</td> <td>minimum RAS-to-CAS delay</td></tr>
|
||||
<tr><td>tASC_DRAM</td> <td>0ns</td> <td>column address setup time before CAS</td></tr>
|
||||
<tr><td>tCAH_DRAM</td> <td>10ns</td> <td>column address hold time after CAS</td></tr>
|
||||
<tr><td>tCAS_DRAM</td> <td>20ns</td> <td>CAS pulse width / access time</td></tr>
|
||||
<tr><td>tRP_DRAM</td> <td>40ns</td> <td>RAS precharge time</td></tr>
|
||||
<tr><td>tCP_DRAM</td> <td>10ns</td> <td>CAS precharge time</td></tr>
|
||||
<tr><td>tRC_DRAM</td> <td>120ns</td> <td>minimum RAS cycle time</td></tr>
|
||||
<tr><td>tACC_ROM</td> <td>70ns</td> <td>ROM access time</td></tr>
|
||||
<tr><td>tOE_ROM</td> <td>40ns</td> <td>ROM OE access time</td></tr>
|
||||
<tr><td>tPD_573</td> <td>20ns</td> <td>74AHCT573 propagation delay after LE or D</td></tr>
|
||||
<tr><td>tSU_573</td> <td>5ns</td> <td>74AHCT573 setup time before LE</td></tr>
|
||||
<tr><td>tH_573</td> <td>2ns</td> <td>74AHCT573 hold time after LE</td></tr>
|
||||
</table>
|
||||
|
||||
|
||||
<h2>Timing Diagrams</h2><p>
|
||||
Below I am presenting some timing diagrams showing the relevant signals for various interesting bus cycle cases. <br/>
|
||||
We are beginning with the timing of the accelerated processor bus, or the front-side bus (FSB), and proceeding on to the timing of the master port on the Mac SE bus, or the I/O Bus (IOB). <br/>
|
||||
The timing diagrams are scaled for a 25 MHz FSB clock frequency and the standard 7.8336 MHz Mac SE bus.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t0">0. Generic MC68000 bus cycle detection</h3>
|
||||
<script type="WaveDrom">{signal: [
|
||||
{name: 'FCLK', wave: 'p.....', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2..x.', phase: 0.25, period: 2},
|
||||
{name: 'R/W', wave: 'x..1....x...', phase: 0.25, period: 1},
|
||||
{name: '/AS', wave: '1...x0........x1....x2.', phase:-0.25, period: 0.5},
|
||||
{name: '/DS (RD)', wave: '1...x0........x1....x..', phase:-0.25, period: 0.5},
|
||||
{name: '/DS (WR)', wave: '1.......x0....x1....x..', phase:-0.25, period: 0.5},
|
||||
{name: '/AS', wave: '1...x0........x1....x..', phase:-0.25, period: 0.5},
|
||||
{name: '/ASrf', wave: '1...x.....0.......1...x', phase:-0.25, period: 0.5},
|
||||
{name: 'BACT', wave: '0...x.1...........0.x.2', phase:-0.25, period: 0.5},
|
||||
]}
|
||||
</script><br/><p>
|
||||
For starters, it is instructive to look at a generic MC68000 bus cycle. <br/>
|
||||
There are some details of the MC68000 bus cycle that complicate the synchronization of a state machine to the bus cycle. <br/>
|
||||
Primarily, /AS falls after a rising edge of the clock but rises after a falling edge. <br/>
|
||||
Since the worst-case clock-to-output delay of MC68000 is equal to half of one clock cycle, <br/>
|
||||
attempting to detect bus activity by registering /AS strictly on the rising or falling edge
|
||||
would result in entrance into a metastable state. <br/>
|
||||
Therefore we introduce the "bus active" BACTV signal. BACT is the conjunction of the address strobe presently and as registered on the previous falling edge of the FSB clock. <br/>
|
||||
The key useful feature of the BACT signal is that it is always valid at the rising edge of FCLK.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t1">1. FSB functionality - /DTACK and Ready</h3>
|
||||
<script type="WaveDrom">{signal: [
|
||||
{name: 'FCLK', wave: 'p.....', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2..x.', phase: 0.25, period: 2},
|
||||
{name: 'R/W', wave: 'x..1....x...', phase: 0.25, period: 1},
|
||||
{name: '/AS', wave: '1...x0........x1....x2.', phase:-0.25, period: 0.5},
|
||||
{name: '/DTACK', wave: '1.......0...........1..', phase:-0.25, period: 0.5},
|
||||
{name: 'BACT', wave: '0...x.1...........0.x.2', phase:-0.25, period: 0.5},
|
||||
{name: 'Ready', wave: 'x12.x.', phase:-0.20, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
Given BACT, the FSB controller asserts either /DTACK or /VPA when BACT is true and removes both /DTACK and /VPA when BACT is false. <br/>
|
||||
Because the Warp-SE is a variable-wait-state system, we also must introduce the ready signals which are input to the FSB controller. <br/>
|
||||
In the Warp-SE, three functional units control the data flow on the FSB. These are the DRAM controller, the IOB slave port, and the sound rate limiter. <br/>
|
||||
Therefore there are three ready signals, Ready0, Ready1, and Ready2. The three Ready signals are functionally equivalent and interchangeable. <br/>
|
||||
Each ready signal is produced by one of the three functional units. The Ready signals must be valid at the rising edge of each clock where BACT is asserted. <br/>
|
||||
For the FSB controller to assert /DTACK or /VPA, each of the ready signls must be active on at least one clock of the given CACT cycle. <br/>
|
||||
Because all of the Ready signals are sampled by the FSB controller during each BACT cycle, functional units must gate their Ready outputs with their own select signals. <br/>
|
||||
/DTACK is a registered output that changes strictly following the rising edge of FCLK. <br/>
|
||||
Note that MC68000's "/AS inactive-to-/DTACK inactive" parameter of two clock cycles minus 5 nanoseconds is met here. /DTACK is negated approximately 1.5 clock cycles after /AS rises.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t2">2. FSB functionality - Units not immediately ready</h3>
|
||||
<script type="WaveDrom">{signal: [
|
||||
{name: 'FCLK', wave: 'p.......', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2....x.', phase: 0.25, period: 2},
|
||||
{name: 'R/W', wave: 'x..1........x...', phase: 0.25, period: 1},
|
||||
{name: '/AS', wave: '1...x0................x1....x2.', phase:-0.25, period: 0.5},
|
||||
{name: '/DTACK', wave: '1...............0...........1..', phase:-0.25, period: 0.5},
|
||||
{name: 'BACT', wave: '0...x.1...................0.x.2', phase:-0.25, period: 0.5},
|
||||
{name: 'Ready0', wave: 'x10...x.', phase:-0.20, period: 2},
|
||||
{name: 'Ready1', wave: 'x0.10.x.', phase:-0.20, period: 2},
|
||||
{name: 'Ready2', wave: 'x010..x.', phase:-0.20, period: 2},
|
||||
{name: 'Ready', wave: 'x0.12.x.', phase:-0.20, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
As discussed, the Ready signals do not each need to be active all at once. The FSB controller "remembers" that each Ready signal has been asserted. <br/>
|
||||
This is represented by the Ready signal. Once all three individual Ready signals have been asserted, Ready becomes true and /DTACK or /VPA is asserted. <br/>
|
||||
Ready is cleared along with /DTACK and /VPA once BACT is false.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t3">3. FSB functionality - /VPA</h3>
|
||||
<script type="WaveDrom">{signal: [
|
||||
{name: 'FCLK', wave: 'p....|...', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2...|.x.', phase: 0.25, period: 2, data: '$FFFFXX'},
|
||||
{name: 'R/W', wave: 'x..1.......|..x...', phase: 0.25, period: 1},
|
||||
{name: '/AS', wave: '1...x0...............|....x1....x2.', phase:-0.25, period: 0.5},
|
||||
{name: '/VPA', wave: '1...............0....|....x.1......', phase:-0.25, period: 0.5},
|
||||
{name: 'BACT', wave: '0...x.1..............|........0.x.2', phase:-0.25, period: 0.5},
|
||||
{name: 'Ready', wave: '1........', phase:-0.20, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
When the address is in the range $FFFFXX, the FSB controller asserts /VPA instead of /DTACK. <br/>
|
||||
The "/AS inactive-to-/VPA inactive" parameter of MC68000 is more stringent than, the "/AS inactive-to-/DTACK inactive" parameter, <br/>
|
||||
so /VPA is additionally gated by /AS, whereas /DTACK is not.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t4">4. Back-to-Back ROM Access</h3>
|
||||
<script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2..x2..x.', phase: 0.25, period: 2, data:['400000-4FFFFF','400000-4FFFFF']},
|
||||
{name: 'ROMCS', wave: '1..x.0.........x.....0.........x.1.....', phase:-0.25, period: 0.5},
|
||||
{name: 'RW', wave: 'x..2....x..2....x...', phase: 0.25, period: 1},
|
||||
{name: 'AS', wave: '1...x0........x1....x0........x1....x2.', phase:-0.25, period: 0.5},
|
||||
{name: 'DS (RD)', wave: '1...x0........x1....x0........x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1...x.0.......x.1...x.0.......x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '1.......x0....x1........x0....x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......x.0...x.1.......x.0...x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'Ready', wave: '1.........', phase:-0.25, period: 2},
|
||||
{name: '/DTACK', wave: '1.0..10..1', phase:-0.20, period: 2},
|
||||
{name: 'D (RD)', wave: 'z..x..2.z..x..2.z...', phase:-0.30},
|
||||
{name: 'D (WR)', wave: 'z......x.2......z......x.2......z.......', phase:-0.30, period:0.5},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram introduces the simplest memory access type, a read from or write to ROM memory. ROM control is completely asynchronous.<br/>
|
||||
</p><p>
|
||||
The ROM /CS signal is implemented as a decode of the address bus.
|
||||
Similarly, the /OE signal is an asynchronous function of LDS, UDS, and /WE. <br/>
|
||||
The /OE signal is shared by the RAM and ROM, so therefore it is critical that the ROMCS signal not be tied low,
|
||||
otherwise bus contention will occur during RAM reads. <br/>
|
||||
The Ready signals are always high during ROM access so all ROM accesses complete with the fastest 4-cycle timing.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t5">5. Back-to-Back RAM Access</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2..x2..x.', phase: 0.25, period: 2, data:['000000-3FFFFF','000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x..1....x..1....x...', phase: 0.25, period: 1, data:['read or write','read or write']},
|
||||
{name: 'AS', wave: '1...x0........x1....x0........x1....x2.', phase:-0.25, period: 0.5},
|
||||
{name: 'DS (RD)', wave: '1...x0........x1....x0........x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1...x.0.......x.1...x.0.......x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '1.......x0....x1........x0....x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......x.0...x.1.......x.0...x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'Ready', wave: 'x10.x10.x.', phase:-0.20, period: 2},
|
||||
{name: 'DTACK', wave: '1.0..10..1', phase:-0.20, period: 2},
|
||||
{name: 'D (RD)', wave: 'z....x2.z....x2.z...', phase:-0.30},
|
||||
{name: 'D (WR)', wave: 'z......x.2......z......x.2......z......', phase:-0.30, period:0.5},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,0,5,6,7,0,5,6,7,0]},
|
||||
{name: 'RAS', wave: '1...x.0.......x.1...x.0.......x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.1.0.', phase:-0.20, period: 2},
|
||||
{name: 'RA', wave: 'x...x2..x2......x....2..x2......x......', phase:-0.20, period:0.5, data:['row','col','row','col']},
|
||||
{name: 'CAS', wave: '1..0.1.0.1', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram introduces the DRAM access timing.
|
||||
</p><p>
|
||||
At 25 MHz for a 4-clock read cycle, there are only 2.5 clock cycles (100 ns) between
|
||||
the MC68k's assertion of /AS and when it latches data from the bus. <br/>
|
||||
Subtracting the 25ns /AS tCO and 5ns data in tSU, that leaves only 70ns during which to initiate and complete a DRAM access,
|
||||
not accounting for any RAS control delay in the CPLD. <br/>
|
||||
Therefore to minimize RAM access latency, RAS is implemented not as a registered output
|
||||
but as an asynchronous decode of the address, /AS, and the internal RAS enable signal. <br/>
|
||||
With 10ns delay in the CPLD, 25 MHz operation with 60ns DRAM is just possible.
|
||||
</p><p>
|
||||
Similarly, the RA multiplexed DRAM address bus is an asynchronous multiplexer controlled by the RASEL signal <br/>
|
||||
which outputs row addresses to the DRAM array when RASEL is low and column addresses when RASEL is high. <br/>
|
||||
The /CAS signal is a function of RASEL, which changes after FCLK rises. If RASEL is high at the next falling edge, /CAS is asserted.
|
||||
Otherwise if RASEL is low, /CAS is deasserted at the next falling edge.
|
||||
</p><p>
|
||||
"RS" is the RAM state. The RS state changes after the rising edge of the clock
|
||||
and can take on values 0-7. <br/>
|
||||
In RS0, the RAM is considered to be idle. <br/>
|
||||
At the rising edge of the clock in RS0 a RAM cycle begins if, if /AS is asserted,
|
||||
a RAM address is present, and a RAM cycle has not already occurred for this /AS cycle. <br/>
|
||||
In this case, we know that /RAS has been active for at least 10 nanoseconds, so RASEL is brogught high. <br/>
|
||||
This switches the RA bus from row to column addresses and RS0 transitions to RS5. <br/>
|
||||
At the falling edge in the middle of RS5, /CAS is brought low. RS5 always transitions to RS6. <br/>
|
||||
At the end of RS6, RASEL is brought low again, switching the RA multiplexers back to row addresses
|
||||
in preparation for the next DRAM access cycle. RS6 always transitions to RS7. <br/>
|
||||
RS7 is the state in which a RAM access or refresh is concluded. At the falling edge in the middle of RS7, /CAS is brought high. <br/>
|
||||
RS7 transitions to RS2 if a refresh request is pending, otherwise RS7 transitions to RS0. <br/>
|
||||
The states RS1 and RS2-RS4 will be discussed in association with the subsequent refresh cycle diagrams. <br/>
|
||||
RAMReady is used along with a RAM select signal to generate the Ready0 signal input to the FSB controller.
|
||||
RAMReady is high if and only if the RAM state is in RS0.<br/>
|
||||
</p><p>
|
||||
Also notice how, during write cycles,
|
||||
it is undefined whether the cycle is conducted as an "early write" or an "OE-controlled write" cycle. <br/>
|
||||
/OE is held high at all times during write cycles,
|
||||
but /LWE and /UWE are asynchronous functions of MC68k's /LDS and /UDS signals. <br/>
|
||||
It is undefined during a write cycle whether /LWE and /UWE will go low before or after /CAS falls. <br/>
|
||||
Since /OE is held high during write cycles, the order of the /WE signals and /CAS is of no consequence.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t6">6. Long-running RAM Access</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2......x.', phase: 0.25, period: 2, data:['000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x..1............x...', phase: 0.25, period: 1, data:['read or write','read or write']},
|
||||
{name: 'AS', wave: '1...x0........................x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'Ready', wave: '0.....1...', phase:-0.20, period: 2},
|
||||
{name: 'DTACK', wave: '1.....0..1', phase:-0.20, period: 2},
|
||||
{name: 'D (RD)', wave: 'z....x2..z..........', phase:-0.30},
|
||||
{name: 'D (WR)', wave: 'z..x2...........z...', phase: 0.00},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,0,5,6,7,0,0,0,0,0]},
|
||||
{name: 'RAS', wave: '1...x.0.......................x.1......', phase:-0.25, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.....', phase:-0.20, period: 2},
|
||||
{name: 'RA', wave: 'x...x2..x2......2...............x........', phase:-0.20, period:0.5, data:['row','col','row']},
|
||||
{name: 'CAS', wave: '1..0.1....', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram shows the timing for a long-running RAM access,
|
||||
in which the RAM read or write completes sooner than MC68k removes /AS. <br/>
|
||||
</p><p>
|
||||
There are cases in which a DRAM access completes in time for termination of a 4-clock bus cycle,
|
||||
but the bus cycle is lengthened because not all of the Ready signals to the FSB controller have gone high. <br/>
|
||||
If RS0 is returned to after a DRAM access but /AS remains asserted,
|
||||
then the DRAM must not enter RS5-7 and thus not initiate any additional /CAS cycles. <br/>
|
||||
Notice how /CAS goes high in the middle of RS7 but /RAS stays low until the end of the /AS cycle.
|
||||
Using EDO DRAM allows the data bus output to be maintained while /RAS is low. <br/>
|
||||
However, if FPM DRAM is used or if a refresh cycle occurs before /AS rises,
|
||||
then maintenance of read data on the data bus falls to the bus capacitance and the bus hold resistors. <br/>
|
||||
Therefore it is best not to prolong DRAM read cycles, even when using EDO DRAM, so that there is no possibility of
|
||||
an intervening DRAM refresh cycle causing the data outputs to tristate. <br/>
|
||||
Fortunately, although DRAM write cycles shadowed to main sound and video memory need to be extended
|
||||
when the posted write FIFO is full, there is no need to extend DRAM read cycles. <br/>
|
||||
Therefore we do not attempt to extend the /CAS pulse to fix this problem until /AS rises since the /CAS pulse
|
||||
could be interrupted by a refresh cycle anyway. <br/>
|
||||
To fix this problem, we could extend the /CAS pulse until /AS is high and have the
|
||||
DRAM controller conform to theDRAM "hidden refresh" protocol but it is not necessary.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t7">7. Refresh During Idle</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '1............', phase:-0.75},
|
||||
{name: 'RS', wave: '2222222', phase:-0.2, period: 2, data:[0,0,2,3,4,7,0,0,0]},
|
||||
{name: 'RefReq', wave: '01..0..', phase:-0.2, period: 2},
|
||||
{name: 'RASEN', wave: '1.0...1', phase:-0.2, period: 2},
|
||||
{name: 'RRAS', wave: '1.....0...1...', phase:-0.20},
|
||||
{name: 'RAS', wave: '1.....0...1...', phase:-0.40},
|
||||
{name: 'CAS', wave: '1..0.1.', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram shows the timing of a refresh occurring after the bus and DRAM are and have been idle for at least one clock cycle.
|
||||
</p><p>
|
||||
RAM states RS1, RS2, RS3, RS4, and RS7 are used for refresh. <br/>
|
||||
RS1 is used when initiating a refresh during a long-running /RAS cycle and will be discussed subsequently. <br/>
|
||||
RS2-RS4 implement the main refresh behavior. <br/>
|
||||
When a refresh request is pending at the rising edge ending RS0 or RS7 while /RAS is inactive,
|
||||
RASEN is brought low and RS2 is entered. <br/>
|
||||
With RASEN low, /AS activity does not cause a /RAS pulse and the DRAM controller uses the registered /RRAS signal
|
||||
to initiate refresh cycles. <br/>
|
||||
At the falling edge in the middle of RS2, /CAS is activated. Then at the rising edge concluding RS2, /RAS is activated
|
||||
and RS2 transitions to RS3. <br/>
|
||||
RREQ is also cleared in RS2 since entrance into RS11 constitutes acceptance of a pending refresh request. <br/>
|
||||
In RS3, /RAS and /CAS remain active, and RS3 transitions to RS4.
|
||||
RS3 and RS4 serve to implement the requisite /RAS pulse width for a refresh. <br/>
|
||||
At the falling edge in the middle of RS4, /CAS is deactivated. Then at the rising edge concluding RS4, /RAS is deactivated
|
||||
and RS4 transitions to RS7. <br/>
|
||||
In RS7, /RAS and /CAS remain inactive. RS7 serves to implement the requisite RAS precharge time between DRAM cycles.<br/>
|
||||
RASEN is brought high again after the rising edge concluding RS7 and RS7 transitions to RS0 and the DRAM is considered idle again.<br/>
|
||||
</p><p>
|
||||
Also notice how a RASEN can only be disabled if /RAS is high or if a DRAM cycle is complete, otherwise
|
||||
there may be a tRAS timing violation. This constrains the timing of a refresh.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t8">8. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p...', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.x1....x.......', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222', phase:-0.20, period: 2, data:[6,7,2,3,4]},
|
||||
{name: 'RefReq', wave: '21..', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0.', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1..0', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.x.1.......0..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.10', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the timing of a refresh occurring immediately after a RAM access cycle.
|
||||
</p><p>
|
||||
Recall that a refresh cannot begin while a DRAM access is ongoing, or else an improperly-short /RAS pulse could occur.<br/>
|
||||
Imagine, however, that MC68k performs many back-to-back DRAM accesses.
|
||||
In this case, there would never be an RS0 in which a /RAS pulse has not already begun. <br/>
|
||||
Therefore the DRAM controller must be able to begin a refresh during RS7,
|
||||
immediately after a RAM access is completed but before MC68k brings /AS low again. <br/>
|
||||
The timing for this case starts out slightly differently but ends the same as the refresh during idle.
|
||||
Therefore the timing is only shown through S4.<br/>
|
||||
The purpose of this diagram is mainly to demonstrate that adequate /RAS and /CAS precharge time exists
|
||||
after the previous DRAM access is terminated before /RAS is pulsed for refresh.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t9">9. Refresh Immediately Following DRAM Access - Bus Transaction Terminated While Refresh In-Progress</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p.......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.................x1....x......', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '22222222', phase:-0.20, period: 2, data:[6,7,1,2,3,4,7,0,0,0,0]},
|
||||
{name: 'RefReq', wave: '21...0..', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0....1', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1...0.1.', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.......1.......0.......1...x..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.1.0.1.', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs during a long-running DRAM access
|
||||
and the /AS cycle terminates before the refresh ends.
|
||||
</p><p>
|
||||
It is possible for a DRAM access cycle to be extended for a long time, during which the DRAM may be deprived of refresh. <br/>
|
||||
Therefore we must provide for the case where a DRAM access completes and a refresh begins but before /AS ever goes high. <br/>
|
||||
In this case, the rising edge of RASEN causes /RAS to go inactive, as opposed to the rising edge of /AS. <br/>
|
||||
Therefore, the /RAS precharge pulse width in this case is much shorter than
|
||||
a refresh occurring during idle or immediately following a DRAM access. <br/>
|
||||
In order to satisfy the tRP precharge time and tRC cycle timing parameters,
|
||||
an additional state, RS1, must be inserted in which /RAS and /CAS are both held in precharge.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t10">10. Refresh Immediately Following DRAM Access - Bus Transaction Terminated After Refresh Completes</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.............................x1....x...', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[6,7,1,2,3,4,7,0,0,0]},
|
||||
{name: 'RefReq', wave: '21.0......', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0......1', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1...0.1...', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.......1.......0.......1...........x...', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.1.0.1...', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs during a long-running DRAM access
|
||||
and the /AS cycle does not terminate before the refresh ends.
|
||||
</p><p>
|
||||
This case is similar to the previous but there is a key difference.
|
||||
/AS does not rise until after the refresh cycle completes. <br/>
|
||||
Therefore if RASEN were brought high upon exit from RS7 into RS0, there may be an improperly-short /RAS pulse. <br/>
|
||||
Consequently RASEN enablement is held off the first rising edge during which BACT is low.
|
||||
</p>
|
||||
|
||||
<h3 id="t11">11. Refresh in the "Middle" of DRAM Access</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p.......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0...............................', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '22222222', phase:-0.20, period: 2, data:[6,7,0,0,0,1,2,3]},
|
||||
{name: 'RefReq', wave: '0...1...', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1....0..', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1......0', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0...................1.......0...', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.1....0', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs in the "middle" of a long-running DRAM access. <br/>
|
||||
The remainder of the timing is given by diagrams 9 or 10.
|
||||
</p>
|
||||
|
||||
<h3 id="t12">12. Concurrent DRAM Access and Refresh Requests</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p..........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2.......x.', phase: 0.25, period: 2, data:['000000-4FFFFF']},
|
||||
{name: '/AS', wave: '1..x0............................x1........', phase:-0.75, period: 0.5},
|
||||
{name: 'DTACK', wave: '1......0..1', phase:-0.30, period: 2},
|
||||
{name: 'DS (RD)', wave: '1..x0............................x1.......', phase:-0.75, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1...x.0..........................x.1.....', phase:-0.75, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '1......x0........................x1.......', phase:-0.75, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......................0........x.1......', phase:-0.75, period: 0.5},
|
||||
{name: 'RS', wave: '22222222222', phase:-0.20, period: 2, data:[0,2,3,4,6,7,0,5,6,7,0]},
|
||||
{name: 'Ready0', wave: 'x0....10.x.', phase:-0.20, period: 2},
|
||||
{name: 'RefReq', wave: '1..0.......', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '10....1....', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1...0...1.............', phase:-0.20},
|
||||
{name: '/RAS', wave: '1.......0.......1.......0.........x.1......', phase:-0.45, period: 0.5},
|
||||
{name: '/CAS', wave: '1.0.1...0.1', phase: 0.70, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the timing of a refresh starting concurrently with the beginning of a RAM access cycle.
|
||||
</p><p>
|
||||
Here we see the timing of refresh being entered concurrently with the start of a RAM access.
|
||||
In this case, there is a little bit of a race condition. <br/>
|
||||
RASEN and /AS both fall following the rising edge of FCLK. /AS causes /RAS activation asynchronously,
|
||||
but RASEN gates this from occurring. <br/>
|
||||
Therefore the internal RASEN feedback in the CPLD must occur sooner than /AS transitions,
|
||||
otherwise an erroneous /RAS pulse will be generated. <br/>
|
||||
Fortunately the CPLDs intended to be used (ispMACH4000, XC9500XL) are some 10 years newer than MC68HC000,
|
||||
so their speed advantage mitigates the problem. <br/>
|
||||
The negation of Ready0 causes /DTACK generation and termination of the bus cycle
|
||||
to be delayed until completion of the refresh. <br/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Before showing the timing for the I/O bus slave port on the FSB,
|
||||
it's instructive to understand the timing of the I/O bus master controller.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t13">13. I/O Bus E State, VMA, "ETACK"</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'C16M', wave: 'p...........................', period: 1},
|
||||
{name: 'C8M', wave: '0101010101010101010101010101', phase:-0.25, period: 1},
|
||||
{name: 'E', wave: '10.....1...0..', phase: 0.90, period: 2},
|
||||
{name: 'Er', wave: '10.....1...0..', phase:-0.40, period: 2},
|
||||
{name: 'Er2', wave: '1..0...........1.......0....', phase:-0.10, period: 1},
|
||||
{name: 'ES', wave: '2222222222222222222222222222', period: 1, data:[18,19,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,0,1,2,3,4,5]},
|
||||
{name: 'IOACT', wave: '2........12.................', period: 1},
|
||||
{name: '/VPA', wave: 'x................0..x...................................', period: 0.5},
|
||||
{name: '/VMA', wave: '1.........0............1....', period: 1},
|
||||
{name: 'ETACK', wave: '0..................10.......', period: 1},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the I/O bus VMA and "ETACK" timing.
|
||||
<p>
|
||||
Although most I/O bus accesses are terminated by /DTACK,
|
||||
accesses to the VIA and interrupt acknowledge areas of memory are terminated by /VPA. <br/>
|
||||
With MC68k having granted the bus to the accelerator,
|
||||
it will no longer generate the /VMA chip select signal in respose to /VPA. <br/>
|
||||
Therefore for /VMA, we must provide the /VMA signal timing. <br/>
|
||||
In order to do this, an internal counter, the ES or "E state" is synchronized to MC68k's E clock cycle. <br/>
|
||||
Synchronization of a state machine running from the C16M clock to the E clock cycle
|
||||
is complicated by clock skew between the C16M, C8M, and E clocks. <br/>
|
||||
The E clock changes following the falling edge of C8M, so E is registered at the falling edge of C8M as Er.
|
||||
Then Er is registered at the rising edge of C16M as Er2. <br/>
|
||||
Er and Er2 both have adequate setup and hold time to be used at the rising edge of C16M.
|
||||
Er and Er2 are then used to synchronize the ES counter to the E clock phase. <br/>
|
||||
</p><p>
|
||||
In ES7, if the IO bus is active, as signified by IOACT, and /VPA has been asserted, the IO bus controller asserts /VMA
|
||||
in preparation for the E clock high pulse. <br/>
|
||||
Then in ES17, if /VMA is low, i.e. a /VPA cycle is ongoing, ETACK is asserted. <br/>
|
||||
ETACK is analogous to /DTACK and signals the I/O controller to
|
||||
terminate the /AS cycle in synchronization with the E clock going low.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t14">14. I/O Bus Access (Even Phase)</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'IOS', wave:'22222222222222222222|222222', period: 1,data:[0,0,0,0,0,0,1,2,3,4,5,6,7,0,1,2,3,4,5,5,5,6,7,0,0,0,0]},
|
||||
{name: 'C16M', wave:'p...................|......', period: 1},
|
||||
{name: 'C8M', wave:'10101010101010101010|101010', phase:-0.25, period: 1},
|
||||
{name: 'C8Mr', wave:'01010101010101010101|010101', phase:-0.10, period: 1},
|
||||
{name: 'AS', wave:'1.....0....1..0.....|.1....', phase:-0.60, period: 1},
|
||||
{name: 'DTACK', wave:'x.........0x......1x|2x....', phase:-0.10, period: 1},
|
||||
{name: 'ETACK', wave:'x.........1x......1x|2x....', phase:-0.10, period: 1},
|
||||
{name: 'BERR', wave:'x.........1x......1x|1x....', phase:-0.10, period: 1},
|
||||
{name: 'IOACT', wave:'0.....1....0..1.....|.0....', phase:-0.10, period: 1},
|
||||
{name: 'IOREQ', wave:'0....1x......1x.....|...0..', phase:-0.60, period: 1},
|
||||
{name: 'ADout0LE',wave:'1.....0.....1.0.....|..1...', phase:-0.10, period: 1},
|
||||
{name: '&&ADLEEN',wave:'1....x0.....1.0.....|..1...', phase:-0.10, period: 1},
|
||||
{name: 'DinLE', wave:'0........1.0.....1..|.0....', phase:-0.60, period: 1},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the timing of two I/O bus cycles, first a 4-clock cycle terminated by /DTACK,
|
||||
then a longer cycle terminated by either /DTACK or /VPA.
|
||||
</p><p>
|
||||
The I/O bus master controller initiates a cycle when the IOREQ signal originating from the FSB domain (discussed subsequently)
|
||||
is high and there is no ongoing bus cycle. <br/>
|
||||
The IOS state counter tracks the progress through a M68k bus master transaction. <br/>
|
||||
In IOS0, the bus is considered to be idle. In IOS0 if C8M is low and IOREQ is high,
|
||||
then IOACT goes high and IOS1 is entered. Entrance into IOS1 is delayed by one clock if C8M is high.<br/>
|
||||
IOS counts from 1-5 and then pauses in IOS5, only transitioning to IOS6 when C8M is high
|
||||
and one of /DTACK, ETACK, /BERR, or /RESET are active. <br/>
|
||||
For /DTACK, /BERR, and /RESET termination, the termination signals must be low not only at the rising edge concluding IOS5
|
||||
but also at the previous falling edge and rising edge, otherwise cycle termination is held off. <br/>
|
||||
In order to best match M68k's timing and meet the timing constraints of BBU, /AS is output on the falling edge of C16M. <br/>
|
||||
/AS is active following the falling edge in the middle of IOS1 until the falling edge in the middle of IOS6. <br/>
|
||||
The timing for /LDS and /UDS is a similarly straightforward function of IOS, R/W, and the FSB /LDS and /UDS signals. <br/>
|
||||
As mentioned before, IOS5 is maintained until C8M is high and one of the cycle termination signals is active.
|
||||
Once this occurs, IOS6 is entered and IOACT goes low. <br/>
|
||||
IOS6 transitions to IOS7 and then around to IOS0, which is maintained until another I/O request comes in. <br/>
|
||||
It is the responsibility of the FSB controller to deassert IOREQ after IOACTV goes high
|
||||
in order to prevent the bus transaction from occurring twice. <br/>
|
||||
However, IOREQ can be maintained high through IOACT going high, low, then high again
|
||||
in order to ensure two back-to-back bus transactions occur.
|
||||
</p><p>
|
||||
Notice the ADout0LE and DinLE signals. <br/>
|
||||
ADoutLE is the latch enable for address and write data going from the FSB to the IOB. <br/>
|
||||
DinLE is the latch enable for read data going from the IOB data to the FSB. <br/>
|
||||
ADoutLE is high only during IOS0 and is low during IOS1-7.
|
||||
Therefore address and write data are latched for the entirety of the bus cycle. <br/>
|
||||
ADoutLE0 is additionally gated by the ADLEEN signal from the FSB clock domain.
|
||||
DinLE is high following the falling edges in the middle of IOS4 and IOS5, thus the input latch captures the read data. <br/>
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t15">15. I/O Bus Access (Odd Phase)</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'IOS', wave:'2222222222222',period: 1,data:[0,0,0,0,0,0,1,2,3,4,5,6,7,0,1,2,3,4,5,5,5,6,7,0,0,0,0]},
|
||||
{name: 'C16M', wave:'p............', period: 1},
|
||||
{name: 'C8M', wave:'1010101010101', phase:-0.25, period: 1},
|
||||
{name: 'C8Mr', wave:'0101010101010', phase:-0.10, period: 1},
|
||||
{name: 'AS', wave:'1.....0....1.', phase:-0.60, period: 1},
|
||||
{name: 'DTACK', wave:'x.........0x.', phase:-0.10, period: 1},
|
||||
{name: 'ETACK', wave:'x.........1x.', phase:-0.10, period: 1},
|
||||
{name: 'BERR', wave:'x.........1x.', phase:-0.10, period: 1},
|
||||
{name: 'IOACT', wave:'0....1.....0.', phase:-0.10, period: 1},
|
||||
{name: 'IOREQ', wave:'0...1x.......', phase:-0.60, period: 1},
|
||||
{name: 'ADout0LE',wave:'1....0.......', phase:-0.10, period: 1},
|
||||
{name: '&&ADLEEN',wave:'1...x0.......', phase:-0.10, period: 1},
|
||||
{name: 'DinLE', wave:'0........1.0.', phase:-0.60, period: 1},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the timing of an I/O bus cycle beginning with C8M high.
|
||||
</p><p>
|
||||
This case is basically the same as the start of the previous, just the IOREQ comes in one C16M clock earlier. <br/>
|
||||
Therefore although IOACTV goes high and ADoutLE goes low immediately following IOREQ detection,
|
||||
entrance into IOS1 is delayed by one clock.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t16">16. IOREQ Synchronization from FSB to IOB</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'C16M', wave:'p..', period: 4},
|
||||
{name: 'IOREQ - FSB (best case)', wave:'0..1....................', period: 0.5, phase: 0.00},
|
||||
{name: 'IOREQ - IOB (best case)', wave:'0...1...................', period: 0.5, phase:-0.15},
|
||||
{name: 'IOREQ - FSB (worst case)', wave:'0...1...................', period: 0.5, phase: 0.15},
|
||||
{name: 'IOREQ - IOB (worst case)', wave:'0...x0......1...........', period: 0.5, phase:-0.15}
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the synchronization of IOREQ from the FSB clock domain to the I/O clock domain.
|
||||
</p><p>
|
||||
Because the C16M clock speed is low and because latency between the FSB and IOB is critical,
|
||||
a single-state synchronizer triggered on the C16M falling edge is used. <br/>
|
||||
On XC9500XL and ispMACH4000, the metastability recovery time tMET is only a few nanoseconds
|
||||
for MTBF in the trillions of years. <br/>
|
||||
With 30ns between the falling and rising edges of C16M, a single-stage synchronizer is adequate. <br/>
|
||||
Given this arrangement, in IOS0, the delay between the FSB sending IOREQ low and the IOB responding with IOACT high <br/>
|
||||
is 1.5 C16M clock cycles plus one tSU and two tCO, or approximately 110 nanoseconds.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t17">17. Three Consecutive Posted Writes to I/O Bus</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p..........|.....', period: 2},
|
||||
{name: 'A', wave: 'x2..x2..x2.|...x.', phase:0.25, period: 2, data:['3F, 50-5F, 90-BF, D0-FF','3F, 50-5F, 90-BF, D0-FF','3F, 50-5F, 90-BF, D0-FF']},
|
||||
{name: 'R/W', wave: 'x..0....x..0....x..0...|......x...', phase:0.25, period: 1},
|
||||
{name: '/AS', wave: '1...x0........x1....x0........x1....x0.......|............x1....x..', phase:-0.25, period: 0.5},
|
||||
{name: '/DS (WR)',wave: '1.......x0....x1........x0....x1........x0...|............x1....x..', phase:-0.25, period: 0.5},
|
||||
{name: 'BACT', wave: '201..01..01|....0', phase:-0.20, period: 2},
|
||||
{name: '/DTACK', wave: '2.0..10..1.|.0..1', phase:-0.3, period: 2},
|
||||
{name: 'D (WR)', wave: 'z...x2..z...x2..z...x2.|......z...', phase:0.00},
|
||||
{name: 'Ready1', wave: 'x1..x10.x0.|1..x.', phase:-0.2, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows two consecutive posted writes to the I/O bus.
|
||||
</p><p>
|
||||
In order to enhance video performance, the ability to "post" up to two consecutive writes to the I/O bus is desirable.
|
||||
Three such posted writes are shown here.<br/>
|
||||
During IOB space write cycles, the Ready1 signal (input to the FSB controller)
|
||||
is high when the FSB-to-IOB interface can accept a posted write. <br/>
|
||||
Because three writes were performed consecutively here before the first had the opportunity to complete,
|
||||
Ready1 goes low because the FSB-to-IOB FIFO is full and completion of the third write is delayed until the FIFO is not full.
|
||||
</p>
|
||||
|
||||
<h3 id="t18">18. Two Consecutive Posted Writes to Video/Sound Memory with FIFO Empty</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', period: 2},
|
||||
{name: 'A', wave: 'x2..x2..x.', phase:0.25, period: 2, data:['3FXXXX','3FXXXX']},
|
||||
{name: 'R/W', wave: 'x..0....x..0....x...', phase:0.25, period: 1},
|
||||
{name: '/AS', wave: '1...x0........x1....x0........x1....x..', phase:-0.25, period: 0.5},
|
||||
{name: '/DS (WR)',wave: '1.......x0....x1........x0....x1....x..', phase:-0.25, period: 0.5},
|
||||
{name: 'BACT', wave: '201..01..0', phase:-0.20, period: 2},
|
||||
{name: '/DTACK', wave: '2.0..10..1', phase:-0.3, period: 2},
|
||||
{name: 'D (WR)', wave: 'z...x2..z...x2..z...', phase:0.00},
|
||||
{name: 'Ready1', wave: 'x1..x10.x.', phase:-0.2, period: 2},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,0,5,6,7,0,5,6,7,0]},
|
||||
{name: 'Ready0', wave: 'x10.x10.x.', phase:-0.20, period: 2},
|
||||
{name: '/RAS', wave: '1...x.0.......x.1...x.0.......x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.1.0.', phase:-0.20, period: 2},
|
||||
{name: 'RA', wave: 'x...x2..x2......x....2..x2......x........', phase:-0.20, period:0.5, data:['row','col','row','col']},
|
||||
{name: '/CAS', wave: '1..0.1.0.1', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows two consecutive posted writes to video/sound RAM.
|
||||
</p><p>
|
||||
When writing to video/sound RAM, the data written must be written to the I/O bus
|
||||
as well as shadowed in the accelerator's onboard RAM. <br/>
|
||||
Therefore a DRAM write cycle occurs concurrently with an I/O bus write. <br/>
|
||||
Here we have the case where the I/O bus FIFO starts out empty and then accepts two writes in four clock cycles each. <br/>
|
||||
In this case, the acceptance of the posted write by the I/O bus slave port and the DRAM write occur simultaneously. <br/>
|
||||
Of course, were the posted write FIFO full or the RAM in refresh, either unit could
|
||||
delay completion of the /AS cycle via their respective Ready signals.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t19">19. Read from I/O Bus</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p..|.....', period: 2},
|
||||
{name: 'A', wave: 'x2.|...x.', phase:0.25, period: 2, data:['50-5F, 90-BF, D0-FF','50-5F, 90-BF, D0-FF']},
|
||||
{name: 'RW', wave: 'x..1...|......x...', phase:0.25, period: 1},
|
||||
{name: 'AS', wave: '1...x0.......|............x1....x..', phase:-0.25, period: 0.5},
|
||||
{name: 'BACT', wave: '101|....0', phase:-0.20, period: 2},
|
||||
{name: 'DTACK', wave: 'x1.|.0..1', phase:-0.3, period: 2},
|
||||
{name: 'D (RD)', wave: 'z.x....|.2....z...', phase:0.00},
|
||||
{name: 'Ready1', wave: 'x0.|1....', phase:-0.2, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows a read from the I/O bus.
|
||||
</p><p>
|
||||
From the perspective of the FSB controller, the case where data is read from the I/O bus is fairly simple. <br/>
|
||||
The IOB slave port holds Ready1 low until the I/O bus transaction is completed.
|
||||
</p>
|
||||
|
||||
|
||||
<h3>20. I/O Bus Slave Port - Single Read/Write</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p...|..|..', period: 2},
|
||||
{name: 'IOAS', wave: '010.|..|..', period: 2, phase:-0.3},
|
||||
{name: 'PS', wave: '2222|22|22', period: 2, data:[0,0,2,2,2,1,1,0], phase:-0.3},
|
||||
{name: 'IOACT', wave: '0...|1.|0.', phase:-0.3, period: 2},
|
||||
{name: 'IOREQ', wave: '0.1.|.0|..', phase:-0.3, period: 2},
|
||||
{name: 'ALEEN0', wave: '1..0|.1|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW0', wave: 'x.1.|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU0', wave: 'x..2|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
{name: 'Ready1 (RD)', wave: 'x..2|..|..', phase:-0.3, period: 2},
|
||||
{name: 'Ready1 (WR)', wave: 'x..2|..|..', phase:-0.3, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the behavior of the I/O bus slave port controller under a single read/write request.
|
||||
</p><p>
|
||||
Here we are just showing the signals relevant to the I/O bus slave port controller rather than all of the M68k FSB signals. <br/>
|
||||
IOAS is a decode of the address, the FSB's /AS, and the IODone signal and represents when an I/O bus cycle request
|
||||
has been submitted but not yet accepted by the I/O bus slave port controller. <br/>
|
||||
If the posted write FIFO is empty then the IOB slave port controller can submit
|
||||
a new access request to the master controller. <br/>
|
||||
In this case the posted write FIFO is empty and IOA is active,
|
||||
so the IOB slave controller enters PS2 and asserts IOREQ. <br/>
|
||||
In addition, at this time, IORW0 is latched from the FSB's R/W line.
|
||||
This tells the IOB master controller whether the current request a read or write.
|
||||
At the end of the first PS2 state, ALEEN0 is lowered in order to latch the address and write data into the IOB interface latches.
|
||||
IOLU0[1:0] is also latched from the FSB /LDS and /UDS signals. <br/>
|
||||
Similar to IORW0, IOLU0 encodes which of the two bytes of the data bus are to be accessed by the IOB master controller. <br/>
|
||||
</p><p>
|
||||
ADLEEN0 merits some additional explanation. <br/>
|
||||
Since the IOB slave controller supports a 4-clock posted write, following the first PS2 state of a posted write,
|
||||
M68k will remove /AS and terminate the cycle. <br/>
|
||||
Because of synchronization overhead between the FSB and IOB clock domains, the IOB master controller may not latch the address and write data into the latches between the FSB and IOB before the cycle terminates. <br/>
|
||||
Therefore the ALE0 output is additionally gated by the FSB clock domain signal ADLEEN0.
|
||||
ADLEEN0 stays low until a receipt of the IOB request is confirmed by the IOB master controller. <br/>
|
||||
</p><p>
|
||||
Following the first PS2 state, the IOB slave controller waits in PS2 until the IOB master controller signals IOACT,
|
||||
indicating that it has received the IOB request. <br/>
|
||||
Once IOACT is received high then the IOB slave controller removes IOREQ and ADLEEN0 and enters PS1.
|
||||
</p><p>
|
||||
In PS1, the IO bus controller waits for IOACT low, indicating that the cycle has completed, and then returns to PS0.
|
||||
Additionally, once IOACT is low, if IORW0 indicates a read was performed, IORDRDY is brought high for one cycle.
|
||||
</p>
|
||||
|
||||
|
||||
<h3>22. I/O Bus Slave Port - Two Writes, FIFO never full</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p..|..|....|..|..', period: 2},
|
||||
{name: 'AS&IO', wave: '01.|..|.01.|..|..', period: 2, phase:-0.3},
|
||||
{name: 'PS', wave: '222|22|2222|22|22', period: 2, data:[0,2,2,2,1,1,0,2,2,2,1,1,0], phase:-0.3},
|
||||
{name: 'IOACT', wave: '0..|1.|0...|1.|0.', phase:-0.3, period: 2},
|
||||
{name: 'IOREQ', wave: '01.|.0|..1.|.0|..', phase:-0.3, period: 2},
|
||||
{name: 'ALE0', wave: '1.0|.1|...0|.1|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW0', wave: 'x0.|..|..0.|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU0', wave: 'x.2|..|...2|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
]}
|
||||
</script>
|
||||
|
||||
<h3>23. I/O Bus Slave Port - Two Writes, FIFO filled (0)</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p..|..|.....|..|..', period: 2},
|
||||
{name: 'AS&IO', wave: '01.|..|01...|..|..', period: 2, phase:-0.3},
|
||||
{name: 'IORDY', wave: '101|..|.0..1|..|..', phase:-0.3, period: 2},
|
||||
{name: 'PS', wave: '222|22|22222|22|22', period: 2, data:[0,2,2,2,1,1,0,2,2,2,2,1,1,0], phase:-0.3},
|
||||
{name: 'IOACT', wave: '0..|1.|0....|1.|0.', phase:-0.3, period: 2},
|
||||
{name: 'IOREQ', wave: '01.|.0|.1...|.0|..', phase:-0.3, period: 2},
|
||||
{name: 'ALE1', wave: '1..|..|.0..1|..|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW1', wave: 'x..|..|.0...|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU1', wave: 'x..|..|..2..|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
{name: 'ALE0', wave: '1.0|.1|...0.|.1|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW0', wave: 'x0.|..|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU0', wave: 'x.2|..|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
]}
|
||||
</script>
|
||||
|
||||
<h3>24. I/O Bus Slave Port - Two Writes, FIFO filled (1)</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p..|....|.....|..|..', period: 2},
|
||||
{name: 'AS&IO', wave: '01.|.01.|.....|..|..', period: 2, phase:-0.3},
|
||||
{name: 'IORDY', wave: '101|..0.|....1|..|..', phase:-0.3, period: 2},
|
||||
{name: 'PS', wave: '222|2222|22222|22|22', period: 2, data:[0,2,2,2,1,1,1,1,0,2,2,2,2,1,1,0], phase:-0.3},
|
||||
{name: 'IOACT', wave: '0..|1...|0....|1.|0.', phase:-0.3, period: 2},
|
||||
{name: 'IOREQ', wave: '01.|.01.|.....|.0|..', phase:-0.3, period: 2},
|
||||
{name: 'ALE1', wave: '1..|..0.|....1|..|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW1', wave: 'x..|..0.|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU1', wave: 'x..|...2|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
{name: 'ALE0', wave: '1.0|.1..|...0.|.1|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW0', wave: 'x0.|....|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU0', wave: 'x.2|....|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
]}
|
||||
</script>
|
||||
|
||||
<h3>25. I/O Bus Slave Port - Two Writes, FIFO filled (2)</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p..|....|.....|..|..', period: 2},
|
||||
{name: 'AS&IO', wave: '01.|01..|.....|..|..', period: 2, phase:-0.3},
|
||||
{name: 'IORDY', wave: '101|.0..|....1|..|..', phase:-0.3, period: 2},
|
||||
{name: 'PS', wave: '222|2222|22222|22|22', period: 2, data:[0,2,2,2,1,1,1,1,0,2,2,2,2,1,1,0], phase:-0.3},
|
||||
{name: 'IOACT', wave: '0..|1...|0....|1.|0.', phase:-0.3, period: 2},
|
||||
{name: 'IOREQ', wave: '01.|....|.....|.0|..', phase:-0.3, period: 2},
|
||||
{name: 'ALE1', wave: '1..|.0..|....1|..|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW1', wave: 'x..|.0..|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU1', wave: 'x..|..2.|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
{name: 'ALE0', wave: '1.0|.1..|...0.|.1|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW0', wave: 'x0.|....|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU0', wave: 'x.2|....|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
]}
|
||||
</script>
|
||||
|
||||
<h3>26. I/O Bus Slave Port - Two Writes, FIFO filled (3)</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p....|..|.....|..|..', period: 2},
|
||||
{name: 'AS&IO', wave: '0101.|0.|.....|..|..', period: 2, phase:-0.3},
|
||||
{name: 'IORDY', wave: '1.10.|..|....1|..|..', phase:-0.3, period: 2},
|
||||
{name: 'PS', wave: '22222|22|22222|22|22', period: 2, data:[0,2,2,2,2,2,1,1,0,2,2,2,2,1,1,0], phase:-0.3},
|
||||
{name: 'IOACT', wave: '0....|1.|0....|1.|0.', phase:-0.3, period: 2},
|
||||
{name: 'IOREQ', wave: '01...|..|.....|.0|..', phase:-0.3, period: 2},
|
||||
{name: 'ALE1', wave: '1..0.|..|....1|..|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW1', wave: 'x..0.|..|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU1', wave: 'x...2|..|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
{name: 'ALE0', wave: '1.0..|.1|...0.|.1|..', phase:-0.3, period: 2},
|
||||
{name: 'IORW0', wave: 'x0...|..|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
|
||||
{name: 'IOLU0', wave: 'x.2..|..|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
|
||||
]}
|
||||
</script>
|
||||
|
||||
|
||||
</body>
|
||||
|
||||
</html>
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 9 10
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
Text HLabel 4750 3550 2 50 Output ~ 0
|
||||
TCK
|
||||
Text HLabel 4750 3750 2 50 Output ~ 0
|
||||
TDI
|
||||
Text HLabel 4750 3450 2 50 Output ~ 0
|
||||
TMS
|
||||
Text HLabel 4750 3650 2 50 Input ~ 0
|
||||
TDO
|
||||
$Comp
|
||||
L Connector_Generic:Conn_02x07_Odd_Even J2
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||||
U 1 1 61B2217D
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||||
P 4450 3650
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||||
F 0 "J2" H 4500 4050 50 0000 C CNN
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||||
F 1 "JTAG" H 4500 3250 50 0000 C CNN
|
||||
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|
||||
F 3 "~" H 4450 3650 50 0001 C CNN
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||||
1 4450 3650
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||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
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||||
L power:GND #PWR0127
|
||||
U 1 1 61B22961
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||||
P 4250 3950
|
||||
F 0 "#PWR0127" H 4250 3700 50 0001 C CNN
|
||||
F 1 "GND" H 4255 3777 50 0000 C CNN
|
||||
F 2 "" H 4250 3950 50 0001 C CNN
|
||||
F 3 "" H 4250 3950 50 0001 C CNN
|
||||
1 4250 3950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4250 3350 4250 3450
|
||||
Connection ~ 4250 3950
|
||||
Connection ~ 4250 3450
|
||||
Wire Wire Line
|
||||
4250 3450 4250 3550
|
||||
Connection ~ 4250 3550
|
||||
Wire Wire Line
|
||||
4250 3550 4250 3650
|
||||
Connection ~ 4250 3650
|
||||
Wire Wire Line
|
||||
4250 3650 4250 3750
|
||||
Connection ~ 4250 3750
|
||||
Wire Wire Line
|
||||
4250 3750 4250 3850
|
||||
Connection ~ 4250 3850
|
||||
Wire Wire Line
|
||||
4250 3850 4250 3950
|
||||
$Comp
|
||||
L power:+3V3 #PWR0128
|
||||
U 1 1 61B2334F
|
||||
P 4750 3350
|
||||
F 0 "#PWR0128" H 4750 3200 50 0001 C CNN
|
||||
F 1 "+3V3" H 4750 3500 50 0000 C CNN
|
||||
F 2 "" H 4750 3350 50 0001 C CNN
|
||||
F 3 "" H 4750 3350 50 0001 C CNN
|
||||
1 4750 3350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 4750 3850
|
||||
NoConn ~ 4750 3950
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 5 10
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L CPU_NXP_68000:MC68000FN U14
|
||||
U 1 1 6187DB31
|
||||
P 2300 3600
|
||||
F 0 "U14" H 2300 5650 50 0000 C CNN
|
||||
F 1 "MC68HC000FN20" H 2300 5550 50 0000 C CNN
|
||||
F 2 "stdpads:PLCC-68" H 1550 5850 50 0001 C CNN
|
||||
F 3 "http://www.nxp.com/files/32bit/doc/ref_manual/MC68000UM.pdf" H 2300 3600 50 0001 C CNN
|
||||
1 2300 3600
|
||||
1 0 0 -1
|
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$EndComp
|
||||
Text HLabel 1300 3300 0 50 Input ~ 0
|
||||
~VPA~
|
||||
Text HLabel 1300 4300 0 50 Input ~ 0
|
||||
~DTACK~
|
||||
Text HLabel 3300 5800 2 50 Output ~ 0
|
||||
R~W~
|
||||
Text HLabel 3300 5700 2 50 Output ~ 0
|
||||
~LDS~
|
||||
Text HLabel 3300 5600 2 50 Output ~ 0
|
||||
~UDS~
|
||||
Text HLabel 3300 5500 2 50 Output ~ 0
|
||||
~AS~
|
||||
Text HLabel 1300 5000 0 50 BiDi ~ 0
|
||||
~RESET~
|
||||
Text HLabel 1300 1700 0 50 Input ~ 0
|
||||
~IPL~0
|
||||
Text HLabel 1300 1800 0 50 Input ~ 0
|
||||
~IPL~1
|
||||
Text HLabel 1300 1900 0 50 Input ~ 0
|
||||
~IPL~2
|
||||
Text HLabel 1300 4100 0 50 Input ~ 0
|
||||
~BERR~
|
||||
Text HLabel 1300 1400 0 50 Input ~ 0
|
||||
CLK
|
||||
Text Label 3300 3800 0 50 ~ 0
|
||||
D0
|
||||
Text Label 3300 3900 0 50 ~ 0
|
||||
D1
|
||||
Text Label 3300 4000 0 50 ~ 0
|
||||
D2
|
||||
Text Label 3300 4100 0 50 ~ 0
|
||||
D3
|
||||
Text Label 3300 4200 0 50 ~ 0
|
||||
D4
|
||||
Text Label 3300 4300 0 50 ~ 0
|
||||
D5
|
||||
Text Label 3300 4400 0 50 ~ 0
|
||||
D6
|
||||
Text Label 3300 4500 0 50 ~ 0
|
||||
D7
|
||||
Text Label 3300 4600 0 50 ~ 0
|
||||
D8
|
||||
Text Label 3300 4700 0 50 ~ 0
|
||||
D9
|
||||
Text Label 3300 4800 0 50 ~ 0
|
||||
D10
|
||||
Text Label 3300 4900 0 50 ~ 0
|
||||
D11
|
||||
Text Label 3300 5000 0 50 ~ 0
|
||||
D12
|
||||
Text Label 3300 5100 0 50 ~ 0
|
||||
D13
|
||||
Text Label 3300 5200 0 50 ~ 0
|
||||
D14
|
||||
Text Label 3300 5300 0 50 ~ 0
|
||||
D15
|
||||
Wire Wire Line
|
||||
3300 5300 3500 5300
|
||||
Wire Wire Line
|
||||
3300 5200 3500 5200
|
||||
Wire Wire Line
|
||||
3300 5100 3500 5100
|
||||
Wire Wire Line
|
||||
3300 5000 3500 5000
|
||||
Wire Wire Line
|
||||
3300 4900 3500 4900
|
||||
Wire Wire Line
|
||||
3300 4800 3500 4800
|
||||
Wire Wire Line
|
||||
3300 4700 3500 4700
|
||||
Wire Wire Line
|
||||
3300 4600 3500 4600
|
||||
Wire Wire Line
|
||||
3300 4500 3500 4500
|
||||
Wire Wire Line
|
||||
3300 4400 3500 4400
|
||||
Wire Wire Line
|
||||
3300 4300 3500 4300
|
||||
Wire Wire Line
|
||||
3300 4200 3500 4200
|
||||
Wire Wire Line
|
||||
3300 4100 3500 4100
|
||||
Wire Wire Line
|
||||
3300 4000 3500 4000
|
||||
Wire Wire Line
|
||||
3300 3900 3500 3900
|
||||
Wire Wire Line
|
||||
3300 3800 3500 3800
|
||||
Entry Wire Line
|
||||
3500 5300 3600 5400
|
||||
Entry Wire Line
|
||||
3500 5200 3600 5300
|
||||
Entry Wire Line
|
||||
3500 5100 3600 5200
|
||||
Entry Wire Line
|
||||
3500 5000 3600 5100
|
||||
Entry Wire Line
|
||||
3500 4900 3600 5000
|
||||
Entry Wire Line
|
||||
3500 4800 3600 4900
|
||||
Entry Wire Line
|
||||
3500 4700 3600 4800
|
||||
Entry Wire Line
|
||||
3500 4600 3600 4700
|
||||
Entry Wire Line
|
||||
3500 4500 3600 4600
|
||||
Entry Wire Line
|
||||
3500 4400 3600 4500
|
||||
Entry Wire Line
|
||||
3500 4300 3600 4400
|
||||
Entry Wire Line
|
||||
3500 4200 3600 4300
|
||||
Entry Wire Line
|
||||
3500 4100 3600 4200
|
||||
Entry Wire Line
|
||||
3500 4000 3600 4100
|
||||
Entry Wire Line
|
||||
3500 3900 3600 4000
|
||||
Entry Wire Line
|
||||
3500 3800 3600 3900
|
||||
Text HLabel 3650 3900 2 50 BiDi ~ 0
|
||||
D[15..0]
|
||||
Wire Wire Line
|
||||
3300 2900 3500 2900
|
||||
Wire Wire Line
|
||||
3300 2800 3500 2800
|
||||
Wire Wire Line
|
||||
3300 2700 3500 2700
|
||||
Wire Wire Line
|
||||
3300 2600 3500 2600
|
||||
Wire Wire Line
|
||||
3300 2500 3500 2500
|
||||
Wire Wire Line
|
||||
3300 2400 3500 2400
|
||||
Wire Wire Line
|
||||
3300 2300 3500 2300
|
||||
Wire Wire Line
|
||||
3300 2200 3500 2200
|
||||
Wire Wire Line
|
||||
3300 2100 3500 2100
|
||||
Wire Wire Line
|
||||
3300 2000 3500 2000
|
||||
Wire Wire Line
|
||||
3300 1900 3500 1900
|
||||
Wire Wire Line
|
||||
3300 1800 3500 1800
|
||||
Wire Wire Line
|
||||
3300 1700 3500 1700
|
||||
Wire Wire Line
|
||||
3300 1600 3500 1600
|
||||
Wire Wire Line
|
||||
3300 1500 3500 1500
|
||||
Wire Wire Line
|
||||
3300 1400 3500 1400
|
||||
Entry Wire Line
|
||||
3500 2900 3600 3000
|
||||
Entry Wire Line
|
||||
3500 2800 3600 2900
|
||||
Entry Wire Line
|
||||
3500 2700 3600 2800
|
||||
Entry Wire Line
|
||||
3500 2600 3600 2700
|
||||
Entry Wire Line
|
||||
3500 2500 3600 2600
|
||||
Entry Wire Line
|
||||
3500 2400 3600 2500
|
||||
Entry Wire Line
|
||||
3500 2300 3600 2400
|
||||
Entry Wire Line
|
||||
3500 2200 3600 2300
|
||||
Entry Wire Line
|
||||
3500 2100 3600 2200
|
||||
Entry Wire Line
|
||||
3500 2000 3600 2100
|
||||
Entry Wire Line
|
||||
3500 1900 3600 2000
|
||||
Entry Wire Line
|
||||
3500 1800 3600 1900
|
||||
Entry Wire Line
|
||||
3500 1700 3600 1800
|
||||
Entry Wire Line
|
||||
3500 1600 3600 1700
|
||||
Entry Wire Line
|
||||
3500 1500 3600 1600
|
||||
Entry Wire Line
|
||||
3500 1400 3600 1500
|
||||
Wire Wire Line
|
||||
3300 3600 3500 3600
|
||||
Wire Wire Line
|
||||
3300 3500 3500 3500
|
||||
Wire Wire Line
|
||||
3300 3400 3500 3400
|
||||
Wire Wire Line
|
||||
3300 3300 3500 3300
|
||||
Wire Wire Line
|
||||
3300 3200 3500 3200
|
||||
Wire Wire Line
|
||||
3300 3100 3500 3100
|
||||
Wire Wire Line
|
||||
3300 3000 3500 3000
|
||||
Entry Wire Line
|
||||
3500 3600 3600 3700
|
||||
Entry Wire Line
|
||||
3500 3500 3600 3600
|
||||
Entry Wire Line
|
||||
3500 3400 3600 3500
|
||||
Entry Wire Line
|
||||
3500 3300 3600 3400
|
||||
Entry Wire Line
|
||||
3500 3200 3600 3300
|
||||
Entry Wire Line
|
||||
3500 3100 3600 3200
|
||||
Entry Wire Line
|
||||
3500 3000 3600 3100
|
||||
Text Label 3300 1400 0 50 ~ 0
|
||||
A1
|
||||
Text Label 3300 1500 0 50 ~ 0
|
||||
A2
|
||||
Text Label 3300 1600 0 50 ~ 0
|
||||
A3
|
||||
Text Label 3300 1700 0 50 ~ 0
|
||||
A4
|
||||
Text Label 3300 1800 0 50 ~ 0
|
||||
A5
|
||||
Text Label 3300 1900 0 50 ~ 0
|
||||
A6
|
||||
Text Label 3300 2000 0 50 ~ 0
|
||||
A7
|
||||
Text Label 3300 2100 0 50 ~ 0
|
||||
A8
|
||||
Text Label 3300 2200 0 50 ~ 0
|
||||
A9
|
||||
Text Label 3300 2300 0 50 ~ 0
|
||||
A10
|
||||
Text Label 3300 2400 0 50 ~ 0
|
||||
A11
|
||||
Text Label 3300 2500 0 50 ~ 0
|
||||
A12
|
||||
Text Label 3300 2600 0 50 ~ 0
|
||||
A13
|
||||
Text Label 3300 2700 0 50 ~ 0
|
||||
A14
|
||||
Text Label 3300 2800 0 50 ~ 0
|
||||
A15
|
||||
Text Label 3300 2900 0 50 ~ 0
|
||||
A16
|
||||
Text Label 3300 3000 0 50 ~ 0
|
||||
A17
|
||||
Text Label 3300 3100 0 50 ~ 0
|
||||
A18
|
||||
Text Label 3300 3200 0 50 ~ 0
|
||||
A19
|
||||
Text Label 3300 3300 0 50 ~ 0
|
||||
A20
|
||||
Text Label 3300 3400 0 50 ~ 0
|
||||
A21
|
||||
Text Label 3300 3500 0 50 ~ 0
|
||||
A22
|
||||
Text Label 3300 3600 0 50 ~ 0
|
||||
A23
|
||||
Text HLabel 3650 1500 2 50 Output ~ 0
|
||||
A[23..1]
|
||||
NoConn ~ 1300 2600
|
||||
NoConn ~ 1300 2700
|
||||
NoConn ~ 1300 2800
|
||||
NoConn ~ 1300 2200
|
||||
Wire Wire Line
|
||||
1300 2300 1200 2300
|
||||
Wire Wire Line
|
||||
1200 2300 1200 2100
|
||||
Wire Wire Line
|
||||
1200 2100 1300 2100
|
||||
$Comp
|
||||
L power:+5V #PWR0101
|
||||
U 1 1 60E9BDD6
|
||||
P 1200 2100
|
||||
F 0 "#PWR0101" H 1200 1950 50 0001 C CNN
|
||||
F 1 "+5V" H 1200 2250 50 0000 C CNN
|
||||
F 2 "" H 1200 2100 50 0001 C CNN
|
||||
F 3 "" H 1200 2100 50 0001 C CNN
|
||||
1 1200 2100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 1200 2100
|
||||
$Comp
|
||||
L power:+5V #PWR0102
|
||||
U 1 1 60E9C1DC
|
||||
P 2200 1000
|
||||
F 0 "#PWR0102" H 2200 850 50 0001 C CNN
|
||||
F 1 "+5V" H 2200 1150 50 0000 C CNN
|
||||
F 2 "" H 2200 1000 50 0001 C CNN
|
||||
F 3 "" H 2200 1000 50 0001 C CNN
|
||||
1 2200 1000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2200 1000 2400 1000
|
||||
Connection ~ 2200 1000
|
||||
$Comp
|
||||
L power:GND #PWR0103
|
||||
U 1 1 60EA198C
|
||||
P 2500 6200
|
||||
F 0 "#PWR0103" H 2500 5950 50 0001 C CNN
|
||||
F 1 "GND" H 2500 6050 50 0000 C CNN
|
||||
F 2 "" H 2500 6200 50 0001 C CNN
|
||||
F 3 "" H 2500 6200 50 0001 C CNN
|
||||
1 2500 6200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2500 6200 2400 6200
|
||||
Connection ~ 2500 6200
|
||||
Connection ~ 2200 6200
|
||||
Wire Wire Line
|
||||
2200 6200 2100 6200
|
||||
Connection ~ 2400 6200
|
||||
Wire Wire Line
|
||||
2400 6200 2200 6200
|
||||
Wire Bus Line
|
||||
3650 1500 3600 1500
|
||||
Wire Bus Line
|
||||
3650 3900 3600 3900
|
||||
$Comp
|
||||
L power:+5V #PWR?
|
||||
U 1 1 6161AC98
|
||||
P 1300 7200
|
||||
AR Path="/6161AC98" Ref="#PWR?" Part="1"
|
||||
AR Path="/60D70CB4/6161AC98" Ref="#PWR?" Part="1"
|
||||
AR Path="/5F72F108/6161AC98" Ref="#PWR0104" Part="1"
|
||||
F 0 "#PWR0104" H 1300 7050 50 0001 C CNN
|
||||
F 1 "+5V" H 1300 7350 50 0000 C CNN
|
||||
F 2 "" H 1300 7200 50 0001 C CNN
|
||||
F 3 "" H 1300 7200 50 0001 C CNN
|
||||
1 1300 7200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1300 7200 1700 7200
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 6161ACA0
|
||||
P 1700 7300
|
||||
AR Path="/6161ACA0" Ref="C?" Part="1"
|
||||
AR Path="/60D70CB4/6161ACA0" Ref="C?" Part="1"
|
||||
AR Path="/5F72F108/6161ACA0" Ref="C2" Part="1"
|
||||
F 0 "C2" H 1750 7350 50 0000 L CNN
|
||||
F 1 "10u" H 1750 7250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 1700 7300 50 0001 C CNN
|
||||
F 3 "~" H 1700 7300 50 0001 C CNN
|
||||
1 1700 7300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 1300 7200
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 6161ACA7
|
||||
P 1300 7300
|
||||
AR Path="/6161ACA7" Ref="C?" Part="1"
|
||||
AR Path="/60D70CB4/6161ACA7" Ref="C?" Part="1"
|
||||
AR Path="/5F72F108/6161ACA7" Ref="C1" Part="1"
|
||||
F 0 "C1" H 1350 7350 50 0000 L CNN
|
||||
F 1 "10u" H 1350 7250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 1300 7300 50 0001 C CNN
|
||||
F 3 "~" H 1300 7300 50 0001 C CNN
|
||||
1 1300 7300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1300 7400 1700 7400
|
||||
Wire Wire Line
|
||||
1300 4800 1300 5000
|
||||
NoConn ~ 1300 3100
|
||||
NoConn ~ 1300 3200
|
||||
$Comp
|
||||
L power:GND #PWR0126
|
||||
U 1 1 61B1134E
|
||||
P 1700 7400
|
||||
F 0 "#PWR0126" H 1700 7150 50 0001 C CNN
|
||||
F 1 "GND" H 1700 7250 50 0000 C CNN
|
||||
F 2 "" H 1700 7400 50 0001 C CNN
|
||||
F 3 "" H 1700 7400 50 0001 C CNN
|
||||
1 1700 7400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 1700 7400
|
||||
Wire Bus Line
|
||||
3600 3900 3600 5400
|
||||
Wire Bus Line
|
||||
3600 1500 3600 3700
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,688 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 4 10
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L GW_Connector:MacSEPDS J?
|
||||
U 1 1 5F6DD05A
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||||
P 1350 3950
|
||||
AR Path="/5F6DD05A" Ref="J?" Part="1"
|
||||
AR Path="/5F6DA71D/5F6DD05A" Ref="J1" Part="1"
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||||
F 0 "J1" H 1232 5867 50 0000 C CNN
|
||||
F 1 "MacSEPDS" H 1232 5776 50 0000 C CNN
|
||||
F 2 "stdpads:DIN41612_R_3x32_Male_Vertical_THT" H 1350 5750 50 0001 C CNN
|
||||
F 3 "" H 1350 5750 50 0001 C CNN
|
||||
1 1350 3950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L GW_Connector:MacSEPDS J?
|
||||
U 3 1 5F6E0CCF
|
||||
P 3900 3950
|
||||
AR Path="/5F6E0CCF" Ref="J?" Part="3"
|
||||
AR Path="/5F6DA71D/5F6E0CCF" Ref="J1" Part="3"
|
||||
F 0 "J1" H 3782 5867 50 0000 C CNN
|
||||
F 1 "MacSEPDS" H 3782 5776 50 0000 C CNN
|
||||
F 2 "stdpads:DIN41612_R_3x32_Male_Vertical_THT" H 3900 5750 50 0001 C CNN
|
||||
F 3 "" H 3900 5750 50 0001 C CNN
|
||||
3 3900 3950
|
||||
1 0 0 -1
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||||
$EndComp
|
||||
NoConn ~ 1500 2300
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||||
NoConn ~ 1500 2400
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||||
NoConn ~ 1500 2500
|
||||
NoConn ~ 2750 4950
|
||||
NoConn ~ 2750 4850
|
||||
NoConn ~ 2750 4750
|
||||
NoConn ~ 2750 4650
|
||||
NoConn ~ 2750 4550
|
||||
NoConn ~ 2750 4450
|
||||
$Comp
|
||||
L power:+5V #PWR0143
|
||||
U 1 1 5F6E26CC
|
||||
P 2850 3950
|
||||
F 0 "#PWR0143" H 2850 3800 50 0001 C CNN
|
||||
F 1 "+5V" H 2850 4100 50 0000 C CNN
|
||||
F 2 "" H 2850 3950 50 0001 C CNN
|
||||
F 3 "" H 2850 3950 50 0001 C CNN
|
||||
1 2850 3950
|
||||
1 0 0 -1
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||||
$EndComp
|
||||
Wire Wire Line
|
||||
2850 3950 2750 3950
|
||||
NoConn ~ 2750 3350
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||||
NoConn ~ 2750 3250
|
||||
$Comp
|
||||
L power:GND #PWR0144
|
||||
U 1 1 5F6E368E
|
||||
P 2850 2350
|
||||
F 0 "#PWR0144" H 2850 2100 50 0001 C CNN
|
||||
F 1 "GND" H 2850 2200 50 0000 C CNN
|
||||
F 2 "" H 2850 2350 50 0001 C CNN
|
||||
F 3 "" H 2850 2350 50 0001 C CNN
|
||||
1 2850 2350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2850 2350 2750 2350
|
||||
$Comp
|
||||
L power:GND #PWR0146
|
||||
U 1 1 5F6E485F
|
||||
P 4500 5200
|
||||
F 0 "#PWR0146" H 4500 4950 50 0001 C CNN
|
||||
F 1 "GND" H 4500 5050 50 0000 C CNN
|
||||
F 2 "" H 4500 5200 50 0001 C CNN
|
||||
F 3 "" H 4500 5200 50 0001 C CNN
|
||||
1 4500 5200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 4050 5300
|
||||
$Comp
|
||||
L power:GND #PWR0147
|
||||
U 1 1 5F6E565A
|
||||
P 1900 5200
|
||||
F 0 "#PWR0147" H 1900 4950 50 0001 C CNN
|
||||
F 1 "GND" H 1900 5050 50 0000 C CNN
|
||||
F 2 "" H 1900 5200 50 0001 C CNN
|
||||
F 3 "" H 1900 5200 50 0001 C CNN
|
||||
1 1900 5200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1900 5200 1500 5200
|
||||
$Comp
|
||||
L power:+5V #PWR0148
|
||||
U 1 1 5F6E63E7
|
||||
P 4450 3500
|
||||
F 0 "#PWR0148" H 4450 3350 50 0001 C CNN
|
||||
F 1 "+5V" H 4450 3650 50 0000 C CNN
|
||||
F 2 "" H 4450 3500 50 0001 C CNN
|
||||
F 3 "" H 4450 3500 50 0001 C CNN
|
||||
1 4450 3500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0149
|
||||
U 1 1 5F6E6FCB
|
||||
P 3150 5150
|
||||
F 0 "#PWR0149" H 3150 4900 50 0001 C CNN
|
||||
F 1 "GND" H 3150 5000 50 0000 C CNN
|
||||
F 2 "" H 3150 5150 50 0001 C CNN
|
||||
F 3 "" H 3150 5150 50 0001 C CNN
|
||||
1 3150 5150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3150 5150 2750 5150
|
||||
NoConn ~ 2750 3450
|
||||
Text HLabel 4050 2300 2 50 Output ~ 0
|
||||
~VPA~
|
||||
Text HLabel 4050 2400 2 50 BiDi ~ 0
|
||||
~VMA~
|
||||
Text HLabel 4050 2800 2 50 Output ~ 0
|
||||
~DTACK~
|
||||
Text HLabel 4050 2900 2 50 BiDi ~ 0
|
||||
R~W~
|
||||
Text HLabel 4050 3000 2 50 BiDi ~ 0
|
||||
~LDS~
|
||||
Text HLabel 4050 3100 2 50 BiDi ~ 0
|
||||
~UDS~
|
||||
Text HLabel 4050 3200 2 50 BiDi ~ 0
|
||||
~AS~
|
||||
Text HLabel 4050 3400 2 50 BiDi ~ 0
|
||||
~RESET~
|
||||
Text HLabel 2750 4050 2 50 Output ~ 0
|
||||
~IPL~0
|
||||
Text HLabel 2750 4150 2 50 Output ~ 0
|
||||
~IPL~1
|
||||
Text HLabel 2750 4250 2 50 Output ~ 0
|
||||
~IPL~2
|
||||
Text HLabel 2750 4350 2 50 Output ~ 0
|
||||
~BERR~
|
||||
Text HLabel 1500 4900 2 50 Output ~ 0
|
||||
E
|
||||
Text HLabel 1500 5000 2 50 Output ~ 0
|
||||
C8M
|
||||
Text HLabel 1500 5100 2 50 Output ~ 0
|
||||
C16M
|
||||
Text Label 4050 3600 0 50 ~ 0
|
||||
D0
|
||||
Text Label 4050 3700 0 50 ~ 0
|
||||
D1
|
||||
Text Label 4050 3800 0 50 ~ 0
|
||||
D2
|
||||
Text Label 4050 3900 0 50 ~ 0
|
||||
D3
|
||||
Text Label 4050 4000 0 50 ~ 0
|
||||
D4
|
||||
Text Label 4050 4100 0 50 ~ 0
|
||||
D5
|
||||
Text Label 4050 4200 0 50 ~ 0
|
||||
D6
|
||||
Text Label 4050 4300 0 50 ~ 0
|
||||
D7
|
||||
Text Label 4050 4400 0 50 ~ 0
|
||||
D8
|
||||
Text Label 4050 4500 0 50 ~ 0
|
||||
D9
|
||||
Text Label 4050 4600 0 50 ~ 0
|
||||
D10
|
||||
Text Label 4050 4700 0 50 ~ 0
|
||||
D11
|
||||
Text Label 4050 4800 0 50 ~ 0
|
||||
D12
|
||||
Text Label 4050 4900 0 50 ~ 0
|
||||
D13
|
||||
Text Label 4050 5000 0 50 ~ 0
|
||||
D14
|
||||
Text Label 4050 5100 0 50 ~ 0
|
||||
D15
|
||||
Wire Wire Line
|
||||
4050 5100 4250 5100
|
||||
Wire Wire Line
|
||||
4050 5000 4250 5000
|
||||
Wire Wire Line
|
||||
4050 4900 4250 4900
|
||||
Wire Wire Line
|
||||
4050 4800 4250 4800
|
||||
Wire Wire Line
|
||||
4050 4700 4250 4700
|
||||
Wire Wire Line
|
||||
4050 4600 4250 4600
|
||||
Wire Wire Line
|
||||
4050 4500 4250 4500
|
||||
Wire Wire Line
|
||||
4050 4400 4250 4400
|
||||
Wire Wire Line
|
||||
4050 4300 4250 4300
|
||||
Wire Wire Line
|
||||
4050 4200 4250 4200
|
||||
Wire Wire Line
|
||||
4050 4100 4250 4100
|
||||
Wire Wire Line
|
||||
4050 4000 4250 4000
|
||||
Wire Wire Line
|
||||
4050 3900 4250 3900
|
||||
Wire Wire Line
|
||||
4050 3800 4250 3800
|
||||
Wire Wire Line
|
||||
4050 3700 4250 3700
|
||||
Wire Wire Line
|
||||
4050 3600 4250 3600
|
||||
Wire Wire Line
|
||||
1500 4100 1700 4100
|
||||
Wire Wire Line
|
||||
1500 4000 1700 4000
|
||||
Wire Wire Line
|
||||
1500 3900 1700 3900
|
||||
Wire Wire Line
|
||||
1500 3800 1700 3800
|
||||
Wire Wire Line
|
||||
1500 3700 1700 3700
|
||||
Wire Wire Line
|
||||
1500 3600 1700 3600
|
||||
Wire Wire Line
|
||||
1500 3500 1700 3500
|
||||
Wire Wire Line
|
||||
1500 3400 1700 3400
|
||||
Wire Wire Line
|
||||
1500 3300 1700 3300
|
||||
Wire Wire Line
|
||||
1500 3200 1700 3200
|
||||
Wire Wire Line
|
||||
1500 3100 1700 3100
|
||||
Wire Wire Line
|
||||
1500 3000 1700 3000
|
||||
Wire Wire Line
|
||||
1500 2900 1700 2900
|
||||
Wire Wire Line
|
||||
1500 2800 1700 2800
|
||||
Wire Wire Line
|
||||
1500 2700 1700 2700
|
||||
Wire Wire Line
|
||||
1500 2600 1700 2600
|
||||
Entry Wire Line
|
||||
1700 4100 1800 4200
|
||||
Entry Wire Line
|
||||
1700 4000 1800 4100
|
||||
Entry Wire Line
|
||||
1700 3900 1800 4000
|
||||
Entry Wire Line
|
||||
1700 3800 1800 3900
|
||||
Entry Wire Line
|
||||
1700 3700 1800 3800
|
||||
Entry Wire Line
|
||||
1700 3600 1800 3700
|
||||
Entry Wire Line
|
||||
1700 3500 1800 3600
|
||||
Entry Wire Line
|
||||
1700 3400 1800 3500
|
||||
Entry Wire Line
|
||||
1700 3300 1800 3400
|
||||
Entry Wire Line
|
||||
1700 3200 1800 3300
|
||||
Entry Wire Line
|
||||
1700 3100 1800 3200
|
||||
Entry Wire Line
|
||||
1700 3000 1800 3100
|
||||
Entry Wire Line
|
||||
1700 2900 1800 3000
|
||||
Entry Wire Line
|
||||
1700 2800 1800 2900
|
||||
Entry Wire Line
|
||||
1700 2700 1800 2800
|
||||
Entry Wire Line
|
||||
1700 2600 1800 2700
|
||||
Text HLabel 1800 2700 2 50 BiDi ~ 0
|
||||
A[23..1]
|
||||
Wire Wire Line
|
||||
1500 4800 1700 4800
|
||||
Wire Wire Line
|
||||
1500 4700 1700 4700
|
||||
Wire Wire Line
|
||||
1500 4600 1700 4600
|
||||
Wire Wire Line
|
||||
1500 4500 1700 4500
|
||||
Wire Wire Line
|
||||
1500 4400 1700 4400
|
||||
Wire Wire Line
|
||||
1500 4300 1700 4300
|
||||
Wire Wire Line
|
||||
1500 4200 1700 4200
|
||||
Entry Wire Line
|
||||
1700 4800 1800 4900
|
||||
Entry Wire Line
|
||||
1700 4700 1800 4800
|
||||
Entry Wire Line
|
||||
1700 4600 1800 4700
|
||||
Entry Wire Line
|
||||
1700 4500 1800 4600
|
||||
Entry Wire Line
|
||||
1700 4400 1800 4500
|
||||
Entry Wire Line
|
||||
1700 4300 1800 4400
|
||||
Entry Wire Line
|
||||
1700 4200 1800 4300
|
||||
Text Label 1500 2600 0 50 ~ 0
|
||||
A1
|
||||
Text Label 1500 2700 0 50 ~ 0
|
||||
A2
|
||||
Text Label 1500 2800 0 50 ~ 0
|
||||
A3
|
||||
Text Label 1500 2900 0 50 ~ 0
|
||||
A4
|
||||
Text Label 1500 3000 0 50 ~ 0
|
||||
A5
|
||||
Text Label 1500 3100 0 50 ~ 0
|
||||
A6
|
||||
Text Label 1500 3200 0 50 ~ 0
|
||||
A7
|
||||
Text Label 1500 3300 0 50 ~ 0
|
||||
A8
|
||||
Text Label 1500 3400 0 50 ~ 0
|
||||
A9
|
||||
Text Label 1500 3500 0 50 ~ 0
|
||||
A10
|
||||
Text Label 1500 3600 0 50 ~ 0
|
||||
A11
|
||||
Text Label 1500 3700 0 50 ~ 0
|
||||
A12
|
||||
Text Label 1500 3800 0 50 ~ 0
|
||||
A13
|
||||
Text Label 1500 3900 0 50 ~ 0
|
||||
A14
|
||||
Text Label 1500 4000 0 50 ~ 0
|
||||
A15
|
||||
Text Label 1500 4100 0 50 ~ 0
|
||||
A16
|
||||
Text Label 1500 4200 0 50 ~ 0
|
||||
A17
|
||||
Text Label 1500 4300 0 50 ~ 0
|
||||
A18
|
||||
Text Label 1500 4400 0 50 ~ 0
|
||||
A19
|
||||
Text Label 1500 4500 0 50 ~ 0
|
||||
A20
|
||||
Text Label 1500 4600 0 50 ~ 0
|
||||
A21
|
||||
Text Label 1500 4700 0 50 ~ 0
|
||||
A22
|
||||
Text Label 1500 4800 0 50 ~ 0
|
||||
A23
|
||||
$Comp
|
||||
L GW_Connector:MacSEPDS J?
|
||||
U 2 1 5F6DF4C8
|
||||
P 2600 4000
|
||||
AR Path="/5F6DF4C8" Ref="J?" Part="2"
|
||||
AR Path="/5F6DA71D/5F6DF4C8" Ref="J1" Part="2"
|
||||
F 0 "J1" H 2462 5917 50 0000 C CNN
|
||||
F 1 "MacSEPDS" H 2462 5826 50 0000 C CNN
|
||||
F 2 "stdpads:DIN41612_R_3x32_Male_Vertical_THT" H 2600 5800 50 0001 C CNN
|
||||
F 3 "" H 2600 5800 50 0001 C CNN
|
||||
2 2600 4000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
NoConn ~ 2750 5050
|
||||
Connection ~ 2100 6400
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616DE7BE
|
||||
P 2100 6300
|
||||
AR Path="/616DE7BE" Ref="C?" Part="1"
|
||||
AR Path="/5F6DA71D/616DE7BE" Ref="C20" Part="1"
|
||||
F 0 "C20" H 2150 6350 50 0000 L CNN
|
||||
F 1 "10u" H 2150 6250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 2100 6300 50 0001 C CNN
|
||||
F 3 "~" H 2100 6300 50 0001 C CNN
|
||||
1 2100 6300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1700 6400 2100 6400
|
||||
Wire Wire Line
|
||||
1300 6400 1700 6400
|
||||
Connection ~ 1700 6400
|
||||
Wire Wire Line
|
||||
1300 6200 1700 6200
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616DE7D1
|
||||
P 1700 6300
|
||||
AR Path="/616DE7D1" Ref="C?" Part="1"
|
||||
AR Path="/5F6DA71D/616DE7D1" Ref="C19" Part="1"
|
||||
F 0 "C19" H 1750 6350 50 0000 L CNN
|
||||
F 1 "10u" H 1750 6250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 1700 6300 50 0001 C CNN
|
||||
F 3 "~" H 1700 6300 50 0001 C CNN
|
||||
1 1700 6300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 2900 6400
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616DE7DB
|
||||
P 2900 6300
|
||||
AR Path="/616DE7DB" Ref="C?" Part="1"
|
||||
AR Path="/5F6DA71D/616DE7DB" Ref="C22" Part="1"
|
||||
F 0 "C22" H 2950 6350 50 0000 L CNN
|
||||
F 1 "10u" H 2950 6250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 2900 6300 50 0001 C CNN
|
||||
F 3 "~" H 2900 6300 50 0001 C CNN
|
||||
1 2900 6300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616DE7E8
|
||||
P 1300 6300
|
||||
AR Path="/616DE7E8" Ref="C?" Part="1"
|
||||
AR Path="/5F6DA71D/616DE7E8" Ref="C18" Part="1"
|
||||
F 0 "C18" H 1350 6350 50 0000 L CNN
|
||||
F 1 "10u" H 1350 6250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 1300 6300 50 0001 C CNN
|
||||
F 3 "~" H 1300 6300 50 0001 C CNN
|
||||
1 1300 6300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2750 3550 2750 3650
|
||||
Connection ~ 2750 3650
|
||||
Wire Wire Line
|
||||
2750 3650 2750 3750
|
||||
Connection ~ 2750 3750
|
||||
Wire Wire Line
|
||||
2750 3750 2750 3850
|
||||
Connection ~ 2750 3850
|
||||
Wire Wire Line
|
||||
2750 3850 2750 3950
|
||||
$Comp
|
||||
L power:+5V #PWR0151
|
||||
U 1 1 616E93B6
|
||||
P 1300 6200
|
||||
F 0 "#PWR0151" H 1300 6050 50 0001 C CNN
|
||||
F 1 "+5V" H 1300 6350 50 0000 C CNN
|
||||
F 2 "" H 1300 6200 50 0001 C CNN
|
||||
F 3 "" H 1300 6200 50 0001 C CNN
|
||||
1 1300 6200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 1300 6200
|
||||
$Comp
|
||||
L power:-12V #PWR0152
|
||||
U 1 1 616F1447
|
||||
P 3700 6200
|
||||
F 0 "#PWR0152" H 3700 6300 50 0001 C CNN
|
||||
F 1 "-12V" H 3700 6350 50 0000 C CNN
|
||||
F 2 "" H 3700 6200 50 0001 C CNN
|
||||
F 3 "" H 3700 6200 50 0001 C CNN
|
||||
1 3700 6200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 616F27A0
|
||||
P 4100 6400
|
||||
AR Path="/616F27A0" Ref="#PWR?" Part="1"
|
||||
AR Path="/5F6DA71D/616F27A0" Ref="#PWR0153" Part="1"
|
||||
F 0 "#PWR0153" H 4100 6150 50 0001 C CNN
|
||||
F 1 "GND" H 4100 6250 50 0000 C CNN
|
||||
F 2 "" H 4100 6400 50 0001 C CNN
|
||||
F 3 "" H 4100 6400 50 0001 C CNN
|
||||
1 4100 6400
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3700 6400 4100 6400
|
||||
Connection ~ 3700 6400
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 616F27B1
|
||||
P 3700 6300
|
||||
AR Path="/616F27B1" Ref="C?" Part="1"
|
||||
AR Path="/5F6DA71D/616F27B1" Ref="C24" Part="1"
|
||||
F 0 "C24" H 3750 6350 50 0000 L CNN
|
||||
F 1 "10u" H 3750 6250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 3700 6300 50 0001 C CNN
|
||||
F 3 "~" H 3700 6300 50 0001 C CNN
|
||||
1 3700 6300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:-5V #PWR0154
|
||||
U 1 1 616FD697
|
||||
P 2100 6200
|
||||
F 0 "#PWR0154" H 2100 6300 50 0001 C CNN
|
||||
F 1 "-5V" H 2100 6350 50 0000 C CNN
|
||||
F 2 "" H 2100 6200 50 0001 C CNN
|
||||
F 3 "" H 2100 6200 50 0001 C CNN
|
||||
1 2100 6200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+12V #PWR0155
|
||||
U 1 1 616F0982
|
||||
P 2900 6200
|
||||
F 0 "#PWR0155" H 2900 6050 50 0001 C CNN
|
||||
F 1 "+12V" H 2900 6350 50 0000 C CNN
|
||||
F 2 "" H 2900 6200 50 0001 C CNN
|
||||
F 3 "" H 2900 6200 50 0001 C CNN
|
||||
1 2900 6200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0156
|
||||
U 1 1 61704865
|
||||
P 4450 2700
|
||||
F 0 "#PWR0156" H 4450 2450 50 0001 C CNN
|
||||
F 1 "GND" H 4455 2527 50 0000 C CNN
|
||||
F 2 "" H 4450 2700 50 0001 C CNN
|
||||
F 3 "" H 4450 2700 50 0001 C CNN
|
||||
1 4450 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4050 2500 4450 2500
|
||||
$Comp
|
||||
L power:+5V #PWR0157
|
||||
U 1 1 6170B699
|
||||
P 4350 2400
|
||||
F 0 "#PWR0157" H 4350 2250 50 0001 C CNN
|
||||
F 1 "+5V" H 4350 2550 50 0000 C CNN
|
||||
F 2 "" H 4350 2400 50 0001 C CNN
|
||||
F 3 "" H 4350 2400 50 0001 C CNN
|
||||
1 4350 2400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4450 2500 4450 2700
|
||||
Wire Wire Line
|
||||
4050 2600 4350 2600
|
||||
Wire Wire Line
|
||||
4350 2600 4350 2400
|
||||
NoConn ~ 4050 2700
|
||||
NoConn ~ 4050 3300
|
||||
Wire Wire Line
|
||||
2750 3150 2750 3050
|
||||
Connection ~ 2750 2450
|
||||
Wire Wire Line
|
||||
2750 2450 2750 2350
|
||||
Connection ~ 2750 2550
|
||||
Wire Wire Line
|
||||
2750 2550 2750 2450
|
||||
Connection ~ 2750 2650
|
||||
Wire Wire Line
|
||||
2750 2650 2750 2550
|
||||
Connection ~ 2750 2750
|
||||
Wire Wire Line
|
||||
2750 2750 2750 2650
|
||||
Connection ~ 2750 2850
|
||||
Wire Wire Line
|
||||
2750 2850 2750 2750
|
||||
Connection ~ 2750 2950
|
||||
Wire Wire Line
|
||||
2750 2950 2750 2850
|
||||
Connection ~ 2750 3050
|
||||
Wire Wire Line
|
||||
2750 3050 2750 2950
|
||||
Connection ~ 2750 3950
|
||||
Connection ~ 2750 2350
|
||||
Wire Wire Line
|
||||
4050 3500 4450 3500
|
||||
Text HLabel 4350 3700 2 50 BiDi ~ 0
|
||||
D[15..0]
|
||||
Entry Wire Line
|
||||
4250 3600 4350 3700
|
||||
Entry Wire Line
|
||||
4250 3700 4350 3800
|
||||
Entry Wire Line
|
||||
4250 3800 4350 3900
|
||||
Entry Wire Line
|
||||
4250 3900 4350 4000
|
||||
Entry Wire Line
|
||||
4250 4000 4350 4100
|
||||
Entry Wire Line
|
||||
4250 4100 4350 4200
|
||||
Entry Wire Line
|
||||
4250 4200 4350 4300
|
||||
Entry Wire Line
|
||||
4250 4300 4350 4400
|
||||
Entry Wire Line
|
||||
4250 4400 4350 4500
|
||||
Entry Wire Line
|
||||
4250 4500 4350 4600
|
||||
Entry Wire Line
|
||||
4250 4600 4350 4700
|
||||
Entry Wire Line
|
||||
4250 4700 4350 4800
|
||||
Entry Wire Line
|
||||
4250 4800 4350 4900
|
||||
Entry Wire Line
|
||||
4250 4900 4350 5000
|
||||
Entry Wire Line
|
||||
4250 5000 4350 5100
|
||||
Entry Wire Line
|
||||
4250 5100 4350 5200
|
||||
Wire Wire Line
|
||||
4050 5200 4300 5200
|
||||
Wire Wire Line
|
||||
4300 5200 4300 5250
|
||||
Wire Wire Line
|
||||
4300 5250 4400 5250
|
||||
Wire Wire Line
|
||||
4400 5250 4400 5200
|
||||
Wire Wire Line
|
||||
4400 5200 4500 5200
|
||||
$Comp
|
||||
L power:-5V #PWR0109
|
||||
U 1 1 6176540D
|
||||
P 2750 5450
|
||||
F 0 "#PWR0109" H 2750 5550 50 0001 C CNN
|
||||
F 1 "-5V" H 2750 5600 50 0000 C CNN
|
||||
F 2 "" H 2750 5450 50 0001 C CNN
|
||||
F 3 "" H 2750 5450 50 0001 C CNN
|
||||
1 2750 5450
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+12V #PWR0110
|
||||
U 1 1 6176B64B
|
||||
P 1600 5400
|
||||
F 0 "#PWR0110" H 1600 5250 50 0001 C CNN
|
||||
F 1 "+12V" H 1600 5550 50 0000 C CNN
|
||||
F 2 "" H 1600 5400 50 0001 C CNN
|
||||
F 3 "" H 1600 5400 50 0001 C CNN
|
||||
1 1600 5400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1500 5400 1500 5300
|
||||
Connection ~ 1500 5400
|
||||
Wire Wire Line
|
||||
1600 5400 1500 5400
|
||||
$Comp
|
||||
L power:+12V #PWR0111
|
||||
U 1 1 61774C31
|
||||
P 2850 5350
|
||||
F 0 "#PWR0111" H 2850 5200 50 0001 C CNN
|
||||
F 1 "+12V" H 2850 5500 50 0000 C CNN
|
||||
F 2 "" H 2850 5350 50 0001 C CNN
|
||||
F 3 "" H 2850 5350 50 0001 C CNN
|
||||
1 2850 5350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2850 5350 2750 5350
|
||||
Wire Wire Line
|
||||
2750 5250 2750 5350
|
||||
Connection ~ 2750 5350
|
||||
$Comp
|
||||
L power:-12V #PWR0112
|
||||
U 1 1 6177FFC5
|
||||
P 4050 5400
|
||||
F 0 "#PWR0112" H 4050 5500 50 0001 C CNN
|
||||
F 1 "-12V" H 4050 5550 50 0000 C CNN
|
||||
F 2 "" H 4050 5400 50 0001 C CNN
|
||||
F 3 "" H 4050 5400 50 0001 C CNN
|
||||
1 4050 5400
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2100 6400 2900 6400
|
||||
Wire Wire Line
|
||||
2900 6400 3700 6400
|
||||
Wire Bus Line
|
||||
4350 3700 4350 5200
|
||||
Wire Bus Line
|
||||
1800 2700 1800 4900
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 9 10
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Regulator_Linear:AP1117-33 U3
|
||||
U 1 1 61B3AB93
|
||||
P 5250 2100
|
||||
F 0 "U3" H 5250 2300 50 0000 C CNN
|
||||
F 1 "AZ1117CH-3.3" H 5250 2200 50 0000 C BNN
|
||||
F 2 "stdpads:SOT-223" H 5250 2300 50 0001 C CNN
|
||||
F 3 "http://www.diodes.com/datasheets/AP1117.pdf" H 5350 1850 50 0001 C CNN
|
||||
1 5250 2100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0129
|
||||
U 1 1 61B3BD83
|
||||
P 4850 2100
|
||||
F 0 "#PWR0129" H 4850 1950 50 0001 C CNN
|
||||
F 1 "+5V" H 4850 2250 50 0000 C CNN
|
||||
F 2 "" H 4850 2100 50 0001 C CNN
|
||||
F 3 "" H 4850 2100 50 0001 C CNN
|
||||
1 4850 2100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4850 2100 4950 2100
|
||||
Wire Wire Line
|
||||
5550 2100 5650 2100
|
||||
$Comp
|
||||
L power:GND #PWR0130
|
||||
U 1 1 61B3CD29
|
||||
P 5250 2400
|
||||
F 0 "#PWR0130" H 5250 2150 50 0001 C CNN
|
||||
F 1 "GND" H 5250 2250 50 0000 C CNN
|
||||
F 2 "" H 5250 2400 50 0001 C CNN
|
||||
F 3 "" H 5250 2400 50 0001 C CNN
|
||||
1 5250 2400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3V3 #PWR0131
|
||||
U 1 1 61B3D39E
|
||||
P 6050 2100
|
||||
F 0 "#PWR0131" H 6050 1950 50 0001 C CNN
|
||||
F 1 "+3V3" H 6050 2250 50 0000 C CNN
|
||||
F 2 "" H 6050 2100 50 0001 C CNN
|
||||
F 3 "" H 6050 2100 50 0001 C CNN
|
||||
1 6050 2100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C3
|
||||
U 1 1 61B3DF5F
|
||||
P 4850 2250
|
||||
F 0 "C3" H 4750 2300 50 0000 R CNN
|
||||
F 1 "10u" H 4750 2200 50 0000 R CNN
|
||||
F 2 "stdpads:C_0805" H 4850 2250 50 0001 C CNN
|
||||
F 3 "~" H 4850 2250 50 0001 C CNN
|
||||
1 4850 2250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4850 2400 5250 2400
|
||||
Connection ~ 5250 2400
|
||||
Wire Wire Line
|
||||
4850 2350 4850 2400
|
||||
Wire Wire Line
|
||||
4850 2100 4850 2150
|
||||
Connection ~ 4850 2100
|
||||
$Comp
|
||||
L Device:C_Small C7
|
||||
U 1 1 61B3E861
|
||||
P 5650 2250
|
||||
F 0 "C7" H 5550 2300 50 0000 R CNN
|
||||
F 1 "10u" H 5550 2200 50 0000 R CNN
|
||||
F 2 "stdpads:C_0805" H 5650 2250 50 0001 C CNN
|
||||
F 3 "~" H 5650 2250 50 0001 C CNN
|
||||
1 5650 2250
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5250 2400 5650 2400
|
||||
Wire Wire Line
|
||||
5650 2400 5650 2350
|
||||
Wire Wire Line
|
||||
5650 2100 5650 2150
|
||||
Connection ~ 5650 2100
|
||||
$Comp
|
||||
L Device:C_Small C9
|
||||
U 1 1 61B3EE84
|
||||
P 5650 3050
|
||||
F 0 "C9" H 5550 3100 50 0000 R CNN
|
||||
F 1 "10u" H 5550 3000 50 0000 R CNN
|
||||
F 2 "stdpads:C_0805" H 5650 3050 50 0001 C CNN
|
||||
F 3 "~" H 5650 3050 50 0001 C CNN
|
||||
1 5650 3050
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5650 2100 6050 2100
|
||||
Wire Wire Line
|
||||
6050 2100 6050 2150
|
||||
Wire Wire Line
|
||||
6050 2350 6050 2400
|
||||
Wire Wire Line
|
||||
6050 2400 5650 2400
|
||||
Connection ~ 5650 2400
|
||||
Connection ~ 6050 2100
|
||||
$Comp
|
||||
L GW_Power:AZ1117CH2 U6
|
||||
U 1 1 61B4296A
|
||||
P 5250 2900
|
||||
F 0 "U6" H 5250 3100 50 0000 C CNN
|
||||
F 1 "AZ1117CH2-3.3" H 5250 3000 50 0000 C BNN
|
||||
F 2 "stdpads:SOT-223" H 5250 3100 50 0001 C CNN
|
||||
F 3 "http://www.diodes.com/datasheets/AP1117.pdf" H 5350 2650 50 0001 C CNN
|
||||
1 5250 2900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0136
|
||||
U 1 1 61B42970
|
||||
P 4850 2900
|
||||
F 0 "#PWR0136" H 4850 2750 50 0001 C CNN
|
||||
F 1 "+5V" H 4850 3050 50 0000 C CNN
|
||||
F 2 "" H 4850 2900 50 0001 C CNN
|
||||
F 3 "" H 4850 2900 50 0001 C CNN
|
||||
1 4850 2900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4850 2900 4950 2900
|
||||
Wire Wire Line
|
||||
5550 2900 5650 2900
|
||||
$Comp
|
||||
L power:GND #PWR0137
|
||||
U 1 1 61B42978
|
||||
P 5250 3200
|
||||
F 0 "#PWR0137" H 5250 2950 50 0001 C CNN
|
||||
F 1 "GND" H 5250 3050 50 0000 C CNN
|
||||
F 2 "" H 5250 3200 50 0001 C CNN
|
||||
F 3 "" H 5250 3200 50 0001 C CNN
|
||||
1 5250 3200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3V3 #PWR0139
|
||||
U 1 1 61B4297E
|
||||
P 6050 2900
|
||||
F 0 "#PWR0139" H 6050 2750 50 0001 C CNN
|
||||
F 1 "+3V3" H 6050 3050 50 0000 C CNN
|
||||
F 2 "" H 6050 2900 50 0001 C CNN
|
||||
F 3 "" H 6050 2900 50 0001 C CNN
|
||||
1 6050 2900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C4
|
||||
U 1 1 61B42984
|
||||
P 4850 3050
|
||||
F 0 "C4" H 4750 3100 50 0000 R CNN
|
||||
F 1 "10u" H 4750 3000 50 0000 R CNN
|
||||
F 2 "stdpads:C_0805" H 4850 3050 50 0001 C CNN
|
||||
F 3 "~" H 4850 3050 50 0001 C CNN
|
||||
1 4850 3050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4850 3200 5250 3200
|
||||
Connection ~ 5250 3200
|
||||
Wire Wire Line
|
||||
4850 3150 4850 3200
|
||||
Wire Wire Line
|
||||
4850 2900 4850 2950
|
||||
Connection ~ 4850 2900
|
||||
$Comp
|
||||
L Device:C_Small C8
|
||||
U 1 1 61B4298F
|
||||
P 6050 2250
|
||||
F 0 "C8" H 5950 2300 50 0000 R CNN
|
||||
F 1 "10u" H 5950 2200 50 0000 R CNN
|
||||
F 2 "stdpads:C_0805" H 6050 2250 50 0001 C CNN
|
||||
F 3 "~" H 6050 2250 50 0001 C CNN
|
||||
1 6050 2250
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5250 3200 5650 3200
|
||||
Wire Wire Line
|
||||
5650 3200 5650 3150
|
||||
Wire Wire Line
|
||||
5650 2900 5650 2950
|
||||
Connection ~ 5650 2900
|
||||
$Comp
|
||||
L Device:C_Small C10
|
||||
U 1 1 61B42999
|
||||
P 6050 3050
|
||||
F 0 "C10" H 5950 3100 50 0000 R CNN
|
||||
F 1 "10u" H 5950 3000 50 0000 R CNN
|
||||
F 2 "stdpads:C_0805" H 6050 3050 50 0001 C CNN
|
||||
F 3 "~" H 6050 3050 50 0001 C CNN
|
||||
1 6050 3050
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5650 2900 6050 2900
|
||||
Wire Wire Line
|
||||
6050 2900 6050 2950
|
||||
Wire Wire Line
|
||||
6050 3150 6050 3200
|
||||
Wire Wire Line
|
||||
6050 3200 5650 3200
|
||||
Connection ~ 5650 3200
|
||||
Connection ~ 6050 2900
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,937 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 2 10
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
Text HLabel 2700 2750 0 50 Input ~ 0
|
||||
RA[11..0]
|
||||
Wire Bus Line
|
||||
2750 2750 2700 2750
|
||||
Entry Wire Line
|
||||
2750 2950 2850 2850
|
||||
Entry Wire Line
|
||||
2750 2850 2850 2750
|
||||
Wire Wire Line
|
||||
3050 2750 2850 2750
|
||||
Wire Wire Line
|
||||
3050 2850 2850 2850
|
||||
Entry Wire Line
|
||||
2750 3150 2850 3050
|
||||
Entry Wire Line
|
||||
2750 3050 2850 2950
|
||||
Wire Wire Line
|
||||
3050 2950 2850 2950
|
||||
Wire Wire Line
|
||||
3050 3050 2850 3050
|
||||
Entry Wire Line
|
||||
2750 3350 2850 3250
|
||||
Entry Wire Line
|
||||
2750 3250 2850 3150
|
||||
Wire Wire Line
|
||||
3050 3150 2850 3150
|
||||
Wire Wire Line
|
||||
3050 3250 2850 3250
|
||||
Entry Wire Line
|
||||
2750 3550 2850 3450
|
||||
Entry Wire Line
|
||||
2750 3450 2850 3350
|
||||
Wire Wire Line
|
||||
3050 3350 2850 3350
|
||||
Wire Wire Line
|
||||
3050 3450 2850 3450
|
||||
Entry Wire Line
|
||||
2750 3750 2850 3650
|
||||
Entry Wire Line
|
||||
2750 3650 2850 3550
|
||||
Wire Wire Line
|
||||
3050 3550 2850 3550
|
||||
Wire Wire Line
|
||||
3050 3650 2850 3650
|
||||
Entry Wire Line
|
||||
2750 3850 2850 3750
|
||||
Wire Wire Line
|
||||
3050 3750 2850 3750
|
||||
Text Label 3050 3750 2 50 ~ 0
|
||||
RA11
|
||||
Text Label 3050 3650 2 50 ~ 0
|
||||
RA10
|
||||
Text Label 3050 3550 2 50 ~ 0
|
||||
RA9
|
||||
Text Label 3050 3450 2 50 ~ 0
|
||||
RA8
|
||||
Text Label 3050 3350 2 50 ~ 0
|
||||
RA7
|
||||
Text Label 3050 3250 2 50 ~ 0
|
||||
RA6
|
||||
Text Label 3050 3150 2 50 ~ 0
|
||||
RA5
|
||||
Text Label 3050 3050 2 50 ~ 0
|
||||
RA4
|
||||
Text Label 3050 2950 2 50 ~ 0
|
||||
RA3
|
||||
Text Label 3050 2850 2 50 ~ 0
|
||||
RA2
|
||||
Text Label 3050 2750 2 50 ~ 0
|
||||
RA1
|
||||
$Comp
|
||||
L GW_RAM:DRAM-2Mx8-SOP-28 U8
|
||||
U 1 1 6140764B
|
||||
P 3450 3250
|
||||
F 0 "U8" H 3450 4000 50 0000 C CNN
|
||||
F 1 "KM48C2100" V 3450 3250 50 0000 C CNN
|
||||
F 2 "stdpads:SOJ-28_300mil" H 3450 2400 50 0001 C CNN
|
||||
F 3 "" H 3450 2700 50 0001 C CNN
|
||||
1 3450 3250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Entry Wire Line
|
||||
2750 2750 2850 2650
|
||||
Wire Wire Line
|
||||
3050 2650 2850 2650
|
||||
Text Label 3050 2650 2 50 ~ 0
|
||||
RA0
|
||||
$Comp
|
||||
L power:GND #PWR0133
|
||||
U 1 1 6144A3AD
|
||||
P 3050 3850
|
||||
F 0 "#PWR0133" H 3050 3600 50 0001 C CNN
|
||||
F 1 "GND" H 3050 3700 50 0000 C CNN
|
||||
F 2 "" H 3050 3850 50 0001 C CNN
|
||||
F 3 "" H 3050 3850 50 0001 C CNN
|
||||
1 3050 3850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3850 3150 4050 3150
|
||||
Wire Wire Line
|
||||
4050 2750 3850 2750
|
||||
Wire Wire Line
|
||||
3850 3450 4050 3450
|
||||
Wire Wire Line
|
||||
3850 3350 4050 3350
|
||||
Wire Wire Line
|
||||
4050 2950 3850 2950
|
||||
Wire Wire Line
|
||||
3850 3250 4050 3250
|
||||
Wire Wire Line
|
||||
4050 3050 3850 3050
|
||||
Text Label 3850 2750 0 50 ~ 0
|
||||
D7
|
||||
Text Label 3850 3450 0 50 ~ 0
|
||||
D6
|
||||
Text Label 3850 3350 0 50 ~ 0
|
||||
D4
|
||||
Text Label 3850 2950 0 50 ~ 0
|
||||
D3
|
||||
Text Label 3850 3250 0 50 ~ 0
|
||||
D2
|
||||
Text Label 3850 3050 0 50 ~ 0
|
||||
D1
|
||||
Text Label 3850 3150 0 50 ~ 0
|
||||
D0
|
||||
Text HLabel 3850 3850 2 50 Input ~ 0
|
||||
~OE~
|
||||
Text HLabel 3850 3550 2 50 Input ~ 0
|
||||
~CAS~
|
||||
Text HLabel 3850 3650 2 50 Input ~ 0
|
||||
~RAS~
|
||||
Text HLabel 3850 3750 2 50 Input ~ 0
|
||||
L~WE~
|
||||
Entry Wire Line
|
||||
2750 4450 2850 4350
|
||||
Entry Wire Line
|
||||
2750 4350 2850 4250
|
||||
Wire Wire Line
|
||||
3050 5150 2850 5150
|
||||
Entry Wire Line
|
||||
2750 4650 2850 4550
|
||||
Entry Wire Line
|
||||
2750 4550 2850 4450
|
||||
Wire Wire Line
|
||||
3050 5250 2850 5250
|
||||
Wire Wire Line
|
||||
3050 5050 2850 5050
|
||||
Entry Wire Line
|
||||
2750 4850 2850 4750
|
||||
Entry Wire Line
|
||||
2750 4750 2850 4650
|
||||
Wire Wire Line
|
||||
3050 4950 2850 4950
|
||||
Wire Wire Line
|
||||
3050 4850 2850 4850
|
||||
Entry Wire Line
|
||||
2750 5050 2850 4950
|
||||
Entry Wire Line
|
||||
2750 4950 2850 4850
|
||||
Wire Wire Line
|
||||
3050 4750 2850 4750
|
||||
Entry Wire Line
|
||||
2750 5250 2850 5150
|
||||
Entry Wire Line
|
||||
2750 5150 2850 5050
|
||||
Wire Wire Line
|
||||
3050 4550 2850 4550
|
||||
Wire Wire Line
|
||||
3050 4350 2850 4350
|
||||
Entry Wire Line
|
||||
2750 5350 2850 5250
|
||||
Wire Wire Line
|
||||
3050 4450 2850 4450
|
||||
Text Label 3050 4450 2 50 ~ 0
|
||||
RA11
|
||||
Text Label 3050 4350 2 50 ~ 0
|
||||
RA10
|
||||
Text Label 3050 4550 2 50 ~ 0
|
||||
RA9
|
||||
Text Label 3050 4750 2 50 ~ 0
|
||||
RA7
|
||||
Text Label 3050 4850 2 50 ~ 0
|
||||
RA6
|
||||
Text Label 3050 4950 2 50 ~ 0
|
||||
RA5
|
||||
Text Label 3050 5050 2 50 ~ 0
|
||||
RA4
|
||||
Text Label 3050 5250 2 50 ~ 0
|
||||
RA3
|
||||
Text Label 3050 5150 2 50 ~ 0
|
||||
RA2
|
||||
$Comp
|
||||
L GW_RAM:DRAM-2Mx8-SOP-28 U9
|
||||
U 1 1 614735EB
|
||||
P 3450 4750
|
||||
F 0 "U9" H 3450 5500 50 0000 C CNN
|
||||
F 1 "KM48C2100" V 3450 4750 50 0000 C CNN
|
||||
F 2 "stdpads:SOJ-28_300mil" H 3450 3900 50 0001 C CNN
|
||||
F 3 "" H 3450 4200 50 0001 C CNN
|
||||
1 3450 4750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Entry Wire Line
|
||||
2750 4250 2850 4150
|
||||
Wire Wire Line
|
||||
3050 4250 2850 4250
|
||||
Text Label 3050 4250 2 50 ~ 0
|
||||
RA0
|
||||
$Comp
|
||||
L power:GND #PWR0134
|
||||
U 1 1 614735F4
|
||||
P 3050 5350
|
||||
F 0 "#PWR0134" H 3050 5100 50 0001 C CNN
|
||||
F 1 "GND" H 3050 5200 50 0000 C CNN
|
||||
F 2 "" H 3050 5350 50 0001 C CNN
|
||||
F 3 "" H 3050 5350 50 0001 C CNN
|
||||
1 3050 5350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text HLabel 3850 5350 2 50 Input ~ 0
|
||||
~OE~
|
||||
Text HLabel 3850 5050 2 50 Input ~ 0
|
||||
~CAS~
|
||||
Text HLabel 3850 5150 2 50 Input ~ 0
|
||||
~RAS~
|
||||
Text HLabel 3850 5250 2 50 Input ~ 0
|
||||
U~WE~
|
||||
Wire Wire Line
|
||||
3850 4950 4050 4950
|
||||
Wire Wire Line
|
||||
3850 4850 4050 4850
|
||||
Wire Wire Line
|
||||
3850 4750 4050 4750
|
||||
Wire Wire Line
|
||||
3850 4650 4050 4650
|
||||
Text Label 3850 4650 0 50 ~ 0
|
||||
D8
|
||||
Text Label 3850 4750 0 50 ~ 0
|
||||
D10
|
||||
Text Label 3850 4850 0 50 ~ 0
|
||||
D12
|
||||
Text Label 3850 4950 0 50 ~ 0
|
||||
D14
|
||||
Entry Wire Line
|
||||
4150 4950 4050 4850
|
||||
Entry Wire Line
|
||||
4150 5050 4050 4950
|
||||
Entry Wire Line
|
||||
4150 4750 4050 4650
|
||||
Entry Wire Line
|
||||
4150 4850 4050 4750
|
||||
Entry Wire Line
|
||||
4150 4550 4050 4450
|
||||
Entry Wire Line
|
||||
4150 4650 4050 4550
|
||||
Entry Wire Line
|
||||
4150 4350 4050 4250
|
||||
Entry Wire Line
|
||||
4150 4450 4050 4350
|
||||
Entry Wire Line
|
||||
4150 3450 4050 3350
|
||||
Entry Wire Line
|
||||
4150 3550 4050 3450
|
||||
Entry Wire Line
|
||||
4150 3250 4050 3150
|
||||
Entry Wire Line
|
||||
4150 3350 4050 3250
|
||||
Entry Wire Line
|
||||
4150 3050 4050 2950
|
||||
Entry Wire Line
|
||||
4150 3150 4050 3050
|
||||
Entry Wire Line
|
||||
4150 2850 4050 2750
|
||||
Entry Wire Line
|
||||
4150 2950 4050 2850
|
||||
Text HLabel 4200 2850 2 50 BiDi ~ 0
|
||||
D[15..0]
|
||||
Wire Bus Line
|
||||
4200 2850 4150 2850
|
||||
Connection ~ 4950 4750
|
||||
Wire Wire Line
|
||||
4550 4550 4950 4550
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 61609D38
|
||||
P 4950 4650
|
||||
AR Path="/61609D38" Ref="C?" Part="1"
|
||||
AR Path="/60D70CB4/61609D38" Ref="C?" Part="1"
|
||||
AR Path="/5F723900/61609D38" Ref="C13" Part="1"
|
||||
F 0 "C13" H 5000 4700 50 0000 L CNN
|
||||
F 1 "2u2" H 5000 4600 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 4950 4650 50 0001 C CNN
|
||||
F 3 "~" H 4950 4650 50 0001 C CNN
|
||||
1 4950 4650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 61609D3F
|
||||
P 4550 4650
|
||||
AR Path="/61609D3F" Ref="C?" Part="1"
|
||||
AR Path="/60D70CB4/61609D3F" Ref="C?" Part="1"
|
||||
AR Path="/5F723900/61609D3F" Ref="C12" Part="1"
|
||||
F 0 "C12" H 4600 4700 50 0000 L CNN
|
||||
F 1 "2u2" H 4600 4600 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 4550 4650 50 0001 C CNN
|
||||
F 3 "~" H 4550 4650 50 0001 C CNN
|
||||
1 4550 4650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4550 4750 4950 4750
|
||||
Connection ~ 5350 4750
|
||||
Wire Wire Line
|
||||
4950 4550 5350 4550
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 6160B1A0
|
||||
P 5350 4650
|
||||
AR Path="/6160B1A0" Ref="C?" Part="1"
|
||||
AR Path="/60D70CB4/6160B1A0" Ref="C?" Part="1"
|
||||
AR Path="/5F723900/6160B1A0" Ref="C14" Part="1"
|
||||
F 0 "C14" H 5400 4700 50 0000 L CNN
|
||||
F 1 "2u2" H 5400 4600 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 5350 4650 50 0001 C CNN
|
||||
F 3 "~" H 5350 4650 50 0001 C CNN
|
||||
1 5350 4650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4950 4750 5350 4750
|
||||
Connection ~ 5750 4750
|
||||
Wire Wire Line
|
||||
5350 4550 5750 4550
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 6160C7C7
|
||||
P 5750 4650
|
||||
AR Path="/6160C7C7" Ref="C?" Part="1"
|
||||
AR Path="/60D70CB4/6160C7C7" Ref="C?" Part="1"
|
||||
AR Path="/5F723900/6160C7C7" Ref="C15" Part="1"
|
||||
F 0 "C15" H 5800 4700 50 0000 L CNN
|
||||
F 1 "2u2" H 5800 4600 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 5750 4650 50 0001 C CNN
|
||||
F 3 "~" H 5750 4650 50 0001 C CNN
|
||||
1 5750 4650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0135
|
||||
U 1 1 6160C7CD
|
||||
P 5750 4750
|
||||
AR Path="/5F723900/6160C7CD" Ref="#PWR0135" Part="1"
|
||||
AR Path="/60D70CB4/6160C7CD" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0135" H 5750 4500 50 0001 C CNN
|
||||
F 1 "GND" H 5750 4600 50 0000 C CNN
|
||||
F 2 "" H 5750 4750 50 0001 C CNN
|
||||
F 3 "" H 5750 4750 50 0001 C CNN
|
||||
1 5750 4750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5350 4750 5750 4750
|
||||
Connection ~ 4950 4550
|
||||
Connection ~ 5350 4550
|
||||
$Comp
|
||||
L power:+5V #PWR?
|
||||
U 1 1 61609D30
|
||||
P 4550 4550
|
||||
AR Path="/61609D30" Ref="#PWR?" Part="1"
|
||||
AR Path="/60D70CB4/61609D30" Ref="#PWR?" Part="1"
|
||||
AR Path="/5F723900/61609D30" Ref="#PWR0138" Part="1"
|
||||
F 0 "#PWR0138" H 4550 4400 50 0001 C CNN
|
||||
F 1 "+5V" H 4550 4700 50 0000 C CNN
|
||||
F 2 "" H 4550 4550 50 0001 C CNN
|
||||
F 3 "" H 4550 4550 50 0001 C CNN
|
||||
1 4550 4550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 4550 4550
|
||||
$Comp
|
||||
L GW_RAM:Flash-512Kx8-PLCC-32 U10
|
||||
U 1 1 61871415
|
||||
P 8700 2300
|
||||
AR Path="/5F723900/61871415" Ref="U10" Part="1"
|
||||
AR Path="/60D70CB4/61871415" Ref="U?" Part="1"
|
||||
F 0 "U10" H 8700 3350 50 0000 C CNN
|
||||
F 1 "39SF040" V 8700 2300 50 0000 C CNN
|
||||
F 2 "stdpads:PLCC-32" H 8700 1250 50 0001 C CNN
|
||||
F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/20005022C.pdf" H 8700 2300 50 0001 C CNN
|
||||
1 8700 2300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0141
|
||||
U 1 1 6187141B
|
||||
P 9100 3200
|
||||
AR Path="/5F723900/6187141B" Ref="#PWR0141" Part="1"
|
||||
AR Path="/60D70CB4/6187141B" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0141" H 9100 2950 50 0001 C CNN
|
||||
F 1 "GND" H 9100 3050 50 0000 C CNN
|
||||
F 2 "" H 9100 3200 50 0001 C CNN
|
||||
F 3 "" H 9100 3200 50 0001 C CNN
|
||||
1 9100 3200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text HLabel 9100 2900 2 50 Input ~ 0
|
||||
~OE~
|
||||
Text HLabel 9100 2700 2 50 Input ~ 0
|
||||
ROM~CS~
|
||||
$Comp
|
||||
L power:GND #PWR0142
|
||||
U 1 1 61871423
|
||||
P 9100 5400
|
||||
AR Path="/5F723900/61871423" Ref="#PWR0142" Part="1"
|
||||
AR Path="/60D70CB4/61871423" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0142" H 9100 5150 50 0001 C CNN
|
||||
F 1 "GND" H 9100 5250 50 0000 C CNN
|
||||
F 2 "" H 9100 5400 50 0001 C CNN
|
||||
F 3 "" H 9100 5400 50 0001 C CNN
|
||||
1 9100 5400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text HLabel 9100 5000 2 50 Input ~ 0
|
||||
ROM~WE~
|
||||
Text HLabel 9100 4900 2 50 Input ~ 0
|
||||
ROM~CS~
|
||||
Text HLabel 9100 5100 2 50 Input ~ 0
|
||||
~OE~
|
||||
$Comp
|
||||
L GW_RAM:Flash-512Kx8-PLCC-32 U11
|
||||
U 1 1 6187142D
|
||||
P 8700 4500
|
||||
AR Path="/5F723900/6187142D" Ref="U11" Part="1"
|
||||
AR Path="/60D70CB4/6187142D" Ref="U?" Part="1"
|
||||
F 0 "U11" H 8700 5550 50 0000 C CNN
|
||||
F 1 "39SF040" V 8700 4500 50 0000 C CNN
|
||||
F 2 "stdpads:PLCC-32" H 8700 3450 50 0001 C CNN
|
||||
F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/20005022C.pdf" H 8700 4500 50 0001 C CNN
|
||||
1 8700 4500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 9100 1600 0 50 ~ 0
|
||||
D0
|
||||
Text Label 9100 1700 0 50 ~ 0
|
||||
D1
|
||||
Text Label 9100 1800 0 50 ~ 0
|
||||
D2
|
||||
Text Label 9100 1900 0 50 ~ 0
|
||||
D3
|
||||
Text Label 9100 2000 0 50 ~ 0
|
||||
D4
|
||||
Text Label 9100 2100 0 50 ~ 0
|
||||
D5
|
||||
Text Label 9100 2200 0 50 ~ 0
|
||||
D6
|
||||
Text Label 9100 2300 0 50 ~ 0
|
||||
D7
|
||||
Text Label 9100 3800 0 50 ~ 0
|
||||
D8
|
||||
Text Label 9100 3900 0 50 ~ 0
|
||||
D9
|
||||
Text Label 9100 4000 0 50 ~ 0
|
||||
D10
|
||||
Text Label 9100 4100 0 50 ~ 0
|
||||
D11
|
||||
Text Label 9100 4200 0 50 ~ 0
|
||||
D12
|
||||
Text Label 9100 4300 0 50 ~ 0
|
||||
D13
|
||||
Text Label 9100 4400 0 50 ~ 0
|
||||
D14
|
||||
Text Label 9100 4500 0 50 ~ 0
|
||||
D15
|
||||
Wire Wire Line
|
||||
9100 4500 9400 4500
|
||||
Wire Wire Line
|
||||
9100 4400 9400 4400
|
||||
Wire Wire Line
|
||||
9100 4300 9400 4300
|
||||
Wire Wire Line
|
||||
9100 4200 9400 4200
|
||||
Wire Wire Line
|
||||
9100 4100 9400 4100
|
||||
Wire Wire Line
|
||||
9100 4000 9400 4000
|
||||
Wire Wire Line
|
||||
9100 3900 9400 3900
|
||||
Wire Wire Line
|
||||
9100 3800 9400 3800
|
||||
Wire Wire Line
|
||||
9100 2300 9400 2300
|
||||
Wire Wire Line
|
||||
9100 2200 9400 2200
|
||||
Wire Wire Line
|
||||
9100 2100 9400 2100
|
||||
Wire Wire Line
|
||||
9100 2000 9400 2000
|
||||
Wire Wire Line
|
||||
9100 1900 9400 1900
|
||||
Wire Wire Line
|
||||
9100 1800 9400 1800
|
||||
Wire Wire Line
|
||||
9100 1700 9400 1700
|
||||
Wire Wire Line
|
||||
9100 1600 9400 1600
|
||||
Wire Wire Line
|
||||
8300 2300 8100 2300
|
||||
Wire Wire Line
|
||||
8300 3200 8100 3200
|
||||
Wire Wire Line
|
||||
8300 2900 8100 2900
|
||||
Wire Wire Line
|
||||
8300 2500 8100 2500
|
||||
Wire Wire Line
|
||||
8300 2600 8100 2600
|
||||
Wire Wire Line
|
||||
8300 2100 8100 2100
|
||||
Wire Wire Line
|
||||
8300 3000 8100 3000
|
||||
Wire Wire Line
|
||||
8300 3100 8100 3100
|
||||
Wire Wire Line
|
||||
8300 1400 8100 1400
|
||||
Wire Wire Line
|
||||
8300 1500 8100 1500
|
||||
Wire Wire Line
|
||||
8300 1600 8100 1600
|
||||
Wire Wire Line
|
||||
8300 1700 8100 1700
|
||||
Wire Wire Line
|
||||
8300 1800 8100 1800
|
||||
Wire Wire Line
|
||||
8300 1900 8100 1900
|
||||
Wire Wire Line
|
||||
8300 2000 8100 2000
|
||||
Entry Wire Line
|
||||
8100 2900 8000 3000
|
||||
Entry Wire Line
|
||||
8100 2800 8000 2900
|
||||
Entry Wire Line
|
||||
8100 2700 8000 2800
|
||||
Entry Wire Line
|
||||
8100 2600 8000 2700
|
||||
Entry Wire Line
|
||||
8100 2500 8000 2600
|
||||
Entry Wire Line
|
||||
8100 2400 8000 2500
|
||||
Entry Wire Line
|
||||
8100 2300 8000 2400
|
||||
Entry Wire Line
|
||||
8100 2200 8000 2300
|
||||
Entry Wire Line
|
||||
8100 2100 8000 2200
|
||||
Entry Wire Line
|
||||
8100 2000 8000 2100
|
||||
Entry Wire Line
|
||||
8100 1900 8000 2000
|
||||
Entry Wire Line
|
||||
8100 1800 8000 1900
|
||||
Entry Wire Line
|
||||
8100 1700 8000 1800
|
||||
Entry Wire Line
|
||||
8100 1600 8000 1700
|
||||
Entry Wire Line
|
||||
8100 1500 8000 1600
|
||||
Entry Wire Line
|
||||
8100 1400 8000 1500
|
||||
Wire Wire Line
|
||||
8300 2800 8100 2800
|
||||
Wire Wire Line
|
||||
8300 2700 8100 2700
|
||||
Wire Wire Line
|
||||
8300 2200 8100 2200
|
||||
Entry Wire Line
|
||||
8100 3200 8000 3300
|
||||
Entry Wire Line
|
||||
8100 3100 8000 3200
|
||||
Entry Wire Line
|
||||
8100 3000 8000 3100
|
||||
Text Label 8300 2000 2 50 ~ 0
|
||||
A1
|
||||
Text Label 8300 1900 2 50 ~ 0
|
||||
A2
|
||||
Text Label 8300 1800 2 50 ~ 0
|
||||
A3
|
||||
Text Label 8300 1700 2 50 ~ 0
|
||||
A4
|
||||
Text Label 8300 1600 2 50 ~ 0
|
||||
A5
|
||||
Text Label 8300 1500 2 50 ~ 0
|
||||
A6
|
||||
Text Label 8300 1400 2 50 ~ 0
|
||||
A7
|
||||
Text Label 8300 3100 2 50 ~ 0
|
||||
A8
|
||||
Text Label 8300 3000 2 50 ~ 0
|
||||
A9
|
||||
Text Label 8300 2100 2 50 ~ 0
|
||||
A10
|
||||
Text Label 8300 2600 2 50 ~ 0
|
||||
A11
|
||||
Text Label 8300 2500 2 50 ~ 0
|
||||
A13
|
||||
Text Label 8300 2900 2 50 ~ 0
|
||||
A14
|
||||
Text Label 8300 3200 2 50 ~ 0
|
||||
A15
|
||||
Text Label 8300 2300 2 50 ~ 0
|
||||
A16
|
||||
Text Label 8300 2200 2 50 ~ 0
|
||||
A17
|
||||
Text Label 8300 2700 2 50 ~ 0
|
||||
A18
|
||||
Text Label 8300 2800 2 50 ~ 0
|
||||
A19
|
||||
Text HLabel 7950 1500 0 50 Input ~ 0
|
||||
A[23..1]
|
||||
Text HLabel 9550 1700 2 50 BiDi ~ 0
|
||||
D[15..0]
|
||||
Entry Wire Line
|
||||
9400 1600 9500 1700
|
||||
Entry Wire Line
|
||||
9400 1700 9500 1800
|
||||
Entry Wire Line
|
||||
9400 1800 9500 1900
|
||||
Entry Wire Line
|
||||
9400 1900 9500 2000
|
||||
Entry Wire Line
|
||||
9400 2000 9500 2100
|
||||
Entry Wire Line
|
||||
9400 2100 9500 2200
|
||||
Entry Wire Line
|
||||
9400 2200 9500 2300
|
||||
Entry Wire Line
|
||||
9400 2300 9500 2400
|
||||
Entry Wire Line
|
||||
9400 3800 9500 3900
|
||||
Entry Wire Line
|
||||
9400 3900 9500 4000
|
||||
Entry Wire Line
|
||||
9400 4000 9500 4100
|
||||
Entry Wire Line
|
||||
9400 4100 9500 4200
|
||||
Entry Wire Line
|
||||
9400 4200 9500 4300
|
||||
Entry Wire Line
|
||||
9400 4300 9500 4400
|
||||
Entry Wire Line
|
||||
9400 4400 9500 4500
|
||||
Entry Wire Line
|
||||
9400 4500 9500 4600
|
||||
Wire Bus Line
|
||||
9550 1700 9500 1700
|
||||
Wire Bus Line
|
||||
7950 1500 8000 1500
|
||||
Entry Wire Line
|
||||
8100 5100 8000 5200
|
||||
Entry Wire Line
|
||||
8100 5000 8000 5100
|
||||
Entry Wire Line
|
||||
8100 4900 8000 5000
|
||||
Entry Wire Line
|
||||
8100 4800 8000 4900
|
||||
Entry Wire Line
|
||||
8100 4700 8000 4800
|
||||
Entry Wire Line
|
||||
8100 4600 8000 4700
|
||||
Entry Wire Line
|
||||
8100 4500 8000 4600
|
||||
Entry Wire Line
|
||||
8100 4400 8000 4500
|
||||
Entry Wire Line
|
||||
8100 4300 8000 4400
|
||||
Entry Wire Line
|
||||
8100 4200 8000 4300
|
||||
Entry Wire Line
|
||||
8100 4100 8000 4200
|
||||
Entry Wire Line
|
||||
8100 4000 8000 4100
|
||||
Entry Wire Line
|
||||
8100 3900 8000 4000
|
||||
Entry Wire Line
|
||||
8100 3800 8000 3900
|
||||
Entry Wire Line
|
||||
8100 3700 8000 3800
|
||||
Entry Wire Line
|
||||
8100 3600 8000 3700
|
||||
Entry Wire Line
|
||||
8100 5400 8000 5500
|
||||
Entry Wire Line
|
||||
8100 5300 8000 5400
|
||||
Entry Wire Line
|
||||
8100 5200 8000 5300
|
||||
$Comp
|
||||
L power:+5V #PWR?
|
||||
U 1 1 618714D9
|
||||
P 10050 4200
|
||||
AR Path="/618714D9" Ref="#PWR?" Part="1"
|
||||
AR Path="/60D70CB4/618714D9" Ref="#PWR?" Part="1"
|
||||
AR Path="/5F723900/618714D9" Ref="#PWR0145" Part="1"
|
||||
F 0 "#PWR0145" H 10050 4050 50 0001 C CNN
|
||||
F 1 "+5V" H 10050 4350 50 0000 C CNN
|
||||
F 2 "" H 10050 4200 50 0001 C CNN
|
||||
F 3 "" H 10050 4200 50 0001 C CNN
|
||||
1 10050 4200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 10450 4400
|
||||
Wire Wire Line
|
||||
10050 4200 10450 4200
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 618714E1
|
||||
P 10450 4300
|
||||
AR Path="/618714E1" Ref="C?" Part="1"
|
||||
AR Path="/60D70CB4/618714E1" Ref="C?" Part="1"
|
||||
AR Path="/5F723900/618714E1" Ref="C17" Part="1"
|
||||
F 0 "C17" H 10500 4350 50 0000 L CNN
|
||||
F 1 "2u2" H 10500 4250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 10450 4300 50 0001 C CNN
|
||||
F 3 "~" H 10450 4300 50 0001 C CNN
|
||||
1 10450 4300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 10050 4200
|
||||
$Comp
|
||||
L Device:C_Small C?
|
||||
U 1 1 618714E8
|
||||
P 10050 4300
|
||||
AR Path="/618714E8" Ref="C?" Part="1"
|
||||
AR Path="/60D70CB4/618714E8" Ref="C?" Part="1"
|
||||
AR Path="/5F723900/618714E8" Ref="C16" Part="1"
|
||||
F 0 "C16" H 10100 4350 50 0000 L CNN
|
||||
F 1 "2u2" H 10100 4250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0805" H 10050 4300 50 0001 C CNN
|
||||
F 3 "~" H 10050 4300 50 0001 C CNN
|
||||
1 10050 4300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0150
|
||||
U 1 1 618714EE
|
||||
P 10450 4400
|
||||
AR Path="/5F723900/618714EE" Ref="#PWR0150" Part="1"
|
||||
AR Path="/60D70CB4/618714EE" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0150" H 10450 4150 50 0001 C CNN
|
||||
F 1 "GND" H 10450 4250 50 0000 C CNN
|
||||
F 2 "" H 10450 4400 50 0001 C CNN
|
||||
F 3 "" H 10450 4400 50 0001 C CNN
|
||||
1 10450 4400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
10050 4400 10450 4400
|
||||
Text Label 8300 2400 2 50 ~ 0
|
||||
A12
|
||||
Wire Wire Line
|
||||
8300 2400 8100 2400
|
||||
Wire Wire Line
|
||||
8300 3600 8100 3600
|
||||
Wire Wire Line
|
||||
8300 3700 8100 3700
|
||||
Wire Wire Line
|
||||
8300 5000 8100 5000
|
||||
Wire Wire Line
|
||||
8300 3800 8100 3800
|
||||
Wire Wire Line
|
||||
8300 3900 8100 3900
|
||||
Wire Wire Line
|
||||
8300 5400 8100 5400
|
||||
Wire Wire Line
|
||||
8300 4600 8100 4600
|
||||
Wire Wire Line
|
||||
8300 4800 8100 4800
|
||||
Wire Wire Line
|
||||
8300 4300 8100 4300
|
||||
Wire Wire Line
|
||||
8300 4200 8100 4200
|
||||
Wire Wire Line
|
||||
8300 4100 8100 4100
|
||||
Wire Wire Line
|
||||
8300 5100 8100 5100
|
||||
Wire Wire Line
|
||||
8300 4000 8100 4000
|
||||
Wire Wire Line
|
||||
8300 5200 8100 5200
|
||||
Wire Wire Line
|
||||
8300 4700 8100 4700
|
||||
Wire Wire Line
|
||||
8300 4500 8100 4500
|
||||
Wire Wire Line
|
||||
8300 4400 8100 4400
|
||||
Text Label 8300 5200 2 50 ~ 0
|
||||
A1
|
||||
Text Label 8300 4000 2 50 ~ 0
|
||||
A2
|
||||
Text Label 8300 5100 2 50 ~ 0
|
||||
A3
|
||||
Text Label 8300 4100 2 50 ~ 0
|
||||
A4
|
||||
Text Label 8300 4200 2 50 ~ 0
|
||||
A5
|
||||
Text Label 8300 4300 2 50 ~ 0
|
||||
A6
|
||||
Text Label 8300 4800 2 50 ~ 0
|
||||
A7
|
||||
Text Label 8300 4600 2 50 ~ 0
|
||||
A8
|
||||
Text Label 8300 5400 2 50 ~ 0
|
||||
A9
|
||||
Text Label 8300 3900 2 50 ~ 0
|
||||
A10
|
||||
Text Label 8300 3800 2 50 ~ 0
|
||||
A11
|
||||
Text Label 8300 5000 2 50 ~ 0
|
||||
A13
|
||||
Text Label 8300 3700 2 50 ~ 0
|
||||
A14
|
||||
Text Label 8300 3600 2 50 ~ 0
|
||||
A15
|
||||
Text Label 8300 4400 2 50 ~ 0
|
||||
A17
|
||||
Text Label 8300 4500 2 50 ~ 0
|
||||
A18
|
||||
Text Label 8300 4700 2 50 ~ 0
|
||||
A19
|
||||
Text Label 8300 5300 2 50 ~ 0
|
||||
A12
|
||||
Wire Wire Line
|
||||
8300 5300 8100 5300
|
||||
Text Label 8300 4900 2 50 ~ 0
|
||||
A16
|
||||
Wire Wire Line
|
||||
8300 4900 8100 4900
|
||||
Text HLabel 9100 2800 2 50 Input ~ 0
|
||||
ROM~WE~
|
||||
Wire Wire Line
|
||||
3050 4650 2850 4650
|
||||
Text Label 3050 4650 2 50 ~ 0
|
||||
RA8
|
||||
Text Label 3050 4150 2 50 ~ 0
|
||||
RA1
|
||||
Wire Wire Line
|
||||
3050 4150 2850 4150
|
||||
Text Label 3850 2850 0 50 ~ 0
|
||||
D5
|
||||
Wire Wire Line
|
||||
4050 2850 3850 2850
|
||||
Text Label 3850 4250 0 50 ~ 0
|
||||
D15
|
||||
Text Label 3850 4350 0 50 ~ 0
|
||||
D13
|
||||
Text Label 3850 4450 0 50 ~ 0
|
||||
D11
|
||||
Text Label 3850 4550 0 50 ~ 0
|
||||
D9
|
||||
Wire Wire Line
|
||||
4050 4550 3850 4550
|
||||
Wire Wire Line
|
||||
4050 4450 3850 4450
|
||||
Wire Wire Line
|
||||
4050 4350 3850 4350
|
||||
Wire Wire Line
|
||||
3850 4250 4050 4250
|
||||
$Comp
|
||||
L power:+5V #PWR0105
|
||||
U 1 1 61AAB186
|
||||
P 3850 2650
|
||||
F 0 "#PWR0105" H 3850 2500 50 0001 C CNN
|
||||
F 1 "+5V" H 3850 2800 50 0000 C CNN
|
||||
F 2 "" H 3850 2650 50 0001 C CNN
|
||||
F 3 "" H 3850 2650 50 0001 C CNN
|
||||
1 3850 2650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0119
|
||||
U 1 1 61AAB670
|
||||
P 3850 4150
|
||||
F 0 "#PWR0119" H 3850 4000 50 0001 C CNN
|
||||
F 1 "+5V" H 3850 4300 50 0000 C CNN
|
||||
F 2 "" H 3850 4150 50 0001 C CNN
|
||||
F 3 "" H 3850 4150 50 0001 C CNN
|
||||
1 3850 4150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0120
|
||||
U 1 1 61AAB93D
|
||||
P 9100 1400
|
||||
F 0 "#PWR0120" H 9100 1250 50 0001 C CNN
|
||||
F 1 "+5V" H 9100 1550 50 0000 C CNN
|
||||
F 2 "" H 9100 1400 50 0001 C CNN
|
||||
F 3 "" H 9100 1400 50 0001 C CNN
|
||||
1 9100 1400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR?
|
||||
U 1 1 61AAC271
|
||||
P 9100 3600
|
||||
AR Path="/61AAC271" Ref="#PWR?" Part="1"
|
||||
AR Path="/60D70CB4/61AAC271" Ref="#PWR?" Part="1"
|
||||
AR Path="/5F723900/61AAC271" Ref="#PWR0121" Part="1"
|
||||
F 0 "#PWR0121" H 9100 3450 50 0001 C CNN
|
||||
F 1 "+5V" H 9100 3750 50 0000 C CNN
|
||||
F 2 "" H 9100 3600 50 0001 C CNN
|
||||
F 3 "" H 9100 3600 50 0001 C CNN
|
||||
1 9100 3600
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Bus Line
|
||||
4150 2850 4150 5050
|
||||
Wire Bus Line
|
||||
9500 1700 9500 4600
|
||||
Wire Bus Line
|
||||
2750 2750 2750 5350
|
||||
Wire Bus Line
|
||||
8000 1500 8000 5500
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,698 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# CPLD_Xilinx_XC95144XL-TQ100
|
||||
#
|
||||
DEF CPLD_Xilinx_XC95144XL-TQ100 U 0 20 Y Y 1 F N
|
||||
F0 "U" -800 2550 50 H V C CNN
|
||||
F1 "CPLD_Xilinx_XC95144XL-TQ100" -800 -2550 50 H V C CNN
|
||||
F2 "Package_QFP:TQFP-100_14x14mm_P0.5mm" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
TQFP*14x14mm*P0.5mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -800 2500 800 -2500 1 1 10 f
|
||||
X I/O/GTS3 1 -1000 1100 200 R 50 50 1 1 B
|
||||
X P10 10 -1000 300 200 R 50 50 1 1 B
|
||||
X GND 100 400 -2700 200 U 50 50 1 1 W
|
||||
X P11 11 -1000 2400 200 R 50 50 1 1 B
|
||||
X P12 12 -1000 2300 200 R 50 50 1 1 B
|
||||
X P13 13 -1000 2200 200 R 50 50 1 1 B
|
||||
X P14 14 -1000 2100 200 R 50 50 1 1 B
|
||||
X P15 15 -1000 2000 200 R 50 50 1 1 B
|
||||
X P16 16 -1000 1900 200 R 50 50 1 1 B
|
||||
X P17 17 -1000 1800 200 R 50 50 1 1 B
|
||||
X P18 18 -1000 1700 200 R 50 50 1 1 B
|
||||
X P19 19 -1000 1600 200 R 50 50 1 1 B
|
||||
X I/O/GTS4 2 -1000 1000 200 R 50 50 1 1 B
|
||||
X P20 20 -1000 1500 200 R 50 50 1 1 B
|
||||
X GND 21 -300 -2700 200 U 50 50 1 1 W
|
||||
X I/O/GCK1 22 -1000 1400 200 R 50 50 1 1 B
|
||||
X I/O/GCK2 23 -1000 100 200 R 50 50 1 1 B
|
||||
X P24 24 -1000 0 200 R 50 50 1 1 B
|
||||
X P25 25 -1000 -100 200 R 50 50 1 1 B
|
||||
X VCCIO 26 0 2700 200 D 50 50 1 1 W
|
||||
X I/O/GCK3 27 -1000 -200 200 R 50 50 1 1 B
|
||||
X P28 28 -1000 -300 200 R 50 50 1 1 B
|
||||
X P29 29 -1000 -400 200 R 50 50 1 1 B
|
||||
X I/O/GTS1 3 -1000 900 200 R 50 50 1 1 B
|
||||
X P30 30 -1000 -500 200 R 50 50 1 1 B
|
||||
X GND 31 -200 -2700 200 U 50 50 1 1 W
|
||||
X P32 32 -1000 -600 200 R 50 50 1 1 B
|
||||
X P33 33 -1000 -700 200 R 50 50 1 1 B
|
||||
X P34 34 -1000 -800 200 R 50 50 1 1 B
|
||||
X P35 35 1000 2400 200 L 50 50 1 1 B
|
||||
X P36 36 1000 2300 200 L 50 50 1 1 B
|
||||
X P37 37 1000 2200 200 L 50 50 1 1 B
|
||||
X VCCIO 38 100 2700 200 D 50 50 1 1 W
|
||||
X P39 39 1000 2100 200 L 50 50 1 1 B
|
||||
X I/O/GTS2 4 -1000 800 200 R 50 50 1 1 B
|
||||
X P40 40 1000 2000 200 L 50 50 1 1 B
|
||||
X P41 41 1000 1900 200 L 50 50 1 1 B
|
||||
X P42 42 1000 1800 200 L 50 50 1 1 B
|
||||
X P43 43 1000 1700 200 L 50 50 1 1 B
|
||||
X GND 44 -100 -2700 200 U 50 50 1 1 W
|
||||
X TDI 45 1000 -2100 200 L 50 50 1 1 I
|
||||
X P46 46 1000 1600 200 L 50 50 1 1 B
|
||||
X TMS 47 1000 -2200 200 L 50 50 1 1 I
|
||||
X TCK 48 1000 -2300 200 L 50 50 1 1 I
|
||||
X P49 49 1000 1500 200 L 50 50 1 1 B
|
||||
X VCCINT 5 -300 2700 200 D 50 50 1 1 W
|
||||
X P50 50 1000 100 200 L 50 50 1 1 B
|
||||
X VCCIO 51 200 2700 200 D 50 50 1 1 W
|
||||
X P52 52 1000 0 200 L 50 50 1 1 B
|
||||
X P53 53 1000 -100 200 L 50 50 1 1 B
|
||||
X P54 54 1000 -200 200 L 50 50 1 1 B
|
||||
X P55 55 1000 -300 200 L 50 50 1 1 B
|
||||
X P56 56 1000 -400 200 L 50 50 1 1 B
|
||||
X VCCINT 57 -200 2700 200 D 50 50 1 1 W
|
||||
X P58 58 1000 -500 200 L 50 50 1 1 B
|
||||
X P59 59 1000 -600 200 L 50 50 1 1 B
|
||||
X P6 6 -1000 700 200 R 50 50 1 1 B
|
||||
X P60 60 1000 -700 200 L 50 50 1 1 B
|
||||
X P61 61 1000 -800 200 L 50 50 1 1 B
|
||||
X GND 62 0 -2700 200 U 50 50 1 1 W
|
||||
X P63 63 1000 -1000 200 L 50 50 1 1 B
|
||||
X P64 64 1000 -1100 200 L 50 50 1 1 B
|
||||
X P65 65 1000 -1200 200 L 50 50 1 1 B
|
||||
X P66 66 1000 -1300 200 L 50 50 1 1 B
|
||||
X P67 67 1000 -1400 200 L 50 50 1 1 B
|
||||
X P68 68 1000 -1500 200 L 50 50 1 1 B
|
||||
X GND 69 100 -2700 200 U 50 50 1 1 W
|
||||
X P7 7 -1000 600 200 R 50 50 1 1 B
|
||||
X P70 70 1000 -1600 200 L 50 50 1 1 B
|
||||
X P71 71 1000 -1700 200 L 50 50 1 1 B
|
||||
X P72 72 1000 -1800 200 L 50 50 1 1 B
|
||||
X P73 73 1000 -1900 200 L 50 50 1 1 B
|
||||
X P74 74 1000 1200 200 L 50 50 1 1 B
|
||||
X GND 75 200 -2700 200 U 50 50 1 1 W
|
||||
X P76 76 1000 1100 200 L 50 50 1 1 B
|
||||
X P77 77 1000 1000 200 L 50 50 1 1 B
|
||||
X P78 78 1000 900 200 L 50 50 1 1 B
|
||||
X P79 79 1000 800 200 L 50 50 1 1 B
|
||||
X P8 8 -1000 500 200 R 50 50 1 1 B
|
||||
X P80 80 1000 700 200 L 50 50 1 1 B
|
||||
X P81 81 1000 600 200 L 50 50 1 1 B
|
||||
X P82 82 1000 500 200 L 50 50 1 1 B
|
||||
X TDO 83 1000 -2400 200 L 50 50 1 1 O
|
||||
X GND 84 300 -2700 200 U 50 50 1 1 W
|
||||
X P85 85 1000 400 200 L 50 50 1 1 B
|
||||
X P86 86 1000 300 200 L 50 50 1 1 B
|
||||
X P87 87 -1000 -1000 200 R 50 50 1 1 B
|
||||
X VCCIO 88 300 2700 200 D 50 50 1 1 W
|
||||
X P89 89 -1000 -1100 200 R 50 50 1 1 B
|
||||
X P9 9 -1000 400 200 R 50 50 1 1 B
|
||||
X P90 90 -1000 -1200 200 R 50 50 1 1 B
|
||||
X P91 91 -1000 -1300 200 R 50 50 1 1 B
|
||||
X P92 92 -1000 -1400 200 R 50 50 1 1 B
|
||||
X P93 93 -1000 -1500 200 R 50 50 1 1 B
|
||||
X P94 94 -1000 -1600 200 R 50 50 1 1 B
|
||||
X P95 95 -1000 -1700 200 R 50 50 1 1 B
|
||||
X P96 96 -1000 -1800 200 R 50 50 1 1 B
|
||||
X P97 97 -1000 -1900 200 R 50 50 1 1 B
|
||||
X VCCINT 98 -100 2700 200 D 50 50 1 1 W
|
||||
X I/O/GSR 99 -1000 1200 200 R 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# CPU_NXP_68000_MC68000FN
|
||||
#
|
||||
DEF CPU_NXP_68000_MC68000FN U 0 30 Y Y 1 F N
|
||||
F0 "U" -650 2350 50 H V C CNN
|
||||
F1 "CPU_NXP_68000_MC68000FN" 500 -2350 50 H V C CNN
|
||||
F2 "Package_LCC:PLCC-68" -750 2250 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
PLCC*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -700 2300 700 -2300 0 1 10 f
|
||||
X D4 1 1000 -600 300 L 50 50 1 1 B
|
||||
X DTACK 10 -1000 -700 300 R 50 50 1 1 I I
|
||||
X BG 11 -1000 1400 300 R 50 50 1 1 O I
|
||||
X BGACK 12 -1000 1500 300 R 50 50 1 1 I I
|
||||
X BR 13 -1000 1300 300 R 50 50 1 1 I I
|
||||
X VCC 14 -100 2600 300 D 50 50 1 1 W
|
||||
X CLK 15 -1000 2200 300 R 50 50 1 1 I C
|
||||
X GND 16 100 -2600 300 U 50 50 1 1 W
|
||||
X GND 17 200 -2600 300 U 50 50 1 1 W
|
||||
X NC 18 -700 -1800 0 R 50 50 1 1 N N
|
||||
X HALT 19 -1000 -1200 300 R 50 50 1 1 B I
|
||||
X D3 2 1000 -500 300 L 50 50 1 1 B
|
||||
X RESET 20 -1000 -1400 300 R 50 50 1 1 I I
|
||||
X VMA 21 -1000 500 300 R 50 50 1 1 O I
|
||||
X E 22 -1000 400 300 R 50 50 1 1 O
|
||||
X VPA 23 -1000 300 300 R 50 50 1 1 I I
|
||||
X BERR 24 -1000 -500 300 R 50 50 1 1 I I
|
||||
X IPL2 25 -1000 1700 300 R 50 50 1 1 I I
|
||||
X IPL1 26 -1000 1800 300 R 50 50 1 1 I I
|
||||
X IPL0 27 -1000 1900 300 R 50 50 1 1 I I
|
||||
X FC2 28 -1000 800 300 R 50 50 1 1 O
|
||||
X FC1 29 -1000 900 300 R 50 50 1 1 O
|
||||
X D2 3 1000 -400 300 L 50 50 1 1 B
|
||||
X FC0 30 -1000 1000 300 R 50 50 1 1 O
|
||||
X NC 31 -700 -1900 0 R 50 50 1 1 N N
|
||||
X A1 32 1000 2200 300 L 50 50 1 1 O
|
||||
X A2 33 1000 2100 300 L 50 50 1 1 O
|
||||
X A3 34 1000 2000 300 L 50 50 1 1 O
|
||||
X A4 35 1000 1900 300 L 50 50 1 1 O
|
||||
X A5 36 1000 1800 300 L 50 50 1 1 O
|
||||
X A6 37 1000 1700 300 L 50 50 1 1 O
|
||||
X A7 38 1000 1600 300 L 50 50 1 1 O
|
||||
X A8 39 1000 1500 300 L 50 50 1 1 O
|
||||
X D1 4 1000 -300 300 L 50 50 1 1 B
|
||||
X A9 40 1000 1400 300 L 50 50 1 1 O
|
||||
X A10 41 1000 1300 300 L 50 50 1 1 O
|
||||
X A11 42 1000 1200 300 L 50 50 1 1 O
|
||||
X A12 43 1000 1100 300 L 50 50 1 1 O
|
||||
X A13 44 1000 1000 300 L 50 50 1 1 O
|
||||
X A14 45 1000 900 300 L 50 50 1 1 O
|
||||
X A15 46 1000 800 300 L 50 50 1 1 O
|
||||
X A16 47 1000 700 300 L 50 50 1 1 O
|
||||
X A17 48 1000 600 300 L 50 50 1 1 O
|
||||
X A18 49 1000 500 300 L 50 50 1 1 O
|
||||
X D0 5 1000 -200 300 L 50 50 1 1 B
|
||||
X A19 50 1000 400 300 L 50 50 1 1 O
|
||||
X A20 51 1000 300 300 L 50 50 1 1 O
|
||||
X VCC 52 100 2600 300 D 50 50 1 1 W
|
||||
X A21 53 1000 200 300 L 50 50 1 1 O
|
||||
X A22 54 1000 100 300 L 50 50 1 1 O
|
||||
X A23 55 1000 0 300 L 50 50 1 1 O
|
||||
X GND 56 -100 -2600 300 U 50 50 1 1 W
|
||||
X GND 57 -200 -2600 300 U 50 50 1 1 W
|
||||
X D15 58 1000 -1700 300 L 50 50 1 1 B
|
||||
X D14 59 1000 -1600 300 L 50 50 1 1 B
|
||||
X AS 6 1000 -1900 300 L 50 50 1 1 O I
|
||||
X D13 60 1000 -1500 300 L 50 50 1 1 B
|
||||
X D12 61 1000 -1400 300 L 50 50 1 1 B
|
||||
X D11 62 1000 -1300 300 L 50 50 1 1 B
|
||||
X D10 63 1000 -1200 300 L 50 50 1 1 B
|
||||
X D9 64 1000 -1100 300 L 50 50 1 1 B
|
||||
X D8 65 1000 -1000 300 L 50 50 1 1 B
|
||||
X D7 66 1000 -900 300 L 50 50 1 1 B
|
||||
X D6 67 1000 -800 300 L 50 50 1 1 B
|
||||
X D5 68 1000 -700 300 L 50 50 1 1 B
|
||||
X UDS 7 1000 -2000 300 L 50 50 1 1 O I
|
||||
X LDS 8 1000 -2100 300 L 50 50 1 1 O I
|
||||
X R/W 9 1000 -2200 300 L 50 50 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Connector_Generic_Conn_02x07_Odd_Even
|
||||
#
|
||||
DEF Connector_Generic_Conn_02x07_Odd_Even J 0 40 Y N 1 F N
|
||||
F0 "J" 50 400 50 H V C CNN
|
||||
F1 "Connector_Generic_Conn_02x07_Odd_Even" 50 -400 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Connector*:*_2x??_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -50 -295 0 -305 1 1 6 N
|
||||
S -50 -195 0 -205 1 1 6 N
|
||||
S -50 -95 0 -105 1 1 6 N
|
||||
S -50 5 0 -5 1 1 6 N
|
||||
S -50 105 0 95 1 1 6 N
|
||||
S -50 205 0 195 1 1 6 N
|
||||
S -50 305 0 295 1 1 6 N
|
||||
S -50 350 150 -350 1 1 10 f
|
||||
S 150 -295 100 -305 1 1 6 N
|
||||
S 150 -195 100 -205 1 1 6 N
|
||||
S 150 -95 100 -105 1 1 6 N
|
||||
S 150 5 100 -5 1 1 6 N
|
||||
S 150 105 100 95 1 1 6 N
|
||||
S 150 205 100 195 1 1 6 N
|
||||
S 150 305 100 295 1 1 6 N
|
||||
X Pin_1 1 -200 300 150 R 50 50 1 1 P
|
||||
X Pin_10 10 300 -100 150 L 50 50 1 1 P
|
||||
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
|
||||
X Pin_12 12 300 -200 150 L 50 50 1 1 P
|
||||
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
|
||||
X Pin_14 14 300 -300 150 L 50 50 1 1 P
|
||||
X Pin_2 2 300 300 150 L 50 50 1 1 P
|
||||
X Pin_3 3 -200 200 150 R 50 50 1 1 P
|
||||
X Pin_4 4 300 200 150 L 50 50 1 1 P
|
||||
X Pin_5 5 -200 100 150 R 50 50 1 1 P
|
||||
X Pin_6 6 300 100 150 L 50 50 1 1 P
|
||||
X Pin_7 7 -200 0 150 R 50 50 1 1 P
|
||||
X Pin_8 8 300 0 150 L 50 50 1 1 P
|
||||
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_C_Small
|
||||
#
|
||||
DEF Device_C_Small C 0 10 N N 1 F N
|
||||
F0 "C" 10 70 50 H V L CNN
|
||||
F1 "Device_C_Small" 10 -80 50 H V L CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
C_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 13 -60 -20 60 -20 N
|
||||
P 2 0 1 12 -60 20 60 20 N
|
||||
X ~ 1 0 100 80 D 50 50 1 1 P
|
||||
X ~ 2 0 -100 80 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_R_Small
|
||||
#
|
||||
DEF Device_R_Small R 0 10 N N 1 F N
|
||||
F0 "R" 30 20 50 H V L CNN
|
||||
F1 "Device_R_Small" 30 -40 50 H V L CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -30 70 30 -70 0 1 8 N
|
||||
X ~ 1 0 100 30 D 50 50 1 1 P
|
||||
X ~ 2 0 -100 30 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GW_Connector_MacSEPDS
|
||||
#
|
||||
DEF GW_Connector_MacSEPDS J 0 40 Y Y 3 L N
|
||||
F0 "J" 0 1800 50 H V C CNN
|
||||
F1 "GW_Connector_MacSEPDS" 0 -1600 50 H V C CNN
|
||||
F2 "" 0 1800 50 H I C CNN
|
||||
F3 "" 0 1800 50 H I C CNN
|
||||
DRAW
|
||||
S 0 1750 -400 -1550 0 1 10 f
|
||||
X FC2 A1 150 1650 150 L 50 50 1 1 U
|
||||
X A7 A10 150 750 150 L 50 50 1 1 U
|
||||
X A8 A11 150 650 150 L 50 50 1 1 U
|
||||
X A9 A12 150 550 150 L 50 50 1 1 U
|
||||
X A10 A13 150 450 150 L 50 50 1 1 U
|
||||
X A11 A14 150 350 150 L 50 50 1 1 U
|
||||
X A12 A15 150 250 150 L 50 50 1 1 U
|
||||
X A13 A16 150 150 150 L 50 50 1 1 U
|
||||
X A14 A17 150 50 150 L 50 50 1 1 U
|
||||
X A15 A18 150 -50 150 L 50 50 1 1 U
|
||||
X A16 A19 150 -150 150 L 50 50 1 1 U
|
||||
X FC1 A2 150 1550 150 L 50 50 1 1 U
|
||||
X A17 A20 150 -250 150 L 50 50 1 1 U
|
||||
X A18 A21 150 -350 150 L 50 50 1 1 U
|
||||
X A19 A22 150 -450 150 L 50 50 1 1 U
|
||||
X A20 A23 150 -550 150 L 50 50 1 1 U
|
||||
X A21 A24 150 -650 150 L 50 50 1 1 U
|
||||
X A22 A25 150 -750 150 L 50 50 1 1 U
|
||||
X A23 A26 150 -850 150 L 50 50 1 1 U
|
||||
X E A27 150 -950 150 L 50 50 1 1 U
|
||||
X C8M A28 150 -1050 150 L 50 50 1 1 U
|
||||
X C16M A29 150 -1150 150 L 50 50 1 1 U
|
||||
X FC0 A3 150 1450 150 L 50 50 1 1 U
|
||||
X GND A30 150 -1250 150 L 50 50 1 1 U
|
||||
X +12V A31 150 -1350 150 L 50 50 1 1 U
|
||||
X +12V A32 150 -1450 150 L 50 50 1 1 U
|
||||
X A1 A4 150 1350 150 L 50 50 1 1 U
|
||||
X A2 A5 150 1250 150 L 50 50 1 1 U
|
||||
X A3 A6 150 1150 150 L 50 50 1 1 U
|
||||
X A4 A7 150 1050 150 L 50 50 1 1 U
|
||||
X A5 A8 150 950 150 L 50 50 1 1 U
|
||||
X A6 A9 150 850 150 L 50 50 1 1 U
|
||||
X GND B1 150 1650 150 L 50 50 2 1 U
|
||||
X NC B10 150 750 150 L 50 50 2 1 U
|
||||
X NC B11 150 650 150 L 50 50 2 1 U
|
||||
X ~HALT~ B12 150 550 150 L 50 50 2 1 U
|
||||
X +5V B13 150 450 150 L 50 50 2 1 U
|
||||
X +5V B14 150 350 150 L 50 50 2 1 U
|
||||
X +5V B15 150 250 150 L 50 50 2 1 U
|
||||
X +5V B16 150 150 150 L 50 50 2 1 U
|
||||
X +5V B17 150 50 150 L 50 50 2 1 U
|
||||
X ~IPL~0 B18 150 -50 150 L 50 50 2 1 U
|
||||
X ~IPL~1 B19 150 -150 150 L 50 50 2 1 U
|
||||
X GND B2 150 1550 150 L 50 50 2 1 U
|
||||
X ~IPL~2 B20 150 -250 150 L 50 50 2 1 U
|
||||
X ~BERR~ B21 150 -350 150 L 50 50 2 1 U
|
||||
X NC B22 150 -450 150 L 50 50 2 1 U
|
||||
X NC B23 150 -550 150 L 50 50 2 1 U
|
||||
X NC B24 150 -650 150 L 50 50 2 1 U
|
||||
X NC B25 150 -750 150 L 50 50 2 1 U
|
||||
X NC B26 150 -850 150 L 50 50 2 1 U
|
||||
X NC B27 150 -950 150 L 50 50 2 1 U
|
||||
X ~EXT.DTK~ B28 150 -1050 150 L 50 50 2 1 U
|
||||
X GND B29 150 -1150 150 L 50 50 2 1 U
|
||||
X GND B3 150 1450 150 L 50 50 2 1 U
|
||||
X +12V B30 150 -1250 150 L 50 50 2 1 U
|
||||
X +12V B31 150 -1350 150 L 50 50 2 1 U
|
||||
X -5V B32 150 -1450 150 L 50 50 2 1 U
|
||||
X GND B4 150 1350 150 L 50 50 2 1 U
|
||||
X GND B5 150 1250 150 L 50 50 2 1 U
|
||||
X GND B6 150 1150 150 L 50 50 2 1 U
|
||||
X GND B7 150 1050 150 L 50 50 2 1 U
|
||||
X GND B8 150 950 150 L 50 50 2 1 U
|
||||
X GND B9 150 850 150 L 50 50 2 1 U
|
||||
X ~VPA~ C1 150 1650 150 L 50 50 3 1 U
|
||||
X ~AS~ C10 150 750 150 L 50 50 3 1 U
|
||||
X ~PMCYC~ C11 150 650 150 L 50 50 3 1 U
|
||||
X ~RESET~ C12 150 550 150 L 50 50 3 1 U
|
||||
X +5V C13 150 450 150 L 50 50 3 1 U
|
||||
X D0 C14 150 350 150 L 50 50 3 1 U
|
||||
X D1 C15 150 250 150 L 50 50 3 1 U
|
||||
X D2 C16 150 150 150 L 50 50 3 1 U
|
||||
X D3 C17 150 50 150 L 50 50 3 1 U
|
||||
X D4 C18 150 -50 150 L 50 50 3 1 U
|
||||
X D5 C19 150 -150 150 L 50 50 3 1 U
|
||||
X ~VMA~ C2 150 1550 150 L 50 50 3 1 U
|
||||
X D6 C20 150 -250 150 L 50 50 3 1 U
|
||||
X D7 C21 150 -350 150 L 50 50 3 1 U
|
||||
X D8 C22 150 -450 150 L 50 50 3 1 U
|
||||
X D9 C23 150 -550 150 L 50 50 3 1 U
|
||||
X D10 C24 150 -650 150 L 50 50 3 1 U
|
||||
X D11 C25 150 -750 150 L 50 50 3 1 U
|
||||
X D12 C26 150 -850 150 L 50 50 3 1 U
|
||||
X D13 C27 150 -950 150 L 50 50 3 1 U
|
||||
X D14 C28 150 -1050 150 L 50 50 3 1 U
|
||||
X D15 C29 150 -1150 150 L 50 50 3 1 U
|
||||
X ~BR~ C3 150 1450 150 L 50 50 3 1 U
|
||||
X GND C30 150 -1250 150 L 50 50 3 1 U
|
||||
X NC C31 150 -1350 150 L 50 50 3 1 U
|
||||
X -12V C32 150 -1450 150 L 50 50 3 1 U
|
||||
X ~BGACK~ C4 150 1350 150 L 50 50 3 1 U
|
||||
X ~BG~ C5 150 1250 150 L 50 50 3 1 U
|
||||
X ~DTACK~ C6 150 1150 150 L 50 50 3 1 U
|
||||
X R~W~ C7 150 1050 150 L 50 50 3 1 U
|
||||
X ~LDS~ C8 150 950 150 L 50 50 3 1 U
|
||||
X ~UDS~ C9 150 850 150 L 50 50 3 1 U
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GW_Logic_74573
|
||||
#
|
||||
DEF GW_Logic_74573 U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 600 50 H V C CNN
|
||||
F1 "GW_Logic_74573" 0 -600 50 H V C CNN
|
||||
F2 "" 0 -650 50 H I C TNN
|
||||
F3 "" 0 100 60 H I C CNN
|
||||
DRAW
|
||||
S -200 550 200 -550 0 1 10 f
|
||||
X ~OE~ 1 -400 450 200 R 50 50 1 1 I
|
||||
X GND 10 -400 -450 200 R 50 50 1 1 W
|
||||
X ~LE~ 11 400 -450 200 L 50 50 1 1 I
|
||||
X Q7 12 400 -350 200 L 50 50 1 1 T
|
||||
X Q6 13 400 -250 200 L 50 50 1 1 T
|
||||
X Q5 14 400 -150 200 L 50 50 1 1 T
|
||||
X Q4 15 400 -50 200 L 50 50 1 1 T
|
||||
X Q3 16 400 50 200 L 50 50 1 1 T
|
||||
X Q2 17 400 150 200 L 50 50 1 1 T
|
||||
X Q1 18 400 250 200 L 50 50 1 1 T
|
||||
X Q0 19 400 350 200 L 50 50 1 1 T
|
||||
X D0 2 -400 350 200 R 50 50 1 1 I
|
||||
X Vcc 20 400 450 200 L 50 50 1 1 W
|
||||
X D1 3 -400 250 200 R 50 50 1 1 I
|
||||
X D2 4 -400 150 200 R 50 50 1 1 I
|
||||
X D3 5 -400 50 200 R 50 50 1 1 I
|
||||
X D4 6 -400 -50 200 R 50 50 1 1 I
|
||||
X D5 7 -400 -150 200 R 50 50 1 1 I
|
||||
X D6 8 -400 -250 200 R 50 50 1 1 I
|
||||
X D7 9 -400 -350 200 R 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GW_Logic_Oscillator_4P
|
||||
#
|
||||
DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 250 50 H V C CNN
|
||||
F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -250 200 250 -100 0 1 10 f
|
||||
X EN 1 -350 100 100 R 50 50 1 1 I
|
||||
X GND 2 -350 0 100 R 50 50 1 1 W
|
||||
X Output 3 350 0 100 L 50 50 1 1 O
|
||||
X Vdd 4 350 100 100 L 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GW_Power_AZ1117CH2
|
||||
#
|
||||
DEF GW_Power_AZ1117CH2 U 0 10 Y Y 1 F N
|
||||
F0 "U" -150 125 50 H V C CNN
|
||||
F1 "GW_Power_AZ1117CH2" 0 125 50 H V L CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN
|
||||
F3 "" 100 -250 50 H I C CNN
|
||||
$FPLIST
|
||||
SOT?223*TabPin2*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 -200 200 75 0 1 10 f
|
||||
X VI 1 -300 0 100 R 50 50 1 1 W
|
||||
X GND 2 0 -300 100 U 50 50 1 1 W
|
||||
X VO 3 300 0 100 L 50 50 1 1 w
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GW_RAM_DRAM-2Mx8-SOP-28
|
||||
#
|
||||
DEF GW_RAM_DRAM-2Mx8-SOP-28 U 0 20 Y Y 1 F N
|
||||
F0 "U" 0 750 50 H V C CNN
|
||||
F1 "GW_RAM_DRAM-2Mx8-SOP-28" 0 0 50 V V C CNN
|
||||
F2 "stdpads:SOP-24-26-300mil" 0 -850 50 H I C CNN
|
||||
F3 "" 0 -550 50 H I C CNN
|
||||
DRAW
|
||||
S -300 700 300 -700 0 1 10 f
|
||||
X VDD 1 400 600 100 L 50 50 1 1 W
|
||||
X A0 10 -400 600 100 R 50 50 1 1 I
|
||||
X A1 11 -400 500 100 R 50 50 1 1 I
|
||||
X A2 12 -400 400 100 R 50 50 1 1 I
|
||||
X A3 13 -400 300 100 R 50 50 1 1 I
|
||||
X VDD 14 400 600 100 L 50 50 1 1 W N
|
||||
X GND 15 -400 -600 100 R 50 50 1 1 W N
|
||||
X A4 16 -400 200 100 R 50 50 1 1 I
|
||||
X A5 17 -400 100 100 R 50 50 1 1 I
|
||||
X A6 18 -400 0 100 R 50 50 1 1 I
|
||||
X A7 19 -400 -100 100 R 50 50 1 1 I
|
||||
X I/O0 2 400 500 100 L 50 50 1 1 B
|
||||
X A8 20 -400 -200 100 R 50 50 1 1 I
|
||||
X A9 21 -400 -300 100 R 50 50 1 1 I
|
||||
X ~OE~ 22 400 -600 100 L 50 50 1 1 I
|
||||
X ~CAS~ 23 400 -300 100 L 50 50 1 1 I
|
||||
X I/O4 24 400 100 100 L 50 50 1 1 B
|
||||
X I/O5 25 400 0 100 L 50 50 1 1 B
|
||||
X I/O6 26 400 -100 100 L 50 50 1 1 B
|
||||
X I/O7 27 400 -200 100 L 50 50 1 1 B
|
||||
X GND 28 -400 -600 100 R 50 50 1 1 W
|
||||
X I/O1 3 400 400 100 L 50 50 1 1 B
|
||||
X I/O2 4 400 300 100 L 50 50 1 1 B
|
||||
X I/O3 5 400 200 100 L 50 50 1 1 B
|
||||
X ~WE~ 6 400 -500 100 L 50 50 1 1 I
|
||||
X ~RAS~ 7 400 -400 100 L 50 50 1 1 I
|
||||
X A11/NC 8 -400 -500 100 R 50 50 1 1 I
|
||||
X A10 9 -400 -400 100 R 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GW_RAM_Flash-512Kx8-PLCC-32
|
||||
#
|
||||
DEF GW_RAM_Flash-512Kx8-PLCC-32 U 0 20 Y Y 1 F N
|
||||
F0 "U" 0 1050 50 H V C CNN
|
||||
F1 "GW_RAM_Flash-512Kx8-PLCC-32" 0 0 50 V V C CNN
|
||||
F2 "stdpads:PLCC-32_SMDSocket" 0 -1050 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -300 1000 300 -1000 0 1 10 f
|
||||
X GND 16 400 -900 100 L 50 50 0 0 W
|
||||
X VCC 32 400 900 100 L 50 50 0 0 W
|
||||
X A18 1 -400 -900 100 R 50 50 1 1 I
|
||||
X A2 10 -400 700 100 R 50 50 1 1 I
|
||||
X A1 11 -400 800 100 R 50 50 1 1 I
|
||||
X A0 12 -400 900 100 R 50 50 1 1 I
|
||||
X D0 13 400 700 100 L 50 50 1 1 B
|
||||
X D1 14 400 600 100 L 50 50 1 1 B
|
||||
X D2 15 400 500 100 L 50 50 1 1 B
|
||||
X D3 17 400 400 100 L 50 50 1 1 B
|
||||
X D4 18 400 300 100 L 50 50 1 1 B
|
||||
X D5 19 400 200 100 L 50 50 1 1 B
|
||||
X A16 2 -400 -700 100 R 50 50 1 1 I
|
||||
X D6 20 400 100 100 L 50 50 1 1 B
|
||||
X D7 21 400 0 100 L 50 50 1 1 B
|
||||
X ~CS~ 22 400 -400 100 L 50 50 1 1 I
|
||||
X A10 23 -400 -100 100 R 50 50 1 1 I
|
||||
X ~OE~ 24 400 -600 100 L 50 50 1 1 I
|
||||
X A11 25 -400 -200 100 R 50 50 1 1 I
|
||||
X A9 26 -400 0 100 R 50 50 1 1 I
|
||||
X A8 27 -400 100 100 R 50 50 1 1 I
|
||||
X A13 28 -400 -400 100 R 50 50 1 1 I
|
||||
X A14 29 -400 -500 100 R 50 50 1 1 I
|
||||
X A15 3 -400 -600 100 R 50 50 1 1 I
|
||||
X A17 30 -400 -800 100 R 50 50 1 1 I
|
||||
X ~WE~ 31 400 -500 100 L 50 50 1 1 I
|
||||
X A12 4 -400 -300 100 R 50 50 1 1 I
|
||||
X A7 5 -400 200 100 R 50 50 1 1 I
|
||||
X A6 6 -400 300 100 R 50 50 1 1 I
|
||||
X A5 7 -400 400 100 R 50 50 1 1 I
|
||||
X A4 8 -400 500 100 R 50 50 1 1 I
|
||||
X A3 9 -400 600 100 R 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Mechanical_Fiducial
|
||||
#
|
||||
DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
|
||||
F0 "FID" 0 200 50 H V C CNN
|
||||
F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Fiducial*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 0 0 50 0 1 20 f
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Mechanical_MountingHole_Pad
|
||||
#
|
||||
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
|
||||
F0 "H" 0 250 50 H V C CNN
|
||||
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
MountingHole*Pad*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 0 50 50 0 1 50 N
|
||||
X 1 1 0 -100 100 U 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Regulator_Linear_AP1117-33
|
||||
#
|
||||
DEF Regulator_Linear_AP1117-33 U 0 10 Y Y 1 F N
|
||||
F0 "U" -150 125 50 H V C CNN
|
||||
F1 "Regulator_Linear_AP1117-33" 0 125 50 H V L CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN
|
||||
F3 "" 100 -250 50 H I C CNN
|
||||
ALIAS AP1117-18 AP1117-25 AP1117-33 AP1117-50 LD1117S33TR_SOT223 LD1117S12TR_SOT223 LD1117S18TR_SOT223 LD1117S25TR_SOT223 LD1117S50TR_SOT223 NCP1117-12_SOT223 NCP1117-1.5_SOT223 NCP1117-1.8_SOT223 NCP1117-2.0_SOT223 NCP1117-2.5_SOT223 NCP1117-2.85_SOT223 NCP1117-3.3_SOT223 NCP1117-5.0_SOT223 AMS1117-1.5 AMS1117-1.8 AMS1117-2.5 AMS1117-2.85 AMS1117-3.3 AMS1117-5.0
|
||||
$FPLIST
|
||||
SOT?223*TabPin2*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 -200 200 75 0 1 10 f
|
||||
X GND 1 0 -300 100 U 50 50 1 1 W
|
||||
X VO 2 300 0 100 L 50 50 1 1 w
|
||||
X VI 3 -300 0 100 R 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Switch_SW_DIP_x02
|
||||
#
|
||||
DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
|
||||
F0 "SW" 0 250 50 H V C CNN
|
||||
F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
SW?DIP?x2*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C -80 0 20 0 0 0 N
|
||||
C -80 100 20 0 0 0 N
|
||||
C 80 0 20 0 0 0 N
|
||||
C 80 100 20 0 0 0 N
|
||||
S -150 200 150 -100 0 1 10 f
|
||||
P 2 0 0 0 -60 5 93 46 N
|
||||
P 2 0 0 0 -60 105 93 146 N
|
||||
X ~ 1 -300 100 200 R 50 50 1 1 P
|
||||
X ~ 2 -300 0 200 R 50 50 1 1 P
|
||||
X ~ 3 300 0 200 L 50 50 1 1 P
|
||||
X ~ 4 300 100 200 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+12V
|
||||
#
|
||||
DEF power_+12V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+12V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +12V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+3V3
|
||||
#
|
||||
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+3V3" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS +3.3V
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +3V3 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+5V
|
||||
#
|
||||
DEF power_+5V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+5V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +5V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_-12V
|
||||
#
|
||||
DEF power_-12V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 100 50 H I C CNN
|
||||
F1 "power_-12V" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
|
||||
X -12V 1 0 0 0 U 50 50 0 0 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_-5V
|
||||
#
|
||||
DEF power_-5V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 100 50 H I C CNN
|
||||
F1 "power_-5V" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
|
||||
X -5V 1 0 0 0 U 50 50 0 0 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GND
|
||||
#
|
||||
DEF power_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GND" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,268 @@
|
|||
update=Friday, September 10, 2021 at 08:57:31 AM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=SE-030.net
|
||||
CopperLayerCount=4
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.15
|
||||
MinViaDiameter=0.5
|
||||
MinViaDrill=0.2
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.15
|
||||
TrackWidth2=0.2
|
||||
TrackWidth3=0.25
|
||||
TrackWidth4=0.3
|
||||
TrackWidth5=0.35
|
||||
TrackWidth6=0.4
|
||||
TrackWidth7=0.45
|
||||
TrackWidth8=0.5
|
||||
TrackWidth9=0.6
|
||||
TrackWidth10=0.8
|
||||
TrackWidth11=1
|
||||
TrackWidth12=1.27
|
||||
TrackWidth13=1.524
|
||||
ViaDiameter1=0.5
|
||||
ViaDrill1=0.2
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
ViaDiameter3=0.8
|
||||
ViaDrill3=0.4
|
||||
ViaDiameter4=1
|
||||
ViaDrill4=0.5
|
||||
ViaDiameter5=1.524
|
||||
ViaDrill5=0.762
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.1524
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.15
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.07619999999999999
|
||||
SolderMaskMinWidth=0.09999999999999999
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.15
|
||||
TrackWidth=0.15
|
||||
ViaDiameter=0.5
|
||||
ViaDrill=0.2
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
|
|
@ -0,0 +1,481 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr USLetter 11000 8500
|
||||
encoding utf-8
|
||||
Sheet 1 10
|
||||
Title "RAM2E II"
|
||||
Date "2020-07-25"
|
||||
Rev "1.0"
|
||||
Comp "Garrett's Workshop"
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Mechanical:MountingHole_Pad H5
|
||||
U 1 1 5ED15A93
|
||||
P 2200 6850
|
||||
F 0 "H5" H 2300 6901 50 0000 L CNN
|
||||
F 1 " " H 2300 6810 50 0000 L CNN
|
||||
F 2 "stdpads:PasteHole_1.1mm_PTH" H 2200 6850 50 0001 C CNN
|
||||
F 3 "~" H 2200 6850 50 0001 C CNN
|
||||
1 2200 6850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:Fiducial FID1
|
||||
U 1 1 5CC47A28
|
||||
P 1000 7150
|
||||
F 0 "FID1" H 1100 7196 50 0000 L CNN
|
||||
F 1 "Fiducial" H 1100 7105 50 0000 L CNN
|
||||
F 2 "stdpads:Fiducial" H 1000 7150 50 0001 C CNN
|
||||
F 3 "~" H 1000 7150 50 0001 C CNN
|
||||
1 1000 7150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:Fiducial FID2
|
||||
U 1 1 5CC4921D
|
||||
P 1500 7150
|
||||
F 0 "FID2" H 1600 7196 50 0000 L CNN
|
||||
F 1 "Fiducial" H 1600 7105 50 0000 L CNN
|
||||
F 2 "stdpads:Fiducial" H 1500 7150 50 0001 C CNN
|
||||
F 3 "~" H 1500 7150 50 0001 C CNN
|
||||
1 1500 7150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:Fiducial FID3
|
||||
U 1 1 5CC4DBD8
|
||||
P 1000 7350
|
||||
F 0 "FID3" H 1100 7396 50 0000 L CNN
|
||||
F 1 "Fiducial" H 1100 7305 50 0000 L CNN
|
||||
F 2 "stdpads:Fiducial" H 1000 7350 50 0001 C CNN
|
||||
F 3 "~" H 1000 7350 50 0001 C CNN
|
||||
1 1000 7350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:Fiducial FID4
|
||||
U 1 1 5CC4DBDF
|
||||
P 1500 7350
|
||||
F 0 "FID4" H 1600 7396 50 0000 L CNN
|
||||
F 1 "Fiducial" H 1600 7305 50 0000 L CNN
|
||||
F 2 "stdpads:Fiducial" H 1500 7350 50 0001 C CNN
|
||||
F 3 "~" H 1500 7350 50 0001 C CNN
|
||||
1 1500 7350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:MountingHole_Pad H1
|
||||
U 1 1 5CC53461
|
||||
P 1000 6850
|
||||
F 0 "H1" H 1100 6901 50 0000 L CNN
|
||||
F 1 " " H 1100 6810 50 0000 L CNN
|
||||
F 2 "stdpads:PasteHole_1.1mm_PTH" H 1000 6850 50 0001 C CNN
|
||||
F 3 "~" H 1000 6850 50 0001 C CNN
|
||||
1 1000 6850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:MountingHole_Pad H2
|
||||
U 1 1 5CC795A2
|
||||
P 1300 6850
|
||||
F 0 "H2" H 1400 6901 50 0000 L CNN
|
||||
F 1 " " H 1400 6810 50 0000 L CNN
|
||||
F 2 "stdpads:PasteHole_1.1mm_PTH" H 1300 6850 50 0001 C CNN
|
||||
F 3 "~" H 1300 6850 50 0001 C CNN
|
||||
1 1300 6850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:MountingHole_Pad H3
|
||||
U 1 1 5CC7E0B9
|
||||
P 1600 6850
|
||||
F 0 "H3" H 1700 6901 50 0000 L CNN
|
||||
F 1 " " H 1700 6810 50 0000 L CNN
|
||||
F 2 "stdpads:PasteHole_1.1mm_PTH" H 1600 6850 50 0001 C CNN
|
||||
F 3 "~" H 1600 6850 50 0001 C CNN
|
||||
1 1600 6850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Mechanical:MountingHole_Pad H4
|
||||
U 1 1 5CC7E0C0
|
||||
P 1900 6850
|
||||
F 0 "H4" H 2000 6901 50 0000 L CNN
|
||||
F 1 " " H 2000 6810 50 0000 L CNN
|
||||
F 2 "stdpads:PasteHole_1.1mm_PTH" H 1900 6850 50 0001 C CNN
|
||||
F 3 "~" H 1900 6850 50 0001 C CNN
|
||||
1 1900 6850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0132
|
||||
U 1 1 5CC8BAFD
|
||||
P 1900 6950
|
||||
F 0 "#PWR0132" H 1900 6700 50 0001 C CNN
|
||||
F 1 "GND" H 1905 6777 50 0000 C CNN
|
||||
F 2 "" H 1900 6950 50 0001 C CNN
|
||||
F 3 "" H 1900 6950 50 0001 C CNN
|
||||
1 1900 6950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1300 6950 1000 6950
|
||||
Connection ~ 1300 6950
|
||||
Connection ~ 1600 6950
|
||||
Wire Wire Line
|
||||
1600 6950 1300 6950
|
||||
Wire Wire Line
|
||||
2200 6950 1900 6950
|
||||
Wire Wire Line
|
||||
1900 6950 1600 6950
|
||||
Connection ~ 1900 6950
|
||||
Wire Wire Line
|
||||
4600 2800 4200 2800
|
||||
Wire Wire Line
|
||||
4700 2900 4200 2900
|
||||
Wire Wire Line
|
||||
4800 3000 4200 3000
|
||||
Wire Wire Line
|
||||
4900 3100 4200 3100
|
||||
Wire Wire Line
|
||||
5100 3300 4200 3300
|
||||
Wire Wire Line
|
||||
2900 2800 3200 2800
|
||||
Wire Bus Line
|
||||
2800 2700 3200 2700
|
||||
Wire Bus Line
|
||||
2800 2700 2700 2700
|
||||
Wire Wire Line
|
||||
2900 2800 2700 2800
|
||||
Wire Bus Line
|
||||
3000 2900 2700 2900
|
||||
Wire Wire Line
|
||||
2700 3000 3200 3000
|
||||
Wire Wire Line
|
||||
2700 3100 3200 3100
|
||||
Wire Wire Line
|
||||
2700 3200 3200 3200
|
||||
Wire Wire Line
|
||||
2700 3300 3200 3300
|
||||
Connection ~ 3100 1600
|
||||
Connection ~ 2800 2700
|
||||
Connection ~ 2900 2800
|
||||
Wire Wire Line
|
||||
3100 2900 3200 2900
|
||||
Wire Wire Line
|
||||
2700 3400 3200 3400
|
||||
Wire Wire Line
|
||||
2700 3500 3200 3500
|
||||
Wire Wire Line
|
||||
5000 3200 4200 3200
|
||||
Wire Bus Line
|
||||
4200 4700 4500 4700
|
||||
Wire Wire Line
|
||||
4200 4500 4500 4500
|
||||
Wire Wire Line
|
||||
4200 4600 4500 4600
|
||||
Wire Wire Line
|
||||
4200 4300 4500 4300
|
||||
Wire Wire Line
|
||||
4200 4400 4500 4400
|
||||
Wire Wire Line
|
||||
4200 4100 4500 4100
|
||||
Wire Wire Line
|
||||
4200 4200 4500 4200
|
||||
Wire Bus Line
|
||||
4400 3800 4500 3800
|
||||
Wire Bus Line
|
||||
4500 3900 4300 3900
|
||||
Wire Bus Line
|
||||
4300 2450 3000 2450
|
||||
Wire Bus Line
|
||||
3000 2450 3000 2900
|
||||
Wire Wire Line
|
||||
4200 2700 4500 2700
|
||||
Wire Bus Line
|
||||
3000 1400 3000 2450
|
||||
Connection ~ 3000 2450
|
||||
Wire Wire Line
|
||||
4600 1900 4600 2800
|
||||
Wire Wire Line
|
||||
4700 1700 4700 2900
|
||||
Wire Wire Line
|
||||
4800 1600 4800 3000
|
||||
Wire Wire Line
|
||||
4900 1400 4900 3100
|
||||
Wire Wire Line
|
||||
5000 1300 5000 3200
|
||||
Wire Wire Line
|
||||
5100 1100 5100 3300
|
||||
$Sheet
|
||||
S 4500 3700 550 1100
|
||||
U 5F723900
|
||||
F0 "RAMROM" 50
|
||||
F1 "RAMROM.sch" 50
|
||||
F2 "~RAS~" I L 4500 4500 50
|
||||
F3 "D[15..0]" B L 4500 3900 50
|
||||
F4 "~CAS~" I L 4500 4600 50
|
||||
F5 "~OE~" I L 4500 4200 50
|
||||
F6 "RA[11..0]" I L 4500 4700 50
|
||||
F7 "L~WE~" I L 4500 4300 50
|
||||
F8 "U~WE~" I L 4500 4400 50
|
||||
F9 "ROM~CS~" I L 4500 4000 50
|
||||
F10 "A[23..1]" I L 4500 3800 50
|
||||
F11 "ROM~WE~" I L 4500 4100 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1700 2600 1000 1000
|
||||
U 60941922
|
||||
F0 "Buf" 50
|
||||
F1 "Buf.sch" 50
|
||||
F2 "AccA[23..1]" B R 2700 2700 50
|
||||
F3 "MacA[23..1]" B L 1700 2800 50
|
||||
F4 "AccD[15..0]" B R 2700 2900 50
|
||||
F5 "MacD[15..0]" B L 1700 3100 50
|
||||
F6 "Dout~OE~" I R 2700 3100 50
|
||||
F7 "Din~OE~" I R 2700 3200 50
|
||||
F8 "DinLE" I R 2700 3500 50
|
||||
F9 "Aout~OE~" I R 2700 3000 50
|
||||
F10 "Mac~R~W" T L 1700 2900 50
|
||||
F11 "Acc~R~W" I R 2700 2800 50
|
||||
F12 "ADoutLE0" I R 2700 3300 50
|
||||
F13 "ADoutLE1" I R 2700 3400 50
|
||||
$EndSheet
|
||||
Wire Bus Line
|
||||
4300 2450 4300 3900
|
||||
Wire Wire Line
|
||||
2900 1200 2900 2800
|
||||
NoConn ~ 4200 3800
|
||||
Wire Wire Line
|
||||
1600 4400 3200 4400
|
||||
Wire Wire Line
|
||||
1600 4500 3200 4500
|
||||
Wire Wire Line
|
||||
1600 4600 3200 4600
|
||||
Wire Wire Line
|
||||
1600 4300 3200 4300
|
||||
Wire Wire Line
|
||||
1600 1600 3100 1600
|
||||
Wire Wire Line
|
||||
1600 4100 3200 4100
|
||||
Wire Wire Line
|
||||
1600 4200 3200 4200
|
||||
Wire Wire Line
|
||||
1600 3800 3200 3800
|
||||
Wire Wire Line
|
||||
1600 2900 1700 2900
|
||||
Wire Wire Line
|
||||
1600 4000 3200 4000
|
||||
Wire Wire Line
|
||||
1600 3900 3200 3900
|
||||
Wire Wire Line
|
||||
1600 3700 3200 3700
|
||||
Wire Bus Line
|
||||
1600 3100 1700 3100
|
||||
Wire Bus Line
|
||||
1600 2800 1700 2800
|
||||
$Sheet
|
||||
S 1050 1100 550 3700
|
||||
U 5F6DA71D
|
||||
F0 "PDS" 50
|
||||
F1 "PDS.sch" 50
|
||||
F2 "A[23..1]" B R 1600 2800 50
|
||||
F3 "D[15..0]" B R 1600 3100 50
|
||||
F4 "~AS~" B R 1600 3700 50
|
||||
F5 "~LDS~" B R 1600 3900 50
|
||||
F6 "~UDS~" B R 1600 4000 50
|
||||
F7 "R~W~" B R 1600 2900 50
|
||||
F8 "~VMA~" B R 1600 3800 50
|
||||
F9 "~VPA~" O R 1600 4200 50
|
||||
F10 "~DTACK~" O R 1600 4100 50
|
||||
F11 "~RESET~" B R 1600 1600 50
|
||||
F12 "~IPL~0" O R 1600 1900 50
|
||||
F13 "~IPL~1" O R 1600 2000 50
|
||||
F14 "~IPL~2" O R 1600 2100 50
|
||||
F15 "~BERR~" O R 1600 4300 50
|
||||
F16 "E" O R 1600 4600 50
|
||||
F17 "C8M" O R 1600 4500 50
|
||||
F18 "C16M" O R 1600 4400 50
|
||||
$EndSheet
|
||||
Wire Wire Line
|
||||
4500 2100 4200 2100
|
||||
Wire Wire Line
|
||||
1600 2100 3200 2100
|
||||
Wire Wire Line
|
||||
1600 2000 3200 2000
|
||||
Wire Wire Line
|
||||
1600 1900 3200 1900
|
||||
Wire Wire Line
|
||||
4200 1900 4600 1900
|
||||
Wire Wire Line
|
||||
3100 1600 3200 1600
|
||||
Wire Wire Line
|
||||
4200 1700 4700 1700
|
||||
Wire Wire Line
|
||||
4200 1600 4800 1600
|
||||
Wire Wire Line
|
||||
4200 1300 5000 1300
|
||||
Wire Wire Line
|
||||
4200 1400 4900 1400
|
||||
Wire Wire Line
|
||||
2900 1200 3200 1200
|
||||
Wire Wire Line
|
||||
4200 1100 5100 1100
|
||||
Wire Bus Line
|
||||
3200 1400 3000 1400
|
||||
Wire Bus Line
|
||||
3200 1100 2800 1100
|
||||
$Sheet
|
||||
S 3200 1000 1000 1200
|
||||
U 5F72F108
|
||||
F0 "MC68k" 50
|
||||
F1 "MC68k.sch" 50
|
||||
F2 "A[23..1]" O L 3200 1100 50
|
||||
F3 "D[15..0]" B L 3200 1400 50
|
||||
F4 "~AS~" O R 4200 1100 50
|
||||
F5 "R~W~" O L 3200 1200 50
|
||||
F6 "~LDS~" O R 4200 1400 50
|
||||
F7 "~UDS~" O R 4200 1300 50
|
||||
F8 "~DTACK~" I R 4200 1600 50
|
||||
F9 "~VPA~" I R 4200 1700 50
|
||||
F10 "~RESET~" B L 3200 1600 50
|
||||
F11 "~BERR~" I R 4200 1900 50
|
||||
F12 "~IPL~0" I L 3200 1900 50
|
||||
F13 "~IPL~1" I L 3200 2000 50
|
||||
F14 "~IPL~2" I L 3200 2100 50
|
||||
F15 "CLK" I R 4200 2100 50
|
||||
$EndSheet
|
||||
Wire Bus Line
|
||||
4400 2350 4400 3800
|
||||
Connection ~ 2800 2350
|
||||
Wire Bus Line
|
||||
2800 1100 2800 2350
|
||||
Wire Bus Line
|
||||
2800 2350 2800 2700
|
||||
Wire Bus Line
|
||||
2800 2350 4400 2350
|
||||
Wire Wire Line
|
||||
3100 1600 3100 2900
|
||||
Wire Wire Line
|
||||
4500 2450 4500 2700
|
||||
Wire Wire Line
|
||||
4500 2100 4500 2350
|
||||
Wire Wire Line
|
||||
4200 4000 4500 4000
|
||||
$Sheet
|
||||
S 5400 3400 550 300
|
||||
U 61A87B62
|
||||
F0 "DIPSW" 50
|
||||
F1 "DIPSW.sch" 50
|
||||
F2 "SW0" O L 5400 3500 50
|
||||
F3 "SW1" O L 5400 3600 50
|
||||
$EndSheet
|
||||
Wire Wire Line
|
||||
5400 3500 5300 3500
|
||||
Connection ~ 5300 3500
|
||||
Wire Wire Line
|
||||
5300 3500 4200 3500
|
||||
Wire Wire Line
|
||||
5400 3600 4200 3600
|
||||
$Sheet
|
||||
S 3200 2600 1000 2700
|
||||
U 5F723173
|
||||
F0 "Control" 50
|
||||
F1 "Control.sch" 50
|
||||
F2 "~RESET~" I L 3200 2900 50
|
||||
F3 "FCLK" I R 4200 2700 50
|
||||
F4 "Mac~AS~" O L 3200 3700 50
|
||||
F5 "Mac~VMA~" O L 3200 3800 50
|
||||
F6 "Mac~DTACK~" I L 3200 4100 50
|
||||
F7 "Mac~VPA~" I L 3200 4200 50
|
||||
F8 "Mac~BERR~" I L 3200 4300 50
|
||||
F9 "MacE" I L 3200 4600 50
|
||||
F10 "C8M" I L 3200 4500 50
|
||||
F11 "C16M" I L 3200 4400 50
|
||||
F12 "Acc~DTACK" O R 4200 3000 50
|
||||
F13 "Acc~BERR~" O R 4200 2800 50
|
||||
F14 "Acc~UDS~" I R 4200 3200 50
|
||||
F15 "Acc~LDS~" I R 4200 3100 50
|
||||
F16 "Acc~AS~" I R 4200 3300 50
|
||||
F17 "~OE~" O R 4200 4200 50
|
||||
F18 "Mac~UDS~" O L 3200 4000 50
|
||||
F19 "Mac~LDS~" O L 3200 3900 50
|
||||
F20 "Acc~VPA~" O R 4200 2900 50
|
||||
F21 "AccR~W~" I L 3200 2800 50
|
||||
F22 "L~WE~" O R 4200 4300 50
|
||||
F23 "U~WE~" O R 4200 4400 50
|
||||
F24 "~RAS~" O R 4200 4500 50
|
||||
F25 "~CAS~" O R 4200 4600 50
|
||||
F26 "ROM~CS~" O R 4200 4000 50
|
||||
F27 "DinLE" O L 3200 3500 50
|
||||
F28 "Dout~OE~" O L 3200 3100 50
|
||||
F29 "Aout~OE~" O L 3200 3000 50
|
||||
F30 "Din~OE~" O L 3200 3200 50
|
||||
F31 "RA[11..0]" O R 4200 4700 50
|
||||
F32 "A[23..1]" I L 3200 2700 50
|
||||
F33 "ADoutLE0" O L 3200 3300 50
|
||||
F34 "~RESET~r" O R 4200 3800 50
|
||||
F35 "ADoutLE1" O L 3200 3400 50
|
||||
F36 "ROM~WE~" O R 4200 4100 50
|
||||
F37 "SW0" I R 4200 3500 50
|
||||
F38 "SW1" I R 4200 3600 50
|
||||
F39 "CKEN" O R 4200 3400 50
|
||||
F40 "TDI" I R 4200 5000 50
|
||||
F41 "TMS" I R 4200 5100 50
|
||||
F42 "TCK" I R 4200 4900 50
|
||||
F43 "TDO" O R 4200 5200 50
|
||||
$EndSheet
|
||||
Wire Wire Line
|
||||
4200 3400 5200 3400
|
||||
Wire Wire Line
|
||||
5200 3400 5200 2550
|
||||
Wire Wire Line
|
||||
5300 2650 5300 3500
|
||||
$Sheet
|
||||
S 5400 4800 550 500
|
||||
U 61B15767
|
||||
F0 "JTAG" 50
|
||||
F1 "JTAG.sch" 50
|
||||
F2 "TCK" O L 5400 4900 50
|
||||
F3 "TDI" O L 5400 5000 50
|
||||
F4 "TMS" O L 5400 5100 50
|
||||
F5 "TDO" I L 5400 5200 50
|
||||
$EndSheet
|
||||
Wire Wire Line
|
||||
5400 4900 4200 4900
|
||||
Wire Wire Line
|
||||
4200 5000 5400 5000
|
||||
Wire Wire Line
|
||||
5400 5100 4200 5100
|
||||
Wire Wire Line
|
||||
4200 5200 5400 5200
|
||||
$Sheet
|
||||
S 1050 5000 550 200
|
||||
U 61B3A5F1
|
||||
F0 "Power" 50
|
||||
F1 "Power.sch" 50
|
||||
$EndSheet
|
||||
Wire Wire Line
|
||||
5200 2550 5400 2550
|
||||
Wire Wire Line
|
||||
5400 2650 5300 2650
|
||||
Wire Wire Line
|
||||
4500 2450 5400 2450
|
||||
Wire Wire Line
|
||||
4500 2350 5400 2350
|
||||
$Sheet
|
||||
S 5400 2250 550 500
|
||||
U 61350D21
|
||||
F0 "Clk.sch" 50
|
||||
F1 "Clk.sch" 50
|
||||
F2 "MCLK" O L 5400 2350 50
|
||||
F3 "RCLK" O L 5400 2450 50
|
||||
F4 "CK20EN" I L 5400 2650 50
|
||||
F5 "CK25EN" I L 5400 2550 50
|
||||
$EndSheet
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
module CNT(
|
||||
/* FSB clock and AS detection */
|
||||
input FCLK, input CACT,
|
||||
/* Refresh request */
|
||||
output RefReq, output RefUrgent, input RefAck,
|
||||
/* Timeout signals */
|
||||
output reg TimeoutA, output reg TimeoutB);
|
||||
|
||||
/* Refresh counter */
|
||||
reg [7:0] RefCnt = 0;
|
||||
reg RefDone = 0;
|
||||
assign RefReq = ~RefDone;
|
||||
assign RefUrgent = RefCnt[7] && RefCnt[6] && RefCnt[5] && ~RefDone;
|
||||
always @(posedge FCLK) begin
|
||||
RefCnt <= RefCnt+1;
|
||||
if (RefCnt==0) RefDone <= 0;
|
||||
else if (RefAck) RefDone <= 1;
|
||||
end
|
||||
|
||||
/* Timeout signals */
|
||||
always @(posedge FCLK) begin
|
||||
if (~CACT) begin
|
||||
TimeoutA <= 0;
|
||||
TimeoutB <= 0;
|
||||
end else begin
|
||||
if (RefCnt==0) TimeoutA <= 1;
|
||||
if (RefCnt==0 && TimeoutA) TimeoutB <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
module CS(
|
||||
/* MC68HC000 interface */
|
||||
input [23:08] A, input CLK, input nRES, input nWE,
|
||||
/* AS cycle detection */
|
||||
input BACT,
|
||||
/* Device select outputs */
|
||||
output IOCS, output SCSICS, output IOPWCS, output IACS, output ROMCS, output RAMCS, output SndRAMCSWR);
|
||||
|
||||
/* Overlay control */
|
||||
reg nOverlay0 = 0;
|
||||
reg nOverlay1 = 0;
|
||||
wire Overlay = ~nOverlay1;
|
||||
wire ODCS = A[23:20]==4'h4; // Disable overlay
|
||||
always @(posedge CLK, negedge nRES) begin
|
||||
if (~nRES) nOverlay0 <= 0;
|
||||
else if (BACT && ODCS) nOverlay0 <= 1;
|
||||
end
|
||||
always @(posedge CLK) begin
|
||||
if (~BACT) nOverlay1 <= nOverlay0;
|
||||
end
|
||||
|
||||
/* Select signals - FSB domain */
|
||||
wire RAMCS_OverlayOff = A[23:22]==2'b00;
|
||||
wire RAMCS_OverlayOn = A[23:21]==3'b011;
|
||||
assign RAMCS = (RAMCS_OverlayOff && ~Overlay) || // 000000-3FFFFF when overlay disabled
|
||||
(RAMCS_OverlayOn && Overlay); // 600000-7FFFFF when overlay enabled
|
||||
wire VidRAMCSWR64k = RAMCS && A[21:20]==2'h3 && A[19:16]==4'hF && ~nWE; // 3F0000-3FFFFF / 7F0000-7FFFFF
|
||||
wire VidRAMCSWR = VidRAMCSWR64k && (
|
||||
(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video
|
||||
(A[15:12]==4'h3) || // 4096 bytes video
|
||||
(A[15:12]==4'h4) || // 4096 bytes video
|
||||
(A[15:12]==4'h5) || // 4096 bytes video
|
||||
(A[15:12]==4'h6) || // 4096 bytes video
|
||||
(A[15:12]==4'h7) || // 3200 bytes video, 896 bytes RAM,
|
||||
(A[15:12]==4'hA) || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
|
||||
(A[15:12]==4'hB) || // 4096 bytes video
|
||||
(A[15:12]==4'hC) || // 4096 bytes video
|
||||
(A[15:12]==4'hD) || // 4096 bytes video
|
||||
(A[15:12]==4'hE) || // 4096 bytes video
|
||||
(A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
|
||||
assign SndRAMCSWR = VidRAMCSWR64k && (
|
||||
(A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
|
||||
(A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
|
||||
|
||||
assign ROMCS = A[23:20]==4'h4 || (A[23:20]==4'h0 && Overlay);
|
||||
|
||||
/* Select signals - IOB domain */
|
||||
assign IACS = A[23:08]==16'hFFFF; // IACK
|
||||
assign IOCS = A[23:20]==4'h5 || // SCSI
|
||||
A[23:20]==4'h8 || // empty
|
||||
A[23:20]==4'h9 || // SCC read/reset
|
||||
A[23:20]==4'hA || // empty
|
||||
A[23:20]==4'hB || // SCC write
|
||||
A[23:20]==4'hC || // empty
|
||||
A[23:20]==4'hD || // IWM
|
||||
A[23:20]==4'hE || // VIA
|
||||
A[23:20]==4'hF || // IACK
|
||||
VidRAMCSWR;
|
||||
assign SCSICS = A[23:20]==4'h5; // SCSI
|
||||
assign IOPWCS = RAMCS_OverlayOff && ~nWE;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
module FSB(
|
||||
/* MC68HC000 interface */
|
||||
input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR,
|
||||
/* AS cycle detection */
|
||||
output BACT,
|
||||
/* Ready inputs */
|
||||
input Ready0, input Ready1, input Ready2,
|
||||
/* BERR inputs */
|
||||
input BERR0, input BERR1,
|
||||
/* Interrupt acknowledge select */
|
||||
input IACS);
|
||||
|
||||
/* AS cycle detection */
|
||||
reg ASrf = 0;
|
||||
always @(negedge FCLK) begin ASrf <= ~nAS; end
|
||||
assign BACT = ~nAS || ASrf;
|
||||
|
||||
/* Ready and BERR "remember" */
|
||||
reg Ready0r, Ready1r, Ready2r;
|
||||
reg BERR0r, BERR1r;
|
||||
wire Ready = (Ready0 || Ready0r) &&
|
||||
(Ready1 || Ready1r) &&
|
||||
(Ready2 || Ready2r);
|
||||
wire BERR = (BERR0 || BERR0r || BERR1 || BERR1r);
|
||||
assign nBERR = ~(~nAS && BERR);
|
||||
always @(posedge FCLK) begin
|
||||
if (~BACT) begin
|
||||
Ready0r <= 0;
|
||||
Ready1r <= 0;
|
||||
Ready2r <= 0;
|
||||
BERR0r <= 0;
|
||||
BERR1r <= 0;
|
||||
end else begin
|
||||
if (Ready0) Ready0r <= 1;
|
||||
if (Ready1) Ready1r <= 1;
|
||||
if (Ready2) Ready2r <= 1;
|
||||
if (BERR0) BERR0r <= 1;
|
||||
if (BERR1) BERR1r <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
/* DTACK/VPA control */
|
||||
reg VPA;
|
||||
assign nVPA = ~(~nAS && VPA);
|
||||
always @(posedge FCLK) begin
|
||||
if (~BACT) begin
|
||||
nDTACK <= 1;
|
||||
VPA <= 0;
|
||||
end else if (Ready && ~BERR) begin
|
||||
nDTACK <= IACS;
|
||||
VPA <= IACS;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
module IOBM(
|
||||
/* PDS interface */
|
||||
input C16M, input C8M, input E,
|
||||
output reg nAS, output reg nLDS, output reg nUDS, output reg nVMA,
|
||||
input nDTACK, input nVPA, input nBERR, input nRES,
|
||||
/* PDS address and data latch control */
|
||||
output nAoutOE, output reg nDoutOE, output reg ALE0, output reg nDinLE,
|
||||
/* IO bus slave port interface */
|
||||
output reg IOACT, output reg IOBERR, input IOREQ, input IOLDS, input IOUDS, input IOWE);
|
||||
|
||||
/* I/O bus slave port input synchronization */
|
||||
reg IOREQr = 0;
|
||||
always @(negedge C16M) begin IOREQr <= IOREQ; end
|
||||
|
||||
/* DTACK, BERR, RESET synchronization */
|
||||
reg DTACKrr, DTACKrf, VPArr, VPArf, BERRrr, BERRrf, RESrr, RESrf;
|
||||
always @(posedge C16M) begin
|
||||
DTACKrr <= ~nDTACK;
|
||||
VPArr <= ~nVPA;
|
||||
BERRrr <= ~nBERR;
|
||||
RESrr <= ~nRES;
|
||||
end
|
||||
always @(negedge C16M) begin
|
||||
DTACKrf <= ~nDTACK;
|
||||
VPArf <= ~nVPA;
|
||||
BERRrf <= ~nBERR;
|
||||
RESrf <= ~nRES;
|
||||
end
|
||||
wire DTACK = DTACKrr && DTACKrf;
|
||||
wire BERR = BERRrr && BERRrf;
|
||||
wire VPA = VPArr && VPArf;
|
||||
wire RES = RESrr && RESrf;
|
||||
|
||||
/* E clock state */
|
||||
reg [4:0] ES;
|
||||
reg Er;
|
||||
reg Er2;
|
||||
always @(negedge C8M) begin Er <= E; end
|
||||
always @(posedge C16M) begin Er2 <= Er; end
|
||||
always @(posedge C16M) begin
|
||||
if (Er2 && ~Er) ES <= 1;
|
||||
else if (ES==0 || ES==19) ES <= 0;
|
||||
else ES <= ES+1;
|
||||
end
|
||||
|
||||
/* ETACK and VMA generation */
|
||||
reg ETACK = 0;
|
||||
always @(posedge C16M) begin ETACK <= ES==16 && ~nVMA; end
|
||||
always @(posedge C16M) begin
|
||||
if (ES==7 && IOACT && VPA) nVMA <= 0;
|
||||
else if (ES==0) nVMA <= 1;
|
||||
end
|
||||
|
||||
/* I/O bus state */
|
||||
reg [2:0] IOS = 0;
|
||||
always @(posedge C16M) begin
|
||||
if (IOS==0) begin
|
||||
if (IOREQr) begin
|
||||
if (~C8M) begin
|
||||
IOS <= 1;
|
||||
end else begin
|
||||
IOS <= 0;
|
||||
end
|
||||
IOACT <= 1;
|
||||
ALE0 <= 1;
|
||||
end else begin
|
||||
IOS <= 0;
|
||||
IOACT <= 0;
|
||||
ALE0 <= 0;
|
||||
end
|
||||
end else if (IOS==1) begin
|
||||
IOS <= 2;
|
||||
IOACT <= 1;
|
||||
ALE0 <= 1;
|
||||
end else if (IOS==2) begin
|
||||
IOS <= 3;
|
||||
IOACT <= 1;
|
||||
ALE0 <= 1;
|
||||
end else if (IOS==3) begin
|
||||
IOS <= 4;
|
||||
IOACT <= 1;
|
||||
ALE0 <= 1;
|
||||
end else if (IOS==4) begin
|
||||
IOS <= 5;
|
||||
IOACT <= 1;
|
||||
ALE0 <= 1;
|
||||
end else if (IOS==5) begin
|
||||
if (C8M && (DTACK || ETACK || BERR || RES)) begin
|
||||
IOS <= 6;
|
||||
IOACT <= 0;
|
||||
IOBERR <= ~nBERR;
|
||||
end else begin
|
||||
IOS <= 5;
|
||||
IOACT <= 1;
|
||||
end
|
||||
ALE0 <= 1;
|
||||
end else if (IOS==6) begin
|
||||
IOS <= 7;
|
||||
IOACT <= 0;
|
||||
ALE0 <= 0;
|
||||
end else if (IOS==7) begin
|
||||
IOS <= 0;
|
||||
IOACT <= 0;
|
||||
ALE0 <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
/* PDS address and data latch control */
|
||||
assign nAoutOE = 0;
|
||||
always @(negedge C16M) begin nDinLE <= IOS==4 || IOS==5; end
|
||||
always @(posedge C16M) begin
|
||||
nDoutOE <= ~(IOWE && (IOS==1 || IOS==2 || IOS==3 ||
|
||||
IOS==4 || IOS==5 || IOS==6));
|
||||
end
|
||||
|
||||
/* AS, DS control */
|
||||
always @(negedge C16M) begin
|
||||
nAS <= ~(IOS==1 || IOS==2 || IOS==3 || IOS==4 || IOS==5);
|
||||
nLDS <= ~(IOLDS && (((IOS==1 || IOS==2) && ~IOWE) || IOS==3 || IOS==4 || IOS==5));
|
||||
nUDS <= ~(IOUDS && (((IOS==1 || IOS==2) && ~IOWE) || IOS==3 || IOS==4 || IOS==5));
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
module IOBS(
|
||||
/* MC68HC000 interface */
|
||||
input CLK, input nWE, input nAS, input nLDS, input nUDS,
|
||||
/* AS cycle detection */
|
||||
input BACT,
|
||||
/* Select and ready signals */
|
||||
input IOCS, input IOPWCS, output Ready, output reg BERR,
|
||||
/* Read data OE control */
|
||||
output nDinOE,
|
||||
/* IOB Master Controller Interface */
|
||||
output reg IOREQ, input IOACT, input IOBERR,
|
||||
/* FIFO primary level control */
|
||||
output reg ALE0, output reg IORW0, output reg IOL0, output reg IOU0,
|
||||
/* FIFO secondary level control */
|
||||
output reg ALE1);
|
||||
|
||||
/* IOACT input synchronization */
|
||||
reg IOACTr = 0;
|
||||
always @(posedge CLK) begin IOACTr <= IOACT; end
|
||||
|
||||
/* Read data OE control */
|
||||
assign nDinOE = ~nAS && IOCS && nWE;
|
||||
|
||||
/* Posted read/write state */
|
||||
reg [1:0] PS = 0;
|
||||
reg Once = 0;
|
||||
|
||||
/* FIFO second level control */
|
||||
reg Load1;
|
||||
reg IORW1;
|
||||
reg IOL1;
|
||||
reg IOU1;
|
||||
always @(posedge CLK) begin
|
||||
if (PS!=0 && BACT && IOCS && ~Once && ~ALE1) begin
|
||||
ALE1 <= 1;
|
||||
IORW1 <= nWE;
|
||||
Load1 <= 1;
|
||||
end else begin
|
||||
if (PS==3) ALE1 <= 0;
|
||||
Load1 <= 0;
|
||||
end
|
||||
end
|
||||
always @(posedge CLK) begin
|
||||
if (Load1) begin
|
||||
IOL1 <= ~nLDS;
|
||||
IOU1 <= ~nUDS;
|
||||
end
|
||||
end
|
||||
|
||||
/* FIFO Primary Level Control */
|
||||
always @(posedge CLK) begin
|
||||
if (PS==0) begin
|
||||
if (ALE1) begin
|
||||
PS <= 3;
|
||||
IOREQ <= 1;
|
||||
IORW0 <= IORW1;
|
||||
end else if (BACT && IOCS && ~Once) begin
|
||||
PS <= 3;
|
||||
IOREQ <= 1;
|
||||
IORW0 <= nWE;
|
||||
end else begin
|
||||
PS <= 0;
|
||||
IOREQ <= 0;
|
||||
end
|
||||
ALE0 <= 0;
|
||||
end else if (PS==3) begin
|
||||
PS <= 2;
|
||||
IOREQ <= 1;
|
||||
ALE0 <= 1;
|
||||
if (ALE1) begin
|
||||
IOL0 <= IOL1;
|
||||
IOU0 <= IOU1;
|
||||
end else begin
|
||||
IOL0 <= ~nLDS;
|
||||
IOU0 <= ~nUDS;
|
||||
end
|
||||
end else if (PS==2) begin
|
||||
if (IOACTr) begin
|
||||
PS <= 1;
|
||||
IOREQ <= 0;
|
||||
end else begin
|
||||
PS <= 2;
|
||||
IOREQ <= 1;
|
||||
end
|
||||
ALE0 <= 0;
|
||||
end else if (PS==1) begin
|
||||
if (~IOACTr) PS <= 0;
|
||||
else PS <= 2;
|
||||
IOREQ <= 0;
|
||||
ALE0 <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
/* Once, ready, BERR control */
|
||||
reg IOReady;
|
||||
wire IOPWReady = ~ALE1;
|
||||
always @(posedge CLK) begin
|
||||
if (~BACT) Once <= 0;
|
||||
else if (IOCS && (PS==0 || (IOPWCS && IOPWReady))) Once <= 1;
|
||||
end
|
||||
always @(posedge CLK) begin
|
||||
if (~BACT) begin
|
||||
IOReady <= 0;
|
||||
BERR <= 0;
|
||||
end else if (Once && (PS==0 || PS==1) && ~IOACTr && IOPWReady) begin
|
||||
IOReady <= ~IOBERR;
|
||||
BERR <= IOBERR;
|
||||
end
|
||||
end
|
||||
assign Ready = ~IOCS || IOReady || (IOPWCS && IOPWReady);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
|
||||
#Created by Constraints Editor (xc95144xl-tq100-10) - 2021/10/07
|
||||
INST "A_FSB<1>" TNM = A_FSB;
|
||||
INST "A_FSB<2>" TNM = A_FSB;
|
||||
INST "A_FSB<3>" TNM = A_FSB;
|
||||
INST "A_FSB<4>" TNM = A_FSB;
|
||||
INST "A_FSB<5>" TNM = A_FSB;
|
||||
INST "A_FSB<6>" TNM = A_FSB;
|
||||
INST "A_FSB<7>" TNM = A_FSB;
|
||||
INST "A_FSB<8>" TNM = A_FSB;
|
||||
INST "A_FSB<9>" TNM = A_FSB;
|
||||
INST "A_FSB<10>" TNM = A_FSB;
|
||||
INST "A_FSB<11>" TNM = A_FSB;
|
||||
INST "A_FSB<12>" TNM = A_FSB;
|
||||
INST "A_FSB<13>" TNM = A_FSB;
|
||||
INST "A_FSB<14>" TNM = A_FSB;
|
||||
INST "A_FSB<15>" TNM = A_FSB;
|
||||
INST "A_FSB<16>" TNM = A_FSB;
|
||||
INST "A_FSB<17>" TNM = A_FSB;
|
||||
INST "A_FSB<18>" TNM = A_FSB;
|
||||
INST "A_FSB<19>" TNM = A_FSB;
|
||||
INST "A_FSB<20>" TNM = A_FSB;
|
||||
INST "A_FSB<21>" TNM = A_FSB;
|
||||
INST "A_FSB<22>" TNM = A_FSB;
|
||||
INST "A_FSB<23>" TNM = A_FSB;
|
||||
#Created by Constraints Editor (xc95144xl-tq100-10) - 2021/10/07
|
||||
NET "CLK_FSB" TNM_NET = CLK_FSB;
|
||||
TIMESPEC TS_CLK_FSB = PERIOD "CLK_FSB" 40 ns HIGH 50%;
|
||||
NET "CLK2X_IOB" TNM_NET = CLK2X_IOB;
|
||||
TIMESPEC TS_CLK2X_IOB = PERIOD "CLK2X_IOB" 15.6672 MHz HIGH 50%;
|
||||
NET "CLK_IOB" TNM_NET = CLK_IOB;
|
||||
TIMESPEC TS_CLK_IOB = PERIOD "CLK_IOB" 7.8336 MHz HIGH 50%;
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
module MXSE(
|
||||
input [23:1] A_FSB,
|
||||
input nAS_FSB,
|
||||
input nLDS_FSB,
|
||||
input nUDS_FSB,
|
||||
input nWE_FSB,
|
||||
output nDTACK_FSB,
|
||||
output nVPA_FSB,
|
||||
output nBERR_FSB,
|
||||
input CLK_FSB,
|
||||
input CLK2X_IOB,
|
||||
input CLK_IOB,
|
||||
input E_IOB,
|
||||
input nDTACK_IOB,
|
||||
input nVPA_IOB,
|
||||
output nVMA_IOB,
|
||||
output nAS_IOB,
|
||||
output nUDS_IOB,
|
||||
output nLDS_IOB,
|
||||
input nBERR_IOB,
|
||||
input nRES,
|
||||
output nROMCS,
|
||||
output nRAMLWE,
|
||||
output nRAMUWE,
|
||||
output nROMWE,
|
||||
output nRAS,
|
||||
output nCAS,
|
||||
output [11:0] RA,
|
||||
output nOE,
|
||||
output nADoutLE0,
|
||||
output nADoutLE1,
|
||||
output nAoutOE,
|
||||
output nDoutOE,
|
||||
output nDinOE,
|
||||
output nDinLE);
|
||||
|
||||
/* AS cycle detection */
|
||||
wire BACT;
|
||||
|
||||
/* Refresh request/ack signals */
|
||||
wire RefReq, RefUrgent, RefAck;
|
||||
|
||||
wire IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR;
|
||||
CS cs(
|
||||
/* MC68HC000 interface */
|
||||
A_FSB[23:08], CLK_FSB, nRES, nWE_FSB,
|
||||
/* AS cycle detection */
|
||||
BACT,
|
||||
/* Device select outputs */
|
||||
IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR);
|
||||
|
||||
wire Ready_RAM;
|
||||
RAM ram(
|
||||
/* MC68HC000 interface */
|
||||
CLK_FSB, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
|
||||
/* AS cycle detection */
|
||||
BACT,
|
||||
/* Select and ready signals */
|
||||
RAMCS, ROMCS, Ready_RAM,
|
||||
/* Refresh Counter Interface */
|
||||
RefReq, RefUrgent, RefAck,
|
||||
/* DRAM and NOR flash interface */
|
||||
RA[11:0], nRAS, nCAS,
|
||||
nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
|
||||
|
||||
wire Ready_IOBS, BERR_IOBS;
|
||||
wire IOREQ, IOACT, IOBERR;
|
||||
wire ALE0S, ALE0M, ALE1;
|
||||
assign nADoutLE0 = ~(ALE0S || ALE0M);
|
||||
assign nADoutLE1 = ~ALE1;
|
||||
wire IORW0, IOL0, IOU0;
|
||||
IOBS iobs(
|
||||
/* MC68HC000 interface */
|
||||
CLK_FSB, nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
|
||||
/* AS cycle detection, FSB BERR */
|
||||
BACT,
|
||||
/* Select and ready signals */
|
||||
IOCS, IOPWCS, Ready_IOBS, BERR_IOBS,
|
||||
/* Read data OE control */
|
||||
nDinOE,
|
||||
/* IOB Master Controller Interface */
|
||||
IOREQ, IOACT, IOBERR,
|
||||
/* FIFO primary level control */
|
||||
ALE0S, IORW0, IOL0, IOU0,
|
||||
/* FIFO secondary level control */
|
||||
ALE1);
|
||||
|
||||
IOBM iobm(
|
||||
/* PDS interface */
|
||||
CLK2X_IOB, CLK_IOB, E_IOB,
|
||||
nAS_IOB, nLDS_IOB, nUDS_IOB, nVMA_IOB,
|
||||
nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRES,
|
||||
/* PDS address and data latch control */
|
||||
nAoutOE, nDoutOE, ALE0M, nDinLE,
|
||||
/* IO bus slave port interface */
|
||||
IOACT, IOBERR, IOREQ, IOL0, IOU0, IORW0);
|
||||
|
||||
wire TimeoutA, TimeoutB;
|
||||
CNT cnt(
|
||||
/* FSB clock and AS detection */
|
||||
CLK_FSB, BACT,
|
||||
/* Refresh request */
|
||||
RefReq, RefUrgent, RefAck,
|
||||
/* Timeout signals */
|
||||
TimeoutA, TimeoutB);
|
||||
|
||||
FSB fsb(
|
||||
/* MC68HC000 interface */
|
||||
CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB,
|
||||
/* AS cycle detection */
|
||||
BACT,
|
||||
/* Ready and IA inputs */
|
||||
Ready_RAM, Ready_IOBS, ~(SndRAMCSWR && ~TimeoutA),
|
||||
/* BERR inputs */
|
||||
(~SCSICS && TimeoutB), BERR_IOBS,
|
||||
/* Interrupt acknowledge select */
|
||||
IACS);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
module RAM(
|
||||
/* MC68HC000 interface */
|
||||
input CLK, input [21:1] A, input nWE, input nAS, input nLDS, input nUDS,
|
||||
/* AS cycle detection */
|
||||
input BACT,
|
||||
/* Select and ready signals */
|
||||
input RAMCS, input ROMCS, output Ready,
|
||||
/* Refresh Counter Interface */
|
||||
input RefReq, input RefUrgent, output RefAck,
|
||||
/* DRAM and NOR flash interface */
|
||||
output [11:0] RA, output nRAS, output reg nCAS,
|
||||
output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
|
||||
|
||||
/* RAM control state */
|
||||
reg [2:0] RS = 0;
|
||||
reg Once = 0;
|
||||
reg RAMReady = 0;
|
||||
reg RASEL = 0; // RASEL controls /CAS signal
|
||||
|
||||
/* Refresh state */
|
||||
reg RAMDIS1 = 0;
|
||||
reg RAMDIS2 = 0;
|
||||
wire RAMDIS = RAMDIS1 || RAMDIS2;
|
||||
wire RAMEN = ~RAMDIS;
|
||||
reg RefRAS = 0;
|
||||
|
||||
assign nROMCS = ~ROMCS;
|
||||
assign nRAS = ~((~nAS && RAMCS && RAMEN && ~RefRAS /* does this add loading to these P-terms? */) || RefRAS);
|
||||
assign nOE = ~(~nAS && nWE);
|
||||
assign nLWE = ~(~nAS && ~nWE && ~nLDS && RAMEN);
|
||||
assign nUWE = ~(~nAS && ~nWE && ~nUDS && RAMEN);
|
||||
assign nROMWE = ~(~nAS && ~nWE);
|
||||
|
||||
assign RA[11] = A[19];
|
||||
assign RA[10] = A[21];
|
||||
assign RA[9:0] = RASEL ? {A[20], A[09:01]} : {A[19], A[18:10]};
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (~BACT) Once <= 0;
|
||||
else if (RS==0 && BACT && RAMCS) Once <= 1;
|
||||
end
|
||||
always @(posedge CLK) begin
|
||||
if (~BACT) RAMDIS2 <= 0;
|
||||
else if ((RS==0 && BACT && RefUrgent && Once && RAMCS) ||
|
||||
(RS==7 && BACT && RefUrgent && Once)) RAMDIS2 <= 1;
|
||||
end
|
||||
reg BACTr;
|
||||
always @(posedge CLK) begin BACTr <= BACT; end
|
||||
always @(posedge CLK) begin
|
||||
if (RS==0) begin
|
||||
if (( BACT && RefReq && ~RAMCS && ~BACTr) || // Non-urgent refresh can start during first clock of non-RAM cycle
|
||||
(~BACT && RefUrgent) || // Urgent refresh can start during bus idle
|
||||
( BACT && RefUrgent && ~RAMCS)) begin // Urgent refresh can start during non-ram cycle
|
||||
RS <= 2;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 1;
|
||||
RAMDIS1 <= 1;
|
||||
end else if (BACT && RAMCS && ~Once) begin
|
||||
// RAM access cycle has priority over urgent refresh if RAM access already begun
|
||||
RS <= 5;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 1;
|
||||
RAMDIS1 <= 0;
|
||||
end else if (BACT && RAMCS && RefUrgent) begin
|
||||
// Urgent refresh can start during prolonged RAM access cycle
|
||||
// But we must insert one extra precharge state first.
|
||||
RS <= 1;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
end else begin
|
||||
// No RAM access/refresh requests pending
|
||||
RS <= 0;
|
||||
RAMReady <= 1;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 0;
|
||||
end
|
||||
RefRAS <= 0;
|
||||
end else if (RS==1) begin
|
||||
RS <= 2;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 1;
|
||||
RAMDIS1 <= 1;
|
||||
RefRAS <= 0;
|
||||
end else if (RS==2) begin
|
||||
RS <= 3;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 1;
|
||||
RAMDIS1 <= 1;
|
||||
RefRAS <= 1;
|
||||
end else if (RS==3) begin
|
||||
RS <= 4;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
RefRAS <= 1;
|
||||
end else if (RS==4) begin
|
||||
RS <= 7;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
RefRAS <= 0;
|
||||
end else if (RS==5) begin
|
||||
RS <= 6;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 1;
|
||||
RAMDIS1 <= 0;
|
||||
RefRAS <= 0;
|
||||
end else if (RS==6) begin
|
||||
RS <= 7;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 0;
|
||||
RefRAS <= 0;
|
||||
end else if (RS==7) begin
|
||||
if (~BACT && RefUrgent) begin
|
||||
RS <= 2;
|
||||
RAMReady <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
RASEL <= 1;
|
||||
end else if (BACT && RefUrgent) begin
|
||||
RS <= 1;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
end else begin
|
||||
RS <= 0;
|
||||
RAMReady <= 1;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 0;
|
||||
end
|
||||
RefRAS <= 0;
|
||||
end
|
||||
end
|
||||
always @(negedge CLK) begin nCAS <= ~RASEL; end
|
||||
|
||||
assign RefAck = RefRAS;
|
||||
|
||||
assign Ready = ~RAMCS || RAMReady;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
module VGA(
|
||||
input VCLK,
|
||||
input [23:1] A,
|
||||
input RnW,
|
||||
input [15:0] D,
|
||||
input nAS,
|
||||
input nLDS,
|
||||
input nUDS,
|
||||
inout [7:0] RD,
|
||||
output reg [14:0] RA,
|
||||
output reg nRCS0,
|
||||
output reg nRCS1,
|
||||
output reg nRWE,
|
||||
output reg nROE,
|
||||
output reg Video,
|
||||
output reg VSync,
|
||||
output reg Hsync);
|
||||
|
||||
/* Video RAM select (superset) */
|
||||
wire VidRAMWR = ~RnW && A[23:20]==4'h3 && A[19:16]==4'hF;
|
||||
|
||||
/* Horizontal counter */
|
||||
reg [9:0] HC;
|
||||
always @(posedge VCLK) begin
|
||||
if (HC==671) HC<=0;
|
||||
else HC <= HC+1;
|
||||
end
|
||||
|
||||
/* Horizontal sync */
|
||||
always @(posedge VCLK) begin
|
||||
if (HC==0) HSync <= 1; // Visible earea end, back porch start
|
||||
else if (HC==079) HSync <= 0; // Back porch end, sync start
|
||||
else if (HC==148) HSync <= 1; // Sync end, front porch start
|
||||
end
|
||||
|
||||
/* Horizontal active */
|
||||
reg HActive = 0;
|
||||
always @(posedge VCLK) begin
|
||||
if (HC==0) HActive <= 0; // Visible area end, back porch start
|
||||
else if (HC==160) HActive <= 1; // Visible area start (FIXME: off by 1?)
|
||||
end
|
||||
|
||||
/* Vertical counter */
|
||||
reg [9:0] VC;
|
||||
always @(posedge VCLK) begin
|
||||
if (VC==805) VC <= 0;
|
||||
else if (HC==671) VC <= VC+1; // Or HC==0?
|
||||
end
|
||||
|
||||
/* Vertical sync */
|
||||
always @(posedge VCLK) begin
|
||||
if (HC==0) VSync <= 1; // Back porch start
|
||||
else if (HC==028) VSync <= 0; // Back porch end, sync start
|
||||
else if (HC==034) VSync <= 1; // Sync end, front porch start
|
||||
else if (HC==037) VSync <= 1; // Sync end, front porch start
|
||||
//else if (HC==38) VSync <= 1; // Visible area start
|
||||
end
|
||||
|
||||
/* Vertical active */
|
||||
reg VActive = 0;
|
||||
always @(posedge VCLK) begin
|
||||
if (HC==0) VActive <= 0; // Visible area end, back porch start
|
||||
else if (HC==160) VActive <= 1; // Visible area start (FIXME: off by 1?)
|
||||
end
|
||||
|
||||
/* AS/select synchronization */
|
||||
reg SELr1, SELr2;
|
||||
always @(negedge VCLK) begin SELr0 <= ~nAS && VidRAMWR; end
|
||||
always @(posedge VCLK) begin SELr1 <= SELr0; end
|
||||
always @(posedge VCLK) begin SELr2 <= SELr1; end
|
||||
|
||||
/* Write/AS Request */
|
||||
wire ASReqNow = ~SELr2 && SELr1;
|
||||
reg ASReqSaved;
|
||||
reg ASReqSaved;
|
||||
wire ASReq = ASReqNow || ASReqSaved;
|
||||
always @(posedge VCLK) begin
|
||||
// FIXME: ASReqSaved
|
||||
if (HC[2:0]==1 || HC[2:0]==4) ASReqSaved <= 0;
|
||||
else if (ASReqNow) ASReqSaved <= 1;
|
||||
end
|
||||
|
||||
/* RAM data bus control */
|
||||
reg [7:0] RDout;
|
||||
reg RDOE;
|
||||
assign RD[7:0] = RDOE ? RDout[7:0] : RDOE;
|
||||
always @(posedge VCLK) begin
|
||||
RDOE <= HC[2:0]==1 || HC[2:0]==2 || HC[2:0]==3 ||
|
||||
HC[2:0]==4 || HC[2:0]==5;
|
||||
end
|
||||
/* Video state machine control */
|
||||
always @(posedge VCLK) begin
|
||||
case (HC[2:0])
|
||||
0: begin
|
||||
RA[14:0] <= A[15:1];
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= 1;
|
||||
nRWE <= 1;
|
||||
nROE <= 1;
|
||||
end 1: begin
|
||||
if (ASReq) begin
|
||||
nRCS0 <= ~nLDS;
|
||||
nRCS1 <= 1;
|
||||
end else begin
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= 1;
|
||||
end
|
||||
RDout[7:0] <= D[7:0];
|
||||
nRWE <= 0;
|
||||
nROE <= 1;
|
||||
end 2: begin
|
||||
if (~RCS0) begin
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= ~nUDS;
|
||||
end else begin
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= 1;
|
||||
end
|
||||
RDout[7:0] <= D[15:8];
|
||||
nRWE <= 0;
|
||||
nROE <= 1;
|
||||
end 3: begin
|
||||
if (nRCS1) RA[14:0] <= A[15:1];
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= 1;
|
||||
nRWE <= 0;
|
||||
nROE <= 1;
|
||||
end 4: begin
|
||||
if (ASReq) begin
|
||||
nRCS0 <= ~nLDS;
|
||||
nRCS1 <= 1;
|
||||
end else begin
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= 1;
|
||||
end
|
||||
RDout[7:0] <= D[7:0];
|
||||
nRWE <= 0;
|
||||
nROE <= 1;
|
||||
end 5: begin
|
||||
if (~RCS0) begin
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= ~nUDS;
|
||||
end else begin
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= 1;
|
||||
end
|
||||
RDout[7:0] <= D[15:8];
|
||||
nRWE <= 0;
|
||||
nROE <= 1;
|
||||
end 6: begin
|
||||
nRCS0 <= 1;
|
||||
nRCS1 <= 1;
|
||||
nRWE <= 1;
|
||||
nROE <= 1;
|
||||
end 7: begin
|
||||
RA[14:0] <= {1'b0, VC[9:1], HC[9:5]}; //FIXME: wrong address
|
||||
nRCS0 <= HC[5]; //FIXME: byte ordering
|
||||
nRCS1 <= ~HC[5];
|
||||
nRWE <= 1;
|
||||
nROE <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
/* Video pixel output state machine */
|
||||
reg VideoShift[7:1];
|
||||
always @(posedge VCLK) begin
|
||||
//FIXME: bit ordering and polarity
|
||||
if (HActive && VActive) begin
|
||||
if (HC[2:0]==0) Video <= RD[0];
|
||||
else Video <= VideoShift[1];
|
||||
end else Video <= 0;
|
||||
end
|
||||
always @(posedge VCLK) begin
|
||||
//FIXME: bit ordering
|
||||
if (HC[2:0]==0) VideoShift[7:1] <= RD[7:1];
|
||||
else VideoShift[6:1] <= VideoShift[7:2];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
Release 14.7 ngdbuild P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
|
||||
ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p
|
||||
xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
|
||||
Reading NGO file
|
||||
"C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.ngc" ...
|
||||
Gathering constraint information from source properties...
|
||||
Done.
|
||||
|
||||
Annotating constraints to design from ucf file
|
||||
"C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf" ...
|
||||
Resolving constraint associations...
|
||||
Checking Constraint Associations...
|
||||
Done...
|
||||
|
||||
Checking expanded design ...
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
|
||||
Total memory usage is 130168 kilobytes
|
||||
|
||||
Writing NGD file "MXSE.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 1 sec
|
||||
Total CPU time to NGDBUILD completion: 1 sec
|
||||
|
||||
Writing NGDBUILD log file "MXSE.bld"...
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
-cwd "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL" timingan_cpld -intstyle ise "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.vm6"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
-cwd "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL" timingan_cpld -intstyle ise "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.vm6"
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
XSLTProcess MXSE_build.xml
|
||||
tsim -intstyle ise MXSE MXSE.nga
|
||||
hprep6 -s IEEE1149 -n MXSE -i MXSE
|
||||
taengine -intstyle ise -f MXSE -w --format html1 -l MXSE_html/tim/timing_report.htm
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/MXSE.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf -p xc95144xl-TQ100-10 MXSE.ngc MXSE.ngd
|
||||
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper MXSE.ngd
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="MXSE.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MXSE.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MXSE.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_GYD" xil_pn:name="MXSE.gyd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_JEDEC" xil_pn:name="MXSE.jed"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MXSE.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MFD" xil_pn:name="MXSE.mfd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGA" xil_pn:name="MXSE.nga"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MXSE.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MXSE.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MXSE.ngr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PNX" xil_pn:name="MXSE.pnx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MXSE.prj"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="MXSE.rpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="MXSE.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MXSE.syr"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="MXSE.tim"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="MXSE.tspec"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VM6" xil_pn:name="MXSE.vm6"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MXSE.xst"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="MXSE_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="MXSE_html"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="MXSE_ngdbuild.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="MXSE_summary.html"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="MXSE_xst.xrpt"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="RAM_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="RAM_stx_beh.prj"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="t_cnt_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="t_cs_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="t_cs_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="t_cs_isim_beh.wdb"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="t_cs_stx_beh.prj"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="t_fsb_dtack_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="t_fsb_dtack_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="t_fsb_dtack_isim_beh.wdb"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="test_fsb_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_fsb_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="test_fsb_isim_beh.wdb"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="test_fsb_stx_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_fsb_vpa_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="test_stx_beh.prj"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1635057466" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1635057466">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635057466" xil_pn:in_ck="3042733603124830897" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1635057466">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="../CNT.v"/>
|
||||
<outfile xil_pn:name="../CS.v"/>
|
||||
<outfile xil_pn:name="../FSB.v"/>
|
||||
<outfile xil_pn:name="../IOBM.v"/>
|
||||
<outfile xil_pn:name="../IOBS.v"/>
|
||||
<outfile xil_pn:name="../MXSE.v"/>
|
||||
<outfile xil_pn:name="../RAM.v"/>
|
||||
<outfile xil_pn:name="../test/t_cnt.v"/>
|
||||
<outfile xil_pn:name="../test/t_cs.v"/>
|
||||
<outfile xil_pn:name="../test/t_fsb_dtack.v"/>
|
||||
<outfile xil_pn:name="../test/t_fsb_vpa.v"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635057466" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="7649031708544547376" xil_pn:start_ts="1635057466">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635057466" xil_pn:in_ck="3042733603124830897" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1635057466">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="../CNT.v"/>
|
||||
<outfile xil_pn:name="../CS.v"/>
|
||||
<outfile xil_pn:name="../FSB.v"/>
|
||||
<outfile xil_pn:name="../IOBM.v"/>
|
||||
<outfile xil_pn:name="../IOBS.v"/>
|
||||
<outfile xil_pn:name="../MXSE.v"/>
|
||||
<outfile xil_pn:name="../RAM.v"/>
|
||||
<outfile xil_pn:name="../test/t_cnt.v"/>
|
||||
<outfile xil_pn:name="../test/t_cs.v"/>
|
||||
<outfile xil_pn:name="../test/t_fsb_dtack.v"/>
|
||||
<outfile xil_pn:name="../test/t_fsb_vpa.v"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635057469" xil_pn:in_ck="3042733603124830897" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="2788949017325677469" xil_pn:start_ts="1635057466">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="fuse.log"/>
|
||||
<outfile xil_pn:name="isim"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
<outfile xil_pn:name="t_cs_beh.prj"/>
|
||||
<outfile xil_pn:name="t_cs_isim_beh.exe"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635057469" xil_pn:in_ck="-5203525758811805332" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2595013534318469184" xil_pn:start_ts="1635057469">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="isim.cmd"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
<outfile xil_pn:name="t_cs_isim_beh.wdb"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635074003" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635074003">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635074003" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="167449203504654628" xil_pn:start_ts="1635074003">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635074007" xil_pn:in_ck="-7042198571556068688" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-2899378119827487496" xil_pn:start_ts="1635074003">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name="MXSE.lso"/>
|
||||
<outfile xil_pn:name="MXSE.ngc"/>
|
||||
<outfile xil_pn:name="MXSE.ngr"/>
|
||||
<outfile xil_pn:name="MXSE.prj"/>
|
||||
<outfile xil_pn:name="MXSE.stx"/>
|
||||
<outfile xil_pn:name="MXSE.syr"/>
|
||||
<outfile xil_pn:name="MXSE.xst"/>
|
||||
<outfile xil_pn:name="MXSE_xst.xrpt"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635074007" xil_pn:in_ck="72657061410852372" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="123229027434767103" xil_pn:start_ts="1635074007">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635074010" xil_pn:in_ck="1136913611493600791" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1635074007">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="MXSE.bld"/>
|
||||
<outfile xil_pn:name="MXSE.ngd"/>
|
||||
<outfile xil_pn:name="MXSE_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635074024" xil_pn:in_ck="3398601133060" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="-8996915014894439674" xil_pn:start_ts="1635074010">
|
||||
<status xil_pn:value="FailedRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="MXSE.rpt"/>
|
||||
<outfile xil_pn:name="MXSE.tim"/>
|
||||
<outfile xil_pn:name="MXSE.tspec"/>
|
||||
<outfile xil_pn:name="MXSE_html"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635071506" xil_pn:in_ck="3398601141924" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1635071505">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<outfile xil_pn:name="MXSE.jed"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1635071511" xil_pn:in_ck="3398601141924" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1635071509">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForced"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1633597924" xil_pn:in_ck="1136913611493600792" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1633597924">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
Pin Freeze File: version P.20131013
|
||||
|
||||
95144XL100 XC95144XL-10-TQ100
|
||||
A_FSB<10> S:PIN68
|
||||
A_FSB<11> S:PIN11
|
||||
A_FSB<12> S:PIN64
|
||||
A_FSB<13> S:PIN13
|
||||
A_FSB<14> S:PIN14
|
||||
A_FSB<15> S:PIN15
|
||||
A_FSB<16> S:PIN89
|
||||
A_FSB<17> S:PIN90
|
||||
A_FSB<18> S:PIN92
|
||||
A_FSB<19> S:PIN82
|
||||
A_FSB<1> S:PIN17
|
||||
A_FSB<20> S:PIN93
|
||||
A_FSB<21> S:PIN80
|
||||
A_FSB<22> S:PIN95
|
||||
A_FSB<23> S:PIN76
|
||||
A_FSB<2> S:PIN18
|
||||
A_FSB<3> S:PIN78
|
||||
A_FSB<4> S:PIN54
|
||||
A_FSB<5> S:PIN25
|
||||
A_FSB<6> S:PIN19
|
||||
A_FSB<7> S:PIN96
|
||||
A_FSB<8> S:PIN52
|
||||
A_FSB<9> S:PIN59
|
||||
CLK2X_IOB S:PIN22
|
||||
CLK_FSB S:PIN23
|
||||
CLK_IOB S:PIN27
|
||||
E_IOB S:PIN46
|
||||
nAS_FSB S:PIN73
|
||||
nBERR_IOB S:PIN56
|
||||
nDTACK_IOB S:PIN49
|
||||
nLDS_FSB S:PIN71
|
||||
nRES S:PIN99
|
||||
nUDS_FSB S:PIN20
|
||||
nVPA_IOB S:PIN28
|
||||
nWE_FSB S:PIN66
|
||||
RA<11> S:PIN58
|
||||
RA<10> S:PIN70
|
||||
RA<0> S:PIN8
|
||||
RA<1> S:PIN87
|
||||
RA<2> S:PIN65
|
||||
RA<3> S:PIN74
|
||||
RA<4> S:PIN77
|
||||
RA<5> S:PIN91
|
||||
RA<6> S:PIN67
|
||||
RA<7> S:PIN50
|
||||
RA<8> S:PIN53
|
||||
RA<9> S:PIN55
|
||||
nADoutLE0 S:PIN60
|
||||
nADoutLE1 S:PIN16
|
||||
nAS_IOB S:PIN10
|
||||
nAoutOE S:PIN72
|
||||
nBERR_FSB S:PIN63
|
||||
nCAS S:PIN79
|
||||
nDTACK_FSB S:PIN12
|
||||
nDinLE S:PIN61
|
||||
nDinOE S:PIN94
|
||||
nDoutOE S:PIN9
|
||||
nLDS_IOB S:PIN6
|
||||
nOE S:PIN81
|
||||
nRAMLWE S:PIN33
|
||||
nRAMUWE S:PIN97
|
||||
nRAS S:PIN24
|
||||
nROMCS S:PIN35
|
||||
nROMWE S:PIN85
|
||||
nUDS_IOB S:PIN7
|
||||
nVMA_IOB S:PIN29
|
||||
nVPA_FSB S:PIN86
|
||||
|
||||
|
||||
;The remaining section of the .gyd file is for documentation purposes only.
|
||||
;It shows where your internal equations were placed in the last successful fit.
|
||||
|
||||
PARTITION FB1_1 EXP14_ EXP15_ nDTACK_FSB_OBUF EXP16_
|
||||
EXP17_ EXP18_
|
||||
PARTITION FB1_8 EXP19_ nADoutLE1_OBUF fsb/BERR0r EXP20_
|
||||
fsb/Ready2r EXP21_ $OpTx$INV$223 EXP22_
|
||||
IORW0 IOREQ EXP23_
|
||||
PARTITION FB2_1 iobm/IOS_FSM_FFd7 iobm/IOS_FSM_FFd6 iobm/IOS_FSM_FFd5 iobm/IOS_FSM_FFd4
|
||||
iobm/IOS_FSM_FFd1 iobm/BERRrr iobm/BERRrf iobm/IOS_FSM_FFd8
|
||||
ALE0M iobm/IOS_FSM_FFd2 nLDS_IOB_OBUF nUDS_IOB_OBUF
|
||||
iobm/IOS_FSM_FFd3 RA_0_OBUF nDoutOE_OBUF IOBERR
|
||||
nAS_IOB_OBUF IOACT
|
||||
PARTITION FB3_1 EXP24_ EXP25_ iobs/IORW1 iobm/ETACK
|
||||
nRAS_OBUF iobs/PS_FSM_FFd1 iobs/IOReady BERR_IOBS
|
||||
ram/RS_FSM_FFd1 ram/Once nVMA_IOB_OBUF iobs/PS_FSM_FFd2
|
||||
EXP26_ iobs/Once nRAMLWE_OBUF fsb/Ready1r
|
||||
EXP27_ iobs/Load1
|
||||
PARTITION FB4_1 EXP28_ RA_1_OBUF EXP29_ ram/RS_FSM_FFd2
|
||||
EXP30_ ram/RASEL EXP31_ RA_5_OBUF
|
||||
EXP32_ ram/RAMDIS1 EXP33_ nDinOE_OBUF
|
||||
EXP34_ ram/RAMReady EXP35_ EXP36_
|
||||
nRAMUWE_OBUF ram/RAMDIS2
|
||||
PARTITION FB5_2 nROMCS_OBUF
|
||||
PARTITION FB5_16 iobm/VPArr iobm/Er cnt/RefCnt<0>
|
||||
PARTITION FB6_1 ram/BACTr RA_3_OBUF iobs/IOACTr fsb/ASrf
|
||||
cnt/RefCnt<3> RA_4_OBUF cnt/RefCnt<2> cnt/RefCnt<1>
|
||||
nCAS_OBUF RefAck ALE0S nOE_OBUF
|
||||
iobs/IOU1 iobs/IOL1 nROMWE_OBUF IOU0
|
||||
nVPA_FSB_OBUF IOL0
|
||||
PARTITION FB7_1 iobm/VPArf RA_7_OBUF iobm/RESrr iobm/RESrf
|
||||
iobm/IOREQr RA_8_OBUF iobm/Er2 iobm/DTACKrr
|
||||
RA_9_OBUF iobm/DTACKrf iobm/ES<3> A_FSB_19_IBUF$BUF0
|
||||
iobm/ES<1> iobm/ES<0> nADoutLE0_OBUF iobm/ES<4>
|
||||
nDinLE_OBUF iobm/ES<2>
|
||||
PARTITION FB8_1 fsb/VPA nBERR_FSB_OBUF cnt/RefCnt<6> cnt/RefCnt<5>
|
||||
cnt/RefCnt<4> RA_2_OBUF fsb/BERR1r cs/nOverlay1
|
||||
RA_6_OBUF cs/nOverlay0 cnt/RefDone A_FSB_21_IBUF$BUF0
|
||||
fsb/Ready0r TimeoutB nAoutOE_OBUF ram/RS_FSM_FFd3
|
||||
TimeoutA cnt/RefCnt<7>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1 @@
|
|||
work
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,18 @@
|
|||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ibis [
|
||||
<!ELEMENT ibis (part, pin+)>
|
||||
<!ELEMENT part EMPTY>
|
||||
<!ELEMENT pin EMPTY>
|
||||
<!ATTLIST part
|
||||
arch CDATA #REQUIRED
|
||||
device CDATA #REQUIRED
|
||||
spg CDATA #REQUIRED
|
||||
pkg CDATA #REQUIRED>
|
||||
<!ATTLIST pin
|
||||
nm CDATA #REQUIRED
|
||||
no CDATA #REQUIRED
|
||||
iostd (TTL|LVTTL|LVCMOS2|NA) "NA"
|
||||
sr (SLOW|FAST|slow|fast) "SLOW"
|
||||
dir (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
|
||||
]>
|
||||
<ibis><part arch="xc9500xl" device="XC95144XL" pkg="TQ100" spg="-10"/><pin dir="input" nm="A_FSB<9>" no="59"/><pin dir="input" nm="A_FSB<20>" no="93"/><pin dir="input" nm="A_FSB<19>" no="82"/><pin dir="input" nm="A_FSB<18>" no="92"/><pin dir="input" nm="A_FSB<17>" no="90"/><pin dir="input" nm="A_FSB<16>" no="89"/><pin dir="input" nm="A_FSB<15>" no="15"/><pin dir="input" nm="A_FSB<13>" no="13"/><pin dir="input" nm="A_FSB<23>" no="76"/><pin dir="input" nm="A_FSB<22>" no="95"/><pin dir="input" nm="A_FSB<21>" no="80"/><pin dir="input" nm="A_FSB<14>" no="14"/><pin dir="input" nm="A_FSB<12>" no="64"/><pin dir="input" nm="A_FSB<11>" no="11"/><pin dir="input" nm="A_FSB<10>" no="68"/><pin dir="input" nm="CLK2X_IOB" no="22"/><pin dir="input" nm="CLK_FSB" no="23"/><pin dir="input" nm="nAS_FSB" no="73"/><pin dir="input" nm="nWE_FSB" no="66"/><pin dir="input" nm="nBERR_IOB" no="56"/><pin dir="input" nm="CLK_IOB" no="27"/><pin dir="input" nm="nRES" no="99"/><pin dir="input" nm="nLDS_FSB" no="71"/><pin dir="input" nm="nUDS_FSB" no="20"/><pin dir="input" nm="E_IOB" no="46"/><pin dir="input" nm="nVPA_IOB" no="28"/><pin dir="input" nm="nDTACK_IOB" no="49"/><pin dir="input" nm="A_FSB<1>" no="17"/><pin dir="input" nm="A_FSB<2>" no="18"/><pin dir="input" nm="A_FSB<3>" no="78"/><pin dir="input" nm="A_FSB<4>" no="54"/><pin dir="input" nm="A_FSB<5>" no="25"/><pin dir="input" nm="A_FSB<6>" no="19"/><pin dir="input" nm="A_FSB<7>" no="96"/><pin dir="input" nm="A_FSB<8>" no="52"/><pin dir="output" nm="nVMA_IOB" no="29" sr="fast"/><pin dir="output" nm="nDTACK_FSB" no="12" sr="fast"/><pin dir="output" nm="nAS_IOB" no="10" sr="fast"/><pin dir="output" nm="nCAS" no="79" sr="fast"/><pin dir="output" nm="nDinLE" no="61" sr="fast"/><pin dir="output" nm="nDoutOE" no="9" sr="fast"/><pin dir="output" nm="nLDS_IOB" no="6" sr="fast"/><pin dir="output" nm="nUDS_IOB" no="7" sr="fast"/><pin dir="output" nm="RA<0>" no="8" sr="fast"/><pin dir="output" nm="RA<1>" no="87" sr="fast"/><pin dir="output" nm="RA<2>" no="65" sr="fast"/><pin dir="output" nm="RA<3>" no="74" sr="fast"/><pin dir="output" nm="RA<4>" no="77" sr="fast"/><pin dir="output" nm="RA<5>" no="91" sr="fast"/><pin dir="output" nm="RA<6>" no="67" sr="fast"/><pin dir="output" nm="RA<7>" no="50" sr="fast"/><pin dir="output" nm="RA<8>" no="53" sr="fast"/><pin dir="output" nm="RA<9>" no="55" sr="fast"/><pin dir="output" nm="nOE" no="81" sr="fast"/><pin dir="output" nm="nROMWE" no="85" sr="fast"/><pin dir="output" nm="nVPA_FSB" no="86" sr="fast"/><pin dir="output" nm="nADoutLE0" no="60" sr="fast"/><pin dir="output" nm="nDinOE" no="94" sr="fast"/><pin dir="output" nm="nRAS" no="24" sr="fast"/><pin dir="output" nm="RA<11>" no="58" sr="fast"/><pin dir="output" nm="RA<10>" no="70" sr="fast"/><pin dir="output" nm="nADoutLE1" no="16" sr="fast"/><pin dir="output" nm="nBERR_FSB" no="63" sr="fast"/><pin dir="output" nm="nRAMLWE" no="33" sr="fast"/><pin dir="output" nm="nRAMUWE" no="97" sr="fast"/><pin dir="output" nm="nROMCS" no="35" sr="fast"/><pin dir="output" nm="nAoutOE" no="72" sr="fast"/></ibis>
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
verilog work "../RAM.v"
|
||||
verilog work "../IOBS.v"
|
||||
verilog work "../IOBM.v"
|
||||
verilog work "../FSB.v"
|
||||
verilog work "../CS.v"
|
||||
verilog work "../CNT.v"
|
||||
verilog work "../MXSE.v"
|
||||
|
|
@ -0,0 +1,677 @@
|
|||
|
||||
cpldfit: version P.20131013 Xilinx Inc.
|
||||
Fitter Report
|
||||
Design Name: MXSE Date: 10-24-2021, 7:13AM
|
||||
Device Used: XC95144XL-10-TQ100
|
||||
Fitting Status: Successful
|
||||
|
||||
************************* Mapped Resource Summary **************************
|
||||
|
||||
Macrocells Product Terms Function Block Registers Pins
|
||||
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
|
||||
108/144 ( 75%) 448 /720 ( 62%) 237/432 ( 55%) 82 /144 ( 57%) 67 /81 ( 83%)
|
||||
|
||||
** Function Block Resources **
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 9/18 39/54 82/90 11/11*
|
||||
FB2 18/18* 38/54 33/90 6/10
|
||||
FB3 18/18* 29/54 51/90 7/10
|
||||
FB4 12/18 36/54 81/90 10/10*
|
||||
FB5 8/18 21/54 81/90 3/10
|
||||
FB6 14/18 41/54 75/90 10/10*
|
||||
FB7 18/18* 20/54 35/90 10/10*
|
||||
FB8 11/18 13/54 10/90 10/10*
|
||||
----- ----- ----- -----
|
||||
108/144 237/432 448/720 67/81
|
||||
|
||||
* - Resource is exhausted
|
||||
|
||||
** Global Control Resources **
|
||||
|
||||
Signal 'CLK2X_IOB' mapped onto global clock net GCK1.
|
||||
Signal 'CLK_FSB' mapped onto global clock net GCK2.
|
||||
Signal 'CLK_IOB' mapped onto global clock net GCK3.
|
||||
Global output enable net(s) unused.
|
||||
Signal 'nRES' mapped onto global set/reset net GSR.
|
||||
|
||||
** Pin Resources **
|
||||
|
||||
Signal Type Required Mapped | Pin Type Used Total
|
||||
------------------------------------|------------------------------------
|
||||
Input : 31 31 | I/O : 63 73
|
||||
Output : 32 32 | GCK/IO : 3 3
|
||||
Bidirectional : 0 0 | GTS/IO : 0 4
|
||||
GCK : 3 3 | GSR/IO : 1 1
|
||||
GTS : 0 0 |
|
||||
GSR : 1 1 |
|
||||
---- ----
|
||||
Total 67 67
|
||||
|
||||
** Power Data **
|
||||
|
||||
There are 108 macrocells in high performance mode (MCHP).
|
||||
There are 0 macrocells in low power mode (MCLP).
|
||||
End of Mapped Resource Summary
|
||||
************************** Errors and Warnings ***************************
|
||||
|
||||
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
|
||||
use the default filename of 'MXSE.ise'.
|
||||
************************* Summary of Mapped Logic ************************
|
||||
|
||||
** 32 Outputs **
|
||||
|
||||
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
|
||||
Name Pts Inps No. Type Use Mode Rate State
|
||||
nDTACK_FSB 23 32 FB1_2 11 I/O O STD FAST RESET
|
||||
nBERR_FSB 3 9 FB1_6 14 I/O O STD FAST
|
||||
RA<0> 2 3 FB1_11 17 I/O O STD FAST
|
||||
RA<3> 2 3 FB2_11 6 I/O O STD FAST
|
||||
RA<4> 2 3 FB2_14 8 I/O O STD FAST
|
||||
RA<6> 2 3 FB2_17 10 I/O O STD FAST
|
||||
nLDS_IOB 3 7 FB3_5 24 I/O O STD FAST RESET
|
||||
nDoutOE 2 7 FB3_11 29 I/O O STD FAST RESET
|
||||
nAS_IOB 1 5 FB3_14 32 I/O O STD FAST RESET
|
||||
nUDS_IOB 3 7 FB3_17 34 I/O O STD FAST RESET
|
||||
nRAS 3 8 FB4_2 87 I/O O STD FAST
|
||||
RA<1> 2 3 FB4_6 90 I/O O STD FAST
|
||||
RA<2> 2 3 FB4_9 92 I/O O STD FAST
|
||||
RA<5> 2 3 FB4_12 94 I/O O STD FAST
|
||||
nVMA_IOB 2 9 FB4_15 96 I/O O STD FAST RESET
|
||||
nDinOE 2 6 FB5_8 39 I/O O STD FAST
|
||||
nROMCS 2 5 FB5_11 41 I/O O STD FAST
|
||||
nADoutLE1 14 18 FB5_14 43 I/O O STD FAST SET
|
||||
nCAS 1 1 FB6_2 74 I/O O STD FAST RESET
|
||||
nOE 1 2 FB6_6 77 I/O O STD FAST
|
||||
nRAMLWE 1 5 FB6_9 79 I/O O STD FAST
|
||||
nRAMUWE 1 5 FB6_12 81 I/O O STD FAST
|
||||
nROMWE 1 2 FB6_15 85 I/O O STD FAST
|
||||
nVPA_FSB 1 2 FB6_17 86 I/O O STD FAST
|
||||
RA<7> 2 3 FB7_2 50 I/O O STD FAST
|
||||
RA<8> 2 3 FB7_8 54 I/O O STD FAST
|
||||
RA<9> 2 3 FB7_12 58 I/O O STD FAST
|
||||
RA<11> 1 1 FB7_17 61 I/O O STD FAST
|
||||
RA<10> 1 1 FB8_2 63 I/O O STD FAST
|
||||
nADoutLE0 1 2 FB8_8 66 I/O O STD FAST
|
||||
nAoutOE 0 0 FB8_12 70 I/O O STD FAST
|
||||
nDinLE 1 2 FB8_17 73 I/O O STD FAST RESET
|
||||
|
||||
** 76 Buried Nodes **
|
||||
|
||||
Signal Total Total Loc Pwr Reg Init
|
||||
Name Pts Inps Mode State
|
||||
cs/nOverlay1 2 3 FB1_5 STD RESET
|
||||
fsb/Ready2r 9 22 FB1_7 STD RESET
|
||||
fsb/VPA__or00001/fsb/VPA__or00001_D2 8 20 FB1_8 STD
|
||||
fsb/Ready1r 7 17 FB1_9 STD RESET
|
||||
fsb/VPA 22 30 FB1_13 STD RESET
|
||||
$OpTx$FX_DC$607 6 12 FB1_16 STD
|
||||
cnt/RefCnt<7> 1 7 FB2_1 STD RESET
|
||||
cnt/RefCnt<6> 1 6 FB2_2 STD RESET
|
||||
cnt/RefCnt<5> 1 5 FB2_3 STD RESET
|
||||
cnt/RefCnt<4> 1 4 FB2_4 STD RESET
|
||||
cnt/RefCnt<3> 1 3 FB2_5 STD RESET
|
||||
cnt/RefCnt<2> 1 2 FB2_6 STD RESET
|
||||
cnt/RefCnt<1> 1 1 FB2_7 STD RESET
|
||||
iobs/PS_FSM_FFd1 2 3 FB2_8 STD RESET
|
||||
fsb/BERR1r 2 4 FB2_9 STD RESET
|
||||
cs/nOverlay0 2 7 FB2_10 STD RESET
|
||||
cnt/RefDone 2 10 FB2_12 STD RESET
|
||||
$OpTx$FX_DC$603 2 5 FB2_13 STD
|
||||
IOU0 3 5 FB2_15 STD RESET
|
||||
IOL0 3 5 FB2_16 STD RESET
|
||||
iobs/IOReady 4 8 FB2_18 STD RESET
|
||||
iobm/IOS_FSM_FFd7 1 3 FB3_1 STD RESET
|
||||
iobm/IOS_FSM_FFd6 1 1 FB3_2 STD RESET
|
||||
iobm/IOS_FSM_FFd5 1 1 FB3_3 STD RESET
|
||||
iobm/IOS_FSM_FFd4 1 1 FB3_4 STD RESET
|
||||
iobm/IOS_FSM_FFd1 1 1 FB3_6 STD RESET
|
||||
iobm/BERRrr 1 1 FB3_7 STD RESET
|
||||
iobm/BERRrf 1 1 FB3_8 STD RESET
|
||||
iobm/IOS_FSM_FFd8 2 4 FB3_9 STD SET
|
||||
ALE0M 2 7 FB3_10 STD RESET
|
||||
iobm/IOS_FSM_FFd2 4 9 FB3_12 STD RESET
|
||||
BERR_IOBS 4 8 FB3_13 STD RESET
|
||||
iobm/IOS_FSM_FFd3 5 10 FB3_15 STD RESET
|
||||
IOBERR 8 11 FB3_16 STD RESET
|
||||
IOACT 10 15 FB3_18 STD RESET
|
||||
ram/RASEL 20 15 FB4_1 STD RESET
|
||||
fsb/Ready0r 3 8 FB4_3 STD RESET
|
||||
iobm/ETACK 1 6 FB4_5 STD RESET
|
||||
ram/RAMReady 16 15 FB4_7 STD RESET
|
||||
ram/RAMDIS2 7 15 FB4_11 STD RESET
|
||||
|
||||
Signal Total Total Loc Pwr Reg Init
|
||||
Name Pts Inps Mode State
|
||||
ram/RAMDIS1 18 15 FB4_13 STD RESET
|
||||
ram/Once 5 10 FB4_16 STD RESET
|
||||
IORW0 18 20 FB5_3 STD RESET
|
||||
iobs/PS_FSM_FFd2 14 19 FB5_7 STD RESET
|
||||
IOREQ 14 19 FB5_9 STD RESET
|
||||
ALE0S 1 2 FB5_15 STD RESET
|
||||
iobs/IORW1 16 19 FB5_17 STD RESET
|
||||
iobs/Once 17 18 FB6_1 STD RESET
|
||||
fsb/BERR0r 3 8 FB6_3 STD RESET
|
||||
ram/RS_FSM_FFd3 11 14 FB6_4 STD RESET
|
||||
TimeoutB 3 12 FB6_5 STD RESET
|
||||
TimeoutA 3 11 FB6_7 STD RESET
|
||||
ram/RS_FSM_FFd1 5 10 FB6_8 STD RESET
|
||||
ram/RS_FSM_FFd2 13 14 FB6_10 STD RESET
|
||||
iobs/Load1 14 18 FB6_13 STD RESET
|
||||
iobm/VPArr 1 1 FB7_1 STD RESET
|
||||
iobm/VPArf 1 1 FB7_3 STD RESET
|
||||
iobm/RESrr 1 1 FB7_4 STD RESET
|
||||
iobm/RESrf 1 1 FB7_5 STD RESET
|
||||
iobm/IOREQr 1 1 FB7_6 STD RESET
|
||||
iobm/Er2 1 1 FB7_7 STD RESET
|
||||
iobm/DTACKrr 1 1 FB7_9 STD RESET
|
||||
iobm/DTACKrf 1 1 FB7_10 STD RESET
|
||||
iobs/IOL1 2 2 FB7_11 STD RESET
|
||||
iobm/ES<3> 3 6 FB7_13 STD RESET
|
||||
iobm/ES<1> 3 4 FB7_14 STD RESET
|
||||
iobm/ES<0> 3 7 FB7_15 STD RESET
|
||||
iobm/ES<4> 4 7 FB7_16 STD RESET
|
||||
iobm/ES<2> 5 7 FB7_18 STD RESET
|
||||
ram/BACTr 1 2 FB8_10 STD RESET
|
||||
iobs/IOACTr 1 1 FB8_11 STD RESET
|
||||
iobm/Er 1 1 FB8_13 STD RESET
|
||||
fsb/ASrf 1 1 FB8_14 STD RESET
|
||||
cnt/RefCnt<0> 0 0 FB8_15 STD RESET
|
||||
RefAck 1 2 FB8_16 STD RESET
|
||||
iobs/IOU1 2 2 FB8_18 STD RESET
|
||||
|
||||
** 35 Inputs **
|
||||
|
||||
Signal Loc Pin Pin Pin
|
||||
Name No. Type Use
|
||||
A_FSB<15> FB1_3 12 I/O I
|
||||
A_FSB<1> FB1_5 13 I/O I
|
||||
A_FSB<9> FB1_8 15 I/O I
|
||||
A_FSB<5> FB1_9 16 I/O I
|
||||
A_FSB<2> FB1_12 18 I/O I
|
||||
A_FSB<6> FB1_14 19 I/O I
|
||||
nBERR_IOB FB1_15 20 I/O I
|
||||
CLK2X_IOB FB1_17 22~ GCK/I/O GCK
|
||||
nRES FB2_2 99~ GSR/I/O GSR/I
|
||||
nAS_FSB FB2_12 7 I/O I
|
||||
nUDS_FSB FB2_15 9 I/O I
|
||||
CLK_FSB FB3_2 23~ GCK/I/O GCK
|
||||
nVPA_IOB FB3_6 25 I/O I
|
||||
CLK_IOB FB3_8 27~ GCK/I/O GCK/I
|
||||
A_FSB<13> FB4_5 89 I/O I
|
||||
A_FSB<14> FB4_8 91 I/O I
|
||||
A_FSB<17> FB4_11 93 I/O I
|
||||
A_FSB<19> FB4_14 95 I/O I
|
||||
A_FSB<21> FB4_17 97 I/O I
|
||||
A_FSB<22> FB6_5 76 I/O I
|
||||
A_FSB<20> FB6_8 78 I/O I
|
||||
A_FSB<18> FB6_11 80 I/O I
|
||||
A_FSB<16> FB6_14 82 I/O I
|
||||
E_IOB FB7_5 52 I/O I
|
||||
nDTACK_IOB FB7_6 53 I/O I
|
||||
A_FSB<3> FB7_9 55 I/O I
|
||||
A_FSB<7> FB7_11 56 I/O I
|
||||
A_FSB<4> FB7_14 59 I/O I
|
||||
A_FSB<8> FB7_15 60 I/O I
|
||||
nWE_FSB FB8_5 64 I/O I
|
||||
A_FSB<12> FB8_6 65 I/O I
|
||||
A_FSB<11> FB8_9 67 I/O I
|
||||
nLDS_FSB FB8_11 68 I/O I
|
||||
A_FSB<23> FB8_14 71 I/O I
|
||||
A_FSB<10> FB8_15 72 I/O I
|
||||
|
||||
Legend:
|
||||
Pin No. - ~ - User Assigned
|
||||
************************** Function Block Details ************************
|
||||
Legend:
|
||||
Total Pt - Total product terms used by the macrocell signal
|
||||
Imp Pt - Product terms imported from other macrocells
|
||||
Exp Pt - Product terms exported to other macrocells
|
||||
in direction shown
|
||||
Unused Pt - Unused local product terms remaining in macrocell
|
||||
Loc - Location where logic was mapped in device
|
||||
Pin Type/Use - I - Input GCK - Global Clock
|
||||
O - Output GTS - Global Output Enable
|
||||
(b) - Buried macrocell GSR - Global Set/Reset
|
||||
X - Signal used as input to the macrocell logic.
|
||||
Pin No. - ~ - User Assigned
|
||||
*********************************** FB1 ***********************************
|
||||
Number of function block inputs used/remaining: 39/15
|
||||
Number of signals used by logic mapping into function block: 39
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
(unused) 0 0 \/5 0 FB1_1 (b) (b)
|
||||
nDTACK_FSB 23 18<- 0 0 FB1_2 11 I/O O
|
||||
(unused) 0 0 /\5 0 FB1_3 12 I/O I
|
||||
(unused) 0 0 /\5 0 FB1_4 (b) (b)
|
||||
cs/nOverlay1 2 0 \/2 1 FB1_5 13 I/O I
|
||||
nBERR_FSB 3 2<- \/4 0 FB1_6 14 I/O O
|
||||
fsb/Ready2r 9 4<- 0 0 FB1_7 (b) (b)
|
||||
fsb/VPA__or00001/fsb/VPA__or00001_D2
|
||||
8 3<- 0 0 FB1_8 15 I/O I
|
||||
fsb/Ready1r 7 5<- /\3 0 FB1_9 16 I/O I
|
||||
(unused) 0 0 /\5 0 FB1_10 (b) (b)
|
||||
RA<0> 2 0 \/2 1 FB1_11 17 I/O O
|
||||
(unused) 0 0 \/5 0 FB1_12 18 I/O I
|
||||
fsb/VPA 22 17<- 0 0 FB1_13 (b) (b)
|
||||
(unused) 0 0 /\5 0 FB1_14 19 I/O I
|
||||
(unused) 0 0 /\5 0 FB1_15 20 I/O I
|
||||
$OpTx$FX_DC$607 6 1<- 0 0 FB1_16 (b) (b)
|
||||
(unused) 0 0 /\1 4 FB1_17 22 GCK/I/O GCK
|
||||
(unused) 0 0 \/3 2 FB1_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: $OpTx$FX_DC$603 14: A_FSB<20> 27: fsb/BERR1r
|
||||
2: $OpTx$FX_DC$607 15: A_FSB<21> 28: fsb/Ready0r
|
||||
3: A_FSB<10> 16: A_FSB<22> 29: fsb/Ready1r
|
||||
4: A_FSB<11> 17: A_FSB<23> 30: fsb/Ready2r
|
||||
5: A_FSB<12> 18: A_FSB<8> 31: fsb/VPA
|
||||
6: A_FSB<13> 19: A_FSB<9> 32: fsb/VPA__or00001/fsb/VPA__or00001_D2
|
||||
7: A_FSB<14> 20: BERR_IOBS 33: iobs/IOReady
|
||||
8: A_FSB<15> 21: TimeoutA 34: nADoutLE1
|
||||
9: A_FSB<16> 22: TimeoutB 35: nAS_FSB
|
||||
10: A_FSB<17> 23: cs/nOverlay0 36: nDTACK_FSB
|
||||
11: A_FSB<18> 24: cs/nOverlay1 37: nWE_FSB
|
||||
12: A_FSB<19> 25: fsb/ASrf 38: ram/RAMReady
|
||||
13: A_FSB<1> 26: fsb/BERR0r 39: ram/RASEL
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
nDTACK_FSB X.XXXXXXXXXX.XXXXXXXX..XXXXXXX..XXXXXX.. 32
|
||||
cs/nOverlay1 ......................X.X.........X..... 3
|
||||
nBERR_FSB .............XXXX..X.X...XX.......X..... 9
|
||||
fsb/Ready2r ..XXXXXXXXXX.XXXXXX.X..XX....X....X.X... 22
|
||||
fsb/VPA__or00001/fsb/VPA__or00001_D2
|
||||
..XXXXXXXXXX.XXXXXX.X..X.....X......X... 20
|
||||
fsb/Ready1r .....XX.XXXX.XXXX......XX...X...XXX.X... 17
|
||||
RA<0> ..X.........X.........................X. 3
|
||||
fsb/VPA XXXXXXXXXXXX.XXXXXXX...XXXXXX.XXX.X..X.. 30
|
||||
$OpTx$FX_DC$607 .....XX.XXXX.XXX.......X.........X..X... 12
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB2 ***********************************
|
||||
Number of function block inputs used/remaining: 38/16
|
||||
Number of signals used by logic mapping into function block: 38
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
cnt/RefCnt<7> 1 0 0 4 FB2_1 (b) (b)
|
||||
cnt/RefCnt<6> 1 0 0 4 FB2_2 99 GSR/I/O GSR/I
|
||||
cnt/RefCnt<5> 1 0 0 4 FB2_3 (b) (b)
|
||||
cnt/RefCnt<4> 1 0 0 4 FB2_4 (b) (b)
|
||||
cnt/RefCnt<3> 1 0 0 4 FB2_5 1 GTS/I/O (b)
|
||||
cnt/RefCnt<2> 1 0 0 4 FB2_6 2 GTS/I/O (b)
|
||||
cnt/RefCnt<1> 1 0 0 4 FB2_7 (b) (b)
|
||||
iobs/PS_FSM_FFd1 2 0 0 3 FB2_8 3 GTS/I/O (b)
|
||||
fsb/BERR1r 2 0 0 3 FB2_9 4 GTS/I/O (b)
|
||||
cs/nOverlay0 2 0 0 3 FB2_10 (b) (b)
|
||||
RA<3> 2 0 0 3 FB2_11 6 I/O O
|
||||
cnt/RefDone 2 0 0 3 FB2_12 7 I/O I
|
||||
$OpTx$FX_DC$603 2 0 0 3 FB2_13 (b) (b)
|
||||
RA<4> 2 0 0 3 FB2_14 8 I/O O
|
||||
IOU0 3 0 0 2 FB2_15 9 I/O I
|
||||
IOL0 3 0 0 2 FB2_16 (b) (b)
|
||||
RA<6> 2 0 0 3 FB2_17 10 I/O O
|
||||
iobs/IOReady 4 0 0 1 FB2_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: A_FSB<13> 14: TimeoutB 27: iobs/IOACTr
|
||||
2: A_FSB<14> 15: cnt/RefCnt<0> 28: iobs/IOL1
|
||||
3: A_FSB<16> 16: cnt/RefCnt<1> 29: iobs/IOReady
|
||||
4: A_FSB<20> 17: cnt/RefCnt<2> 30: iobs/IOU1
|
||||
5: A_FSB<21> 18: cnt/RefCnt<3> 31: iobs/Once
|
||||
6: A_FSB<22> 19: cnt/RefCnt<4> 32: iobs/PS_FSM_FFd1
|
||||
7: A_FSB<23> 20: cnt/RefCnt<5> 33: iobs/PS_FSM_FFd2
|
||||
8: A_FSB<4> 21: cnt/RefCnt<6> 34: nADoutLE1
|
||||
9: A_FSB<5> 22: cnt/RefCnt<7> 35: nAS_FSB
|
||||
10: A_FSB<7> 23: cnt/RefDone 36: nLDS_FSB
|
||||
11: BERR_IOBS 24: cs/nOverlay0 37: nUDS_FSB
|
||||
12: IOBERR 25: fsb/ASrf 38: ram/RASEL
|
||||
13: RefAck 26: fsb/BERR1r
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
cnt/RefCnt<7> ..............XXXXXXX................... 7
|
||||
cnt/RefCnt<6> ..............XXXXXX.................... 6
|
||||
cnt/RefCnt<5> ..............XXXXX..................... 5
|
||||
cnt/RefCnt<4> ..............XXXX...................... 4
|
||||
cnt/RefCnt<3> ..............XXX....................... 3
|
||||
cnt/RefCnt<2> ..............XX........................ 2
|
||||
cnt/RefCnt<1> ..............X......................... 1
|
||||
iobs/PS_FSM_FFd1 ..........................X....XX....... 3
|
||||
fsb/BERR1r ..........X.............XX........X..... 4
|
||||
cs/nOverlay0 ...XXXX................XX.........X..... 7
|
||||
RA<3> X......X.............................X.. 3
|
||||
cnt/RefDone ............X.XXXXXXXXX................. 10
|
||||
$OpTx$FX_DC$603 ...XXXX......X.......................... 5
|
||||
RA<4> .X......X............................X.. 3
|
||||
IOU0 .............................X.XXX..X... 5
|
||||
IOL0 ...........................X...XXX.X.... 5
|
||||
RA<6> ..X......X...........................X.. 3
|
||||
iobs/IOReady ...........X............X.X.X.X.XXX..... 8
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB3 ***********************************
|
||||
Number of function block inputs used/remaining: 29/25
|
||||
Number of signals used by logic mapping into function block: 29
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
iobm/IOS_FSM_FFd7 1 0 /\3 1 FB3_1 (b) (b)
|
||||
iobm/IOS_FSM_FFd6 1 0 0 4 FB3_2 23 GCK/I/O GCK
|
||||
iobm/IOS_FSM_FFd5 1 0 0 4 FB3_3 (b) (b)
|
||||
iobm/IOS_FSM_FFd4 1 0 0 4 FB3_4 (b) (b)
|
||||
nLDS_IOB 3 0 0 2 FB3_5 24 I/O O
|
||||
iobm/IOS_FSM_FFd1 1 0 0 4 FB3_6 25 I/O I
|
||||
iobm/BERRrr 1 0 0 4 FB3_7 (b) (b)
|
||||
iobm/BERRrf 1 0 0 4 FB3_8 27 GCK/I/O GCK/I
|
||||
iobm/IOS_FSM_FFd8 2 0 0 3 FB3_9 28 I/O (b)
|
||||
ALE0M 2 0 0 3 FB3_10 (b) (b)
|
||||
nDoutOE 2 0 0 3 FB3_11 29 I/O O
|
||||
iobm/IOS_FSM_FFd2 4 0 0 1 FB3_12 30 I/O (b)
|
||||
BERR_IOBS 4 0 0 1 FB3_13 (b) (b)
|
||||
nAS_IOB 1 0 \/3 1 FB3_14 32 I/O O
|
||||
iobm/IOS_FSM_FFd3 5 3<- \/3 0 FB3_15 33 I/O (b)
|
||||
IOBERR 8 3<- 0 0 FB3_16 (b) (b)
|
||||
nUDS_IOB 3 0 \/2 0 FB3_17 34 I/O O
|
||||
IOACT 10 5<- 0 0 FB3_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: BERR_IOBS 11: iobm/DTACKrr 21: iobm/IOS_FSM_FFd8
|
||||
2: CLK_IOB 12: iobm/ETACK 22: iobm/RESrf
|
||||
3: IOBERR 13: iobm/IOREQr 23: iobm/RESrr
|
||||
4: IOL0 14: iobm/IOS_FSM_FFd1 24: iobs/IOACTr
|
||||
5: IORW0 15: iobm/IOS_FSM_FFd2 25: iobs/Once
|
||||
6: IOU0 16: iobm/IOS_FSM_FFd3 26: iobs/PS_FSM_FFd2
|
||||
7: fsb/ASrf 17: iobm/IOS_FSM_FFd4 27: nADoutLE1
|
||||
8: iobm/BERRrf 18: iobm/IOS_FSM_FFd5 28: nAS_FSB
|
||||
9: iobm/BERRrr 19: iobm/IOS_FSM_FFd6 29: nBERR_IOB
|
||||
10: iobm/DTACKrf 20: iobm/IOS_FSM_FFd7
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
iobm/IOS_FSM_FFd7 .X..........X.......X................... 3
|
||||
iobm/IOS_FSM_FFd6 ...................X.................... 1
|
||||
iobm/IOS_FSM_FFd5 ..................X..................... 1
|
||||
iobm/IOS_FSM_FFd4 .................X...................... 1
|
||||
nLDS_IOB ...XX..........XXXXX.................... 7
|
||||
iobm/IOS_FSM_FFd1 ..............X......................... 1
|
||||
iobm/BERRrr ............................X........... 1
|
||||
iobm/BERRrf ............................X........... 1
|
||||
iobm/IOS_FSM_FFd8 .X..........XX......X................... 4
|
||||
ALE0M ............X..XXXXXX................... 7
|
||||
nDoutOE ....X.........XXXXXX.................... 7
|
||||
iobm/IOS_FSM_FFd2 .X.....XXXXX...X.....XX................. 9
|
||||
BERR_IOBS X.X...X................XXXXX............ 8
|
||||
nAS_IOB ...............XXXXX.................... 5
|
||||
iobm/IOS_FSM_FFd3 .X.....XXXXX...XX....XX................. 10
|
||||
IOBERR .XX....XXXXX...X.....XX.....X........... 11
|
||||
nUDS_IOB ....XX.........XXXXX.................... 7
|
||||
IOACT .X.....XXXXXX..XXXXXXXX................. 15
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB4 ***********************************
|
||||
Number of function block inputs used/remaining: 36/18
|
||||
Number of signals used by logic mapping into function block: 36
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
ram/RASEL 20 15<- 0 0 FB4_1 (b) (b)
|
||||
nRAS 3 3<- /\5 0 FB4_2 87 I/O O
|
||||
fsb/Ready0r 3 1<- /\3 0 FB4_3 (b) (b)
|
||||
(unused) 0 0 /\1 4 FB4_4 (b) (b)
|
||||
iobm/ETACK 1 0 \/2 2 FB4_5 89 I/O I
|
||||
RA<1> 2 2<- \/5 0 FB4_6 90 I/O O
|
||||
ram/RAMReady 16 11<- 0 0 FB4_7 (b) (b)
|
||||
(unused) 0 0 /\5 0 FB4_8 91 I/O I
|
||||
RA<2> 2 0 /\1 2 FB4_9 92 I/O O
|
||||
(unused) 0 0 \/4 1 FB4_10 (b) (b)
|
||||
ram/RAMDIS2 7 4<- \/2 0 FB4_11 93 I/O I
|
||||
RA<5> 2 2<- \/5 0 FB4_12 94 I/O O
|
||||
ram/RAMDIS1 18 13<- 0 0 FB4_13 (b) (b)
|
||||
(unused) 0 0 /\5 0 FB4_14 95 I/O I
|
||||
nVMA_IOB 2 0 /\3 0 FB4_15 96 I/O O
|
||||
ram/Once 5 0 0 0 FB4_16 (b) (b)
|
||||
(unused) 0 0 \/5 0 FB4_17 97 I/O I
|
||||
(unused) 0 0 \/5 0 FB4_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: A_FSB<11> 13: cnt/RefCnt<6> 25: iobm/VPArr
|
||||
2: A_FSB<12> 14: cnt/RefCnt<7> 26: nAS_FSB
|
||||
3: A_FSB<15> 15: cnt/RefDone 27: nVMA_IOB
|
||||
4: A_FSB<21> 16: cs/nOverlay1 28: ram/BACTr
|
||||
5: A_FSB<22> 17: fsb/ASrf 29: ram/Once
|
||||
6: A_FSB<23> 18: fsb/Ready0r 30: ram/RAMDIS1
|
||||
7: A_FSB<2> 19: iobm/ES<0> 31: ram/RAMDIS2
|
||||
8: A_FSB<3> 20: iobm/ES<1> 32: ram/RAMReady
|
||||
9: A_FSB<6> 21: iobm/ES<2> 33: ram/RASEL
|
||||
10: IOACT 22: iobm/ES<3> 34: ram/RS_FSM_FFd1
|
||||
11: RefAck 23: iobm/ES<4> 35: ram/RS_FSM_FFd2
|
||||
12: cnt/RefCnt<5> 24: iobm/VPArf 36: ram/RS_FSM_FFd3
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
ram/RASEL ...XXX.....XXXXXX........X.XX....XXX.... 15
|
||||
nRAS ...XXX....X....X.........X...XX......... 8
|
||||
fsb/Ready0r ...XXX.........XXX.......X.....X........ 8
|
||||
iobm/ETACK ..................XXXXX...X............. 6
|
||||
RA<1> X.....X.........................X....... 3
|
||||
ram/RAMReady ...XXX.....XXXXXX........X.XX....XXX.... 15
|
||||
RA<2> .X.....X........................X....... 3
|
||||
ram/RAMDIS2 ...XXX.....XXXXXX........X..X.X..XXX.... 15
|
||||
RA<5> ..X.....X.......................X....... 3
|
||||
ram/RAMDIS1 ...XXX.....XXXXXX........X.XX....XXX.... 15
|
||||
nVMA_IOB .........X........XXXXXXX.X............. 9
|
||||
ram/Once ...XXX.........XX........X..X....XXX.... 10
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB5 ***********************************
|
||||
Number of function block inputs used/remaining: 21/33
|
||||
Number of signals used by logic mapping into function block: 21
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
(unused) 0 0 /\1 4 FB5_1 (b) (b)
|
||||
(unused) 0 0 \/5 0 FB5_2 35 I/O (b)
|
||||
IORW0 18 13<- 0 0 FB5_3 (b) (b)
|
||||
(unused) 0 0 /\5 0 FB5_4 (b) (b)
|
||||
(unused) 0 0 /\3 2 FB5_5 36 I/O (b)
|
||||
(unused) 0 0 \/5 0 FB5_6 37 I/O (b)
|
||||
iobs/PS_FSM_FFd2 14 9<- 0 0 FB5_7 (b) (b)
|
||||
nDinOE 2 1<- /\4 0 FB5_8 39 I/O O
|
||||
IOREQ 14 10<- /\1 0 FB5_9 40 I/O (b)
|
||||
(unused) 0 0 /\5 0 FB5_10 (b) (b)
|
||||
nROMCS 2 2<- /\5 0 FB5_11 41 I/O O
|
||||
(unused) 0 0 /\2 3 FB5_12 42 I/O (b)
|
||||
(unused) 0 0 \/5 0 FB5_13 (b) (b)
|
||||
nADoutLE1 14 9<- 0 0 FB5_14 43 I/O O
|
||||
ALE0S 1 0 /\4 0 FB5_15 46 I/O (b)
|
||||
(unused) 0 0 \/5 0 FB5_16 (b) (b)
|
||||
iobs/IORW1 16 11<- 0 0 FB5_17 49 I/O (b)
|
||||
(unused) 0 0 /\5 0 FB5_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: A_FSB<13> 8: A_FSB<21> 15: iobs/IORW1
|
||||
2: A_FSB<14> 9: A_FSB<22> 16: iobs/Once
|
||||
3: A_FSB<16> 10: A_FSB<23> 17: iobs/PS_FSM_FFd1
|
||||
4: A_FSB<17> 11: IORW0 18: iobs/PS_FSM_FFd2
|
||||
5: A_FSB<18> 12: cs/nOverlay1 19: nADoutLE1
|
||||
6: A_FSB<19> 13: fsb/ASrf 20: nAS_FSB
|
||||
7: A_FSB<20> 14: iobs/IOACTr 21: nWE_FSB
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
IORW0 XXXXXXXXXXXXX.XXXXXXX................... 20
|
||||
iobs/PS_FSM_FFd2 XXXXXXXXXX.XXX.XXXXXX................... 19
|
||||
nDinOE ......XXXX.........XX................... 6
|
||||
IOREQ XXXXXXXXXX.XXX.XXXXXX................... 19
|
||||
nROMCS ......XXXX.X............................ 5
|
||||
nADoutLE1 XXXXXXXXXX.XX..XXXXXX................... 18
|
||||
ALE0S ................XX...................... 2
|
||||
iobs/IORW1 XXXXXXXXXX.XX.XXXXXXX................... 19
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB6 ***********************************
|
||||
Number of function block inputs used/remaining: 41/13
|
||||
Number of signals used by logic mapping into function block: 41
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
iobs/Once 17 12<- 0 0 FB6_1 (b) (b)
|
||||
nCAS 1 0 /\4 0 FB6_2 74 I/O O
|
||||
fsb/BERR0r 3 0 \/2 0 FB6_3 (b) (b)
|
||||
ram/RS_FSM_FFd3 11 6<- 0 0 FB6_4 (b) (b)
|
||||
TimeoutB 3 2<- /\4 0 FB6_5 76 I/O I
|
||||
nOE 1 0 /\2 2 FB6_6 77 I/O O
|
||||
TimeoutA 3 0 0 2 FB6_7 (b) (b)
|
||||
ram/RS_FSM_FFd1 5 0 0 0 FB6_8 78 I/O I
|
||||
nRAMLWE 1 0 \/3 1 FB6_9 79 I/O O
|
||||
ram/RS_FSM_FFd2 13 8<- 0 0 FB6_10 (b) (b)
|
||||
(unused) 0 0 /\5 0 FB6_11 80 I/O I
|
||||
nRAMUWE 1 0 \/4 0 FB6_12 81 I/O O
|
||||
iobs/Load1 14 9<- 0 0 FB6_13 (b) (b)
|
||||
(unused) 0 0 /\5 0 FB6_14 82 I/O I
|
||||
nROMWE 1 0 0 4 FB6_15 85 I/O O
|
||||
(unused) 0 0 0 5 FB6_16 (b)
|
||||
nVPA_FSB 1 0 \/3 1 FB6_17 86 I/O O
|
||||
(unused) 0 0 \/5 0 FB6_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: A_FSB<13> 15: cnt/RefCnt<2> 29: nADoutLE1
|
||||
2: A_FSB<14> 16: cnt/RefCnt<3> 30: nAS_FSB
|
||||
3: A_FSB<16> 17: cnt/RefCnt<4> 31: nLDS_FSB
|
||||
4: A_FSB<17> 18: cnt/RefCnt<5> 32: nUDS_FSB
|
||||
5: A_FSB<18> 19: cnt/RefCnt<6> 33: nWE_FSB
|
||||
6: A_FSB<19> 20: cnt/RefCnt<7> 34: ram/BACTr
|
||||
7: A_FSB<20> 21: cnt/RefDone 35: ram/Once
|
||||
8: A_FSB<21> 22: cs/nOverlay1 36: ram/RAMDIS1
|
||||
9: A_FSB<22> 23: fsb/ASrf 37: ram/RAMDIS2
|
||||
10: A_FSB<23> 24: fsb/BERR0r 38: ram/RASEL
|
||||
11: TimeoutA 25: fsb/VPA 39: ram/RS_FSM_FFd1
|
||||
12: TimeoutB 26: iobs/Once 40: ram/RS_FSM_FFd2
|
||||
13: cnt/RefCnt<0> 27: iobs/PS_FSM_FFd1 41: ram/RS_FSM_FFd3
|
||||
14: cnt/RefCnt<1> 28: iobs/PS_FSM_FFd2
|
||||
|
||||
Signal 1 2 3 4 5 FB
|
||||
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
||||
iobs/Once XXXXXXXXXX...........XX..XXXXX..X................. 18
|
||||
nCAS .....................................X............ 1
|
||||
fsb/BERR0r ......XXXX.X..........XX.....X.................... 8
|
||||
ram/RS_FSM_FFd3 .......XXX.......XXXXXX......X....X...XXX......... 14
|
||||
TimeoutB ..........XXXXXXXXXX..X......X.................... 12
|
||||
nOE .............................X..X................. 2
|
||||
TimeoutA ..........X.XXXXXXXX..X......X.................... 11
|
||||
ram/RS_FSM_FFd1 .......XXX...........XX......X....X...XXX......... 10
|
||||
nRAMLWE .............................XX.X..XX............. 5
|
||||
ram/RS_FSM_FFd2 .......XXX.......XXXXXX......X...X....XXX......... 14
|
||||
nRAMUWE .............................X.XX..XX............. 5
|
||||
iobs/Load1 XXXXXXXXXX...........XX..XXXXX..X................. 18
|
||||
nROMWE .............................X..X................. 2
|
||||
nVPA_FSB ........................X....X.................... 2
|
||||
0----+----1----+----2----+----3----+----4----+----5
|
||||
0 0 0 0 0
|
||||
*********************************** FB7 ***********************************
|
||||
Number of function block inputs used/remaining: 20/34
|
||||
Number of signals used by logic mapping into function block: 20
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
iobm/VPArr 1 0 0 4 FB7_1 (b) (b)
|
||||
RA<7> 2 0 0 3 FB7_2 50 I/O O
|
||||
iobm/VPArf 1 0 0 4 FB7_3 (b) (b)
|
||||
iobm/RESrr 1 0 0 4 FB7_4 (b) (b)
|
||||
iobm/RESrf 1 0 0 4 FB7_5 52 I/O I
|
||||
iobm/IOREQr 1 0 0 4 FB7_6 53 I/O I
|
||||
iobm/Er2 1 0 0 4 FB7_7 (b) (b)
|
||||
RA<8> 2 0 0 3 FB7_8 54 I/O O
|
||||
iobm/DTACKrr 1 0 0 4 FB7_9 55 I/O I
|
||||
iobm/DTACKrf 1 0 0 4 FB7_10 (b) (b)
|
||||
iobs/IOL1 2 0 0 3 FB7_11 56 I/O I
|
||||
RA<9> 2 0 0 3 FB7_12 58 I/O O
|
||||
iobm/ES<3> 3 0 0 2 FB7_13 (b) (b)
|
||||
iobm/ES<1> 3 0 0 2 FB7_14 59 I/O I
|
||||
iobm/ES<0> 3 0 0 2 FB7_15 60 I/O I
|
||||
iobm/ES<4> 4 0 0 1 FB7_16 (b) (b)
|
||||
RA<11> 1 0 0 4 FB7_17 61 I/O O
|
||||
iobm/ES<2> 5 0 0 0 FB7_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: A_FSB<17> 8: iobm/ES<0> 15: iobs/Load1
|
||||
2: A_FSB<18> 9: iobm/ES<1> 16: nDTACK_IOB
|
||||
3: A_FSB<19> 10: iobm/ES<2> 17: nLDS_FSB
|
||||
4: A_FSB<20> 11: iobm/ES<3> 18: nRES
|
||||
5: A_FSB<8> 12: iobm/ES<4> 19: nVPA_IOB
|
||||
6: A_FSB<9> 13: iobm/Er 20: ram/RASEL
|
||||
7: IOREQ 14: iobm/Er2
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
iobm/VPArr ..................X..................... 1
|
||||
RA<7> X...X..............X.................... 3
|
||||
iobm/VPArf ..................X..................... 1
|
||||
iobm/RESrr .................X...................... 1
|
||||
iobm/RESrf .................X...................... 1
|
||||
iobm/IOREQr ......X................................. 1
|
||||
iobm/Er2 ............X........................... 1
|
||||
RA<8> .X...X.............X.................... 3
|
||||
iobm/DTACKrr ...............X........................ 1
|
||||
iobm/DTACKrf ...............X........................ 1
|
||||
iobs/IOL1 ..............X.X....................... 2
|
||||
RA<9> ..XX...............X.................... 3
|
||||
iobm/ES<3> .......XXXX.XX.......................... 6
|
||||
iobm/ES<1> .......XX...XX.......................... 4
|
||||
iobm/ES<0> .......XXXXXXX.......................... 7
|
||||
iobm/ES<4> .......XXXXXXX.......................... 7
|
||||
RA<11> ..X..................................... 1
|
||||
iobm/ES<2> .......XXXXXXX.......................... 7
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB8 ***********************************
|
||||
Number of function block inputs used/remaining: 13/41
|
||||
Number of signals used by logic mapping into function block: 13
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
(unused) 0 0 0 5 FB8_1 (b)
|
||||
RA<10> 1 0 0 4 FB8_2 63 I/O O
|
||||
(unused) 0 0 0 5 FB8_3 (b)
|
||||
(unused) 0 0 0 5 FB8_4 (b)
|
||||
(unused) 0 0 0 5 FB8_5 64 I/O I
|
||||
(unused) 0 0 0 5 FB8_6 65 I/O I
|
||||
(unused) 0 0 0 5 FB8_7 (b)
|
||||
nADoutLE0 1 0 0 4 FB8_8 66 I/O O
|
||||
(unused) 0 0 0 5 FB8_9 67 I/O I
|
||||
ram/BACTr 1 0 0 4 FB8_10 (b) (b)
|
||||
iobs/IOACTr 1 0 0 4 FB8_11 68 I/O I
|
||||
nAoutOE 0 0 0 5 FB8_12 70 I/O O
|
||||
iobm/Er 1 0 0 4 FB8_13 (b) (b)
|
||||
fsb/ASrf 1 0 0 4 FB8_14 71 I/O I
|
||||
cnt/RefCnt<0> 0 0 0 5 FB8_15 72 I/O I
|
||||
RefAck 1 0 0 4 FB8_16 (b) (b)
|
||||
nDinLE 1 0 0 4 FB8_17 73 I/O O
|
||||
iobs/IOU1 2 0 0 3 FB8_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: ALE0M 6: fsb/ASrf 10: nAS_FSB
|
||||
2: ALE0S 7: iobm/IOS_FSM_FFd3 11: nUDS_FSB
|
||||
3: A_FSB<21> 8: iobm/IOS_FSM_FFd4 12: ram/RS_FSM_FFd1
|
||||
4: E_IOB 9: iobs/Load1 13: ram/RS_FSM_FFd2
|
||||
5: IOACT
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
RA<10> ..X..................................... 1
|
||||
nADoutLE0 XX...................................... 2
|
||||
ram/BACTr .....X...X.............................. 2
|
||||
iobs/IOACTr ....X................................... 1
|
||||
nAoutOE ........................................ 0
|
||||
iobm/Er ...X.................................... 1
|
||||
fsb/ASrf .........X.............................. 1
|
||||
cnt/RefCnt<0> ........................................ 0
|
||||
RefAck ...........XX........................... 2
|
||||
nDinLE ......XX................................ 2
|
||||
iobs/IOU1 ........X.X............................. 2
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
******************************* Equations ********************************
|
||||
|
||||
********** Mapped Logic **********
|
||||
|
||||
|
||||
$OpTx$FX_DC$603 <= ((NOT TimeoutB)
|
||||
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20)));
|
||||
|
||||
|
|
@ -0,0 +1,471 @@
|
|||
Release 14.7 - xst P.20131013 (nt)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
--> Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.08 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.08 secs
|
||||
|
||||
--> Reading design: MXSE.prj
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Synthesis Options Summary
|
||||
2) HDL Compilation
|
||||
3) Design Hierarchy Analysis
|
||||
4) HDL Analysis
|
||||
5) HDL Synthesis
|
||||
5.1) HDL Synthesis Report
|
||||
6) Advanced HDL Synthesis
|
||||
6.1) Advanced HDL Synthesis Report
|
||||
7) Low Level Synthesis
|
||||
8) Partition Report
|
||||
9) Final Report
|
||||
|
||||
=========================================================================
|
||||
* Synthesis Options Summary *
|
||||
=========================================================================
|
||||
---- Source Parameters
|
||||
Input File Name : "MXSE.prj"
|
||||
Input Format : mixed
|
||||
Ignore Synthesis Constraint File : NO
|
||||
|
||||
---- Target Parameters
|
||||
Output File Name : "MXSE"
|
||||
Output Format : NGC
|
||||
Target Device : XC9500XL CPLDs
|
||||
|
||||
---- Source Options
|
||||
Top Module Name : MXSE
|
||||
Automatic FSM Extraction : YES
|
||||
FSM Encoding Algorithm : Auto
|
||||
Safe Implementation : No
|
||||
Mux Extraction : Yes
|
||||
Resource Sharing : YES
|
||||
|
||||
---- Target Options
|
||||
Add IO Buffers : YES
|
||||
MACRO Preserve : YES
|
||||
XOR Preserve : YES
|
||||
Equivalent register Removal : YES
|
||||
|
||||
---- General Options
|
||||
Optimization Goal : Speed
|
||||
Optimization Effort : 1
|
||||
Keep Hierarchy : Yes
|
||||
Netlist Hierarchy : As_Optimized
|
||||
RTL Output : Yes
|
||||
Hierarchy Separator : /
|
||||
Bus Delimiter : <>
|
||||
Case Specifier : Maintain
|
||||
Verilog 2001 : YES
|
||||
|
||||
---- Other Options
|
||||
Clock Enable : YES
|
||||
wysiwyg : NO
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling verilog file "../RAM.v" in library work
|
||||
Compiling verilog file "../IOBS.v" in library work
|
||||
Module <RAM> compiled
|
||||
Compiling verilog file "../IOBM.v" in library work
|
||||
Module <IOBS> compiled
|
||||
Compiling verilog file "../FSB.v" in library work
|
||||
Module <IOBM> compiled
|
||||
Compiling verilog file "../CS.v" in library work
|
||||
Module <FSB> compiled
|
||||
Compiling verilog file "../CNT.v" in library work
|
||||
Module <CS> compiled
|
||||
Compiling verilog file "../MXSE.v" in library work
|
||||
Module <CNT> compiled
|
||||
Module <MXSE> compiled
|
||||
No errors in compilation
|
||||
Analysis of file <"MXSE.prj"> succeeded.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Design Hierarchy Analysis *
|
||||
=========================================================================
|
||||
Analyzing hierarchy for module <MXSE> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <CS> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <RAM> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <IOBS> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <IOBM> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <CNT> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <FSB> in library <work>.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing top module <MXSE>.
|
||||
Module <MXSE> is correct for synthesis.
|
||||
|
||||
Analyzing module <CS> in library <work>.
|
||||
Module <CS> is correct for synthesis.
|
||||
|
||||
Analyzing module <RAM> in library <work>.
|
||||
Module <RAM> is correct for synthesis.
|
||||
|
||||
Analyzing module <IOBS> in library <work>.
|
||||
Module <IOBS> is correct for synthesis.
|
||||
|
||||
Analyzing module <IOBM> in library <work>.
|
||||
Module <IOBM> is correct for synthesis.
|
||||
|
||||
Analyzing module <CNT> in library <work>.
|
||||
Module <CNT> is correct for synthesis.
|
||||
|
||||
Analyzing module <FSB> in library <work>.
|
||||
Module <FSB> is correct for synthesis.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Performing bidirectional port resolution...
|
||||
|
||||
Synthesizing Unit <CS>.
|
||||
Related source file is "../CS.v".
|
||||
Found 1-bit register for signal <nOverlay0>.
|
||||
Found 1-bit register for signal <nOverlay1>.
|
||||
Summary:
|
||||
inferred 2 D-type flip-flop(s).
|
||||
Unit <CS> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <RAM>.
|
||||
Related source file is "../RAM.v".
|
||||
Found finite state machine <FSM_0> for signal <RS>.
|
||||
-----------------------------------------------------------------------
|
||||
| States | 8 |
|
||||
| Transitions | 18 |
|
||||
| Inputs | 6 |
|
||||
| Outputs | 9 |
|
||||
| Clock | CLK (rising_edge) |
|
||||
| Power Up State | 000 |
|
||||
| Encoding | automatic |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 1-bit register for signal <nCAS>.
|
||||
Found 1-bit register for signal <BACTr>.
|
||||
Found 1-bit register for signal <Once>.
|
||||
Found 1-bit register for signal <RAMDIS1>.
|
||||
Found 1-bit register for signal <RAMDIS2>.
|
||||
Found 1-bit register for signal <RAMReady>.
|
||||
Found 1-bit register for signal <RASEL>.
|
||||
Found 1-bit register for signal <RefRAS>.
|
||||
Summary:
|
||||
inferred 1 Finite State Machine(s).
|
||||
inferred 6 D-type flip-flop(s).
|
||||
Unit <RAM> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <IOBS>.
|
||||
Related source file is "../IOBS.v".
|
||||
Found finite state machine <FSM_1> for signal <PS>.
|
||||
-----------------------------------------------------------------------
|
||||
| States | 4 |
|
||||
| Transitions | 10 |
|
||||
| Inputs | 5 |
|
||||
| Outputs | 5 |
|
||||
| Clock | CLK (rising_edge) |
|
||||
| Power Up State | 00 |
|
||||
| Encoding | automatic |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 1-bit register for signal <BERR>.
|
||||
Found 1-bit register for signal <IOREQ>.
|
||||
Found 1-bit register for signal <IORW0>.
|
||||
Found 1-bit register for signal <IOL0>.
|
||||
Found 1-bit register for signal <IOU0>.
|
||||
Found 1-bit register for signal <ALE0>.
|
||||
Found 1-bit register for signal <ALE1>.
|
||||
Found 1-bit register for signal <IOACTr>.
|
||||
Found 1-bit register for signal <IOL1>.
|
||||
Found 1-bit register for signal <IOReady>.
|
||||
Found 1-bit register for signal <IORW1>.
|
||||
Found 1-bit register for signal <IOU1>.
|
||||
Found 1-bit register for signal <Load1>.
|
||||
Found 1-bit register for signal <Once>.
|
||||
Summary:
|
||||
inferred 1 Finite State Machine(s).
|
||||
inferred 9 D-type flip-flop(s).
|
||||
Unit <IOBS> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <IOBM>.
|
||||
Related source file is "../IOBM.v".
|
||||
Found finite state machine <FSM_2> for signal <IOS>.
|
||||
-----------------------------------------------------------------------
|
||||
| States | 8 |
|
||||
| Transitions | 15 |
|
||||
| Inputs | 6 |
|
||||
| Outputs | 9 |
|
||||
| Clock | C16M (rising_edge) |
|
||||
| Power Up State | 000 |
|
||||
| Encoding | automatic |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 1-bit register for signal <IOBERR>.
|
||||
Found 1-bit register for signal <IOACT>.
|
||||
Found 1-bit register for signal <nAS>.
|
||||
Found 1-bit register for signal <nLDS>.
|
||||
Found 1-bit register for signal <nUDS>.
|
||||
Found 1-bit register for signal <nDinLE>.
|
||||
Found 1-bit register for signal <nDoutOE>.
|
||||
Found 1-bit register for signal <ALE0>.
|
||||
Found 1-bit register for signal <nVMA>.
|
||||
Found 1-bit register for signal <BERRrf>.
|
||||
Found 1-bit register for signal <BERRrr>.
|
||||
Found 1-bit register for signal <DTACKrf>.
|
||||
Found 1-bit register for signal <DTACKrr>.
|
||||
Found 1-bit register for signal <Er>.
|
||||
Found 1-bit register for signal <Er2>.
|
||||
Found 5-bit up counter for signal <ES>.
|
||||
Found 1-bit register for signal <ETACK>.
|
||||
Found 1-bit register for signal <IOREQr>.
|
||||
Found 1-bit register for signal <RESrf>.
|
||||
Found 1-bit register for signal <RESrr>.
|
||||
Found 1-bit register for signal <VPArf>.
|
||||
Found 1-bit register for signal <VPArr>.
|
||||
Summary:
|
||||
inferred 1 Finite State Machine(s).
|
||||
inferred 1 Counter(s).
|
||||
inferred 20 D-type flip-flop(s).
|
||||
Unit <IOBM> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <CNT>.
|
||||
Related source file is "../CNT.v".
|
||||
Found 1-bit register for signal <TimeoutA>.
|
||||
Found 1-bit register for signal <TimeoutB>.
|
||||
Found 8-bit up counter for signal <RefCnt>.
|
||||
Found 1-bit register for signal <RefDone>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
Unit <CNT> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <FSB>.
|
||||
Related source file is "../FSB.v".
|
||||
Found 1-bit register for signal <nDTACK>.
|
||||
Found 1-bit register for signal <ASrf>.
|
||||
Found 1-bit register for signal <BERR0r>.
|
||||
Found 1-bit register for signal <BERR1r>.
|
||||
Found 1-bit register for signal <Ready0r>.
|
||||
Found 1-bit register for signal <Ready1r>.
|
||||
Found 1-bit register for signal <Ready2r>.
|
||||
Found 1-bit register for signal <VPA>.
|
||||
Summary:
|
||||
inferred 1 D-type flip-flop(s).
|
||||
Unit <FSB> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <MXSE>.
|
||||
Related source file is "../MXSE.v".
|
||||
Unit <MXSE> synthesized.
|
||||
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Counters : 2
|
||||
5-bit up counter : 1
|
||||
8-bit up counter : 1
|
||||
# Registers : 56
|
||||
1-bit register : 56
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Analyzing FSM <FSM_2> for best encoding.
|
||||
Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:8]> with one-hot encoding.
|
||||
-------------------
|
||||
State | Encoding
|
||||
-------------------
|
||||
000 | 00000001
|
||||
001 | 00000010
|
||||
010 | 00000100
|
||||
011 | 00001000
|
||||
100 | 00010000
|
||||
101 | 00100000
|
||||
110 | 01000000
|
||||
111 | 10000000
|
||||
-------------------
|
||||
Analyzing FSM <FSM_1> for best encoding.
|
||||
Optimizing FSM <iobs/PS/FSM> on signal <PS[1:2]> with johnson encoding.
|
||||
-------------------
|
||||
State | Encoding
|
||||
-------------------
|
||||
00 | 00
|
||||
11 | 01
|
||||
10 | 11
|
||||
01 | 10
|
||||
-------------------
|
||||
Analyzing FSM <FSM_0> for best encoding.
|
||||
Optimizing FSM <ram/RS/FSM> on signal <RS[1:3]> with user encoding.
|
||||
-------------------
|
||||
State | Encoding
|
||||
-------------------
|
||||
000 | 000
|
||||
010 | 010
|
||||
101 | 101
|
||||
001 | 001
|
||||
011 | 011
|
||||
100 | 100
|
||||
111 | 111
|
||||
110 | 110
|
||||
-------------------
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# FSMs : 3
|
||||
# Counters : 2
|
||||
5-bit up counter : 1
|
||||
8-bit up counter : 1
|
||||
# Registers : 38
|
||||
Flip-Flops : 38
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Low Level Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Optimizing unit <MXSE> ...
|
||||
|
||||
Optimizing unit <CS> ...
|
||||
implementation constraint: INIT=r : nOverlay0
|
||||
implementation constraint: INIT=r : nOverlay1
|
||||
|
||||
Optimizing unit <RAM> ...
|
||||
implementation constraint: INIT=r : RAMReady
|
||||
implementation constraint: INIT=r : RASEL
|
||||
implementation constraint: INIT=r : RAMDIS1
|
||||
implementation constraint: INIT=r : RefRAS
|
||||
implementation constraint: INIT=r : RAMDIS2
|
||||
implementation constraint: INIT=r : Once
|
||||
implementation constraint: INIT=r : RS_FSM_FFd1
|
||||
implementation constraint: INIT=r : RS_FSM_FFd2
|
||||
implementation constraint: INIT=r : RS_FSM_FFd3
|
||||
|
||||
Optimizing unit <IOBS> ...
|
||||
implementation constraint: INIT=r : IOACTr
|
||||
implementation constraint: INIT=r : Once
|
||||
implementation constraint: INIT=r : PS_FSM_FFd1
|
||||
implementation constraint: INIT=r : PS_FSM_FFd2
|
||||
|
||||
Optimizing unit <FSB> ...
|
||||
implementation constraint: INIT=r : ASrf
|
||||
|
||||
Optimizing unit <IOBM> ...
|
||||
implementation constraint: INIT=r : ETACK
|
||||
implementation constraint: INIT=r : IOREQr
|
||||
implementation constraint: INIT=r : IOS_FSM_FFd1
|
||||
implementation constraint: INIT=r : IOS_FSM_FFd2
|
||||
implementation constraint: INIT=r : IOS_FSM_FFd3
|
||||
implementation constraint: INIT=r : IOS_FSM_FFd4
|
||||
implementation constraint: INIT=r : IOS_FSM_FFd5
|
||||
implementation constraint: INIT=r : IOS_FSM_FFd6
|
||||
implementation constraint: INIT=r : IOS_FSM_FFd7
|
||||
implementation constraint: INIT=s : IOS_FSM_FFd8
|
||||
|
||||
Optimizing unit <CNT> ...
|
||||
implementation constraint: INIT=r : RefDone
|
||||
implementation constraint: INIT=r : RefCnt_7
|
||||
implementation constraint: INIT=r : RefCnt_6
|
||||
implementation constraint: INIT=r : RefCnt_5
|
||||
implementation constraint: INIT=r : RefCnt_4
|
||||
implementation constraint: INIT=r : RefCnt_3
|
||||
implementation constraint: INIT=r : RefCnt_2
|
||||
implementation constraint: INIT=r : RefCnt_1
|
||||
implementation constraint: INIT=r : RefCnt_0
|
||||
|
||||
=========================================================================
|
||||
* Partition Report *
|
||||
=========================================================================
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
=========================================================================
|
||||
* Final Report *
|
||||
=========================================================================
|
||||
Final Results
|
||||
RTL Top Level Output File Name : MXSE.ngr
|
||||
Top Level Output File Name : MXSE
|
||||
Output Format : NGC
|
||||
Optimization Goal : Speed
|
||||
Keep Hierarchy : Yes
|
||||
Target Technology : XC9500XL CPLDs
|
||||
Macro Preserve : YES
|
||||
XOR Preserve : YES
|
||||
Clock Enable : YES
|
||||
wysiwyg : NO
|
||||
|
||||
Design Statistics
|
||||
# IOs : 67
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 566
|
||||
# AND2 : 162
|
||||
# AND3 : 21
|
||||
# AND4 : 15
|
||||
# AND5 : 1
|
||||
# AND6 : 3
|
||||
# AND8 : 3
|
||||
# GND : 6
|
||||
# INV : 238
|
||||
# OR2 : 91
|
||||
# OR3 : 8
|
||||
# OR4 : 5
|
||||
# VCC : 1
|
||||
# XOR2 : 12
|
||||
# FlipFlops/Latches : 82
|
||||
# FD : 56
|
||||
# FDCE : 26
|
||||
# IO Buffers : 67
|
||||
# IBUF : 35
|
||||
# OBUF : 32
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 3.00 secs
|
||||
Total CPU time to Xst completion: 2.37 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 231768 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 0 ( 0 filtered)
|
||||
Number of infos : 0 ( 0 filtered)
|
||||
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:IOBERR.D:666
|
||||
TS_CLK2X_IOB:FROM:IOBERR.Q:TO:IOBERR.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:IOBERR.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:IOBERR.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:IOBERR.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/DTACKrr.Q:TO:IOBERR.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:IOBERR.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:IOBERR.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:IOBERR.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd3.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:iobm/IOS_FSM_FFd3.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:iobm/IOS_FSM_FFd3.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:iobm/IOS_FSM_FFd3.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:iobm/IOS_FSM_FFd3.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/DTACKrr.Q:TO:iobm/IOS_FSM_FFd3.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:iobm/IOS_FSM_FFd3.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:iobm/IOS_FSM_FFd3.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:iobm/IOS_FSM_FFd3.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd8.Q:TO:iobm/IOS_FSM_FFd7.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOREQr.Q:TO:iobm/IOS_FSM_FFd7.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd8.Q:TO:iobm/IOS_FSM_FFd8.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd1.Q:TO:iobm/IOS_FSM_FFd8.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOREQr.Q:TO:iobm/IOS_FSM_FFd8.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd7.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd8.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd5.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd6.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:IOACT.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/DTACKrr.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:IOACT.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:IOACT.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:IOACT.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOREQr.Q:TO:IOACT.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:iobm/IOS_FSM_FFd2.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ETACK.Q:TO:iobm/IOS_FSM_FFd2.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/BERRrr.Q:TO:iobm/IOS_FSM_FFd2.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/BERRrf.Q:TO:iobm/IOS_FSM_FFd2.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/DTACKrr.Q:TO:iobm/IOS_FSM_FFd2.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/DTACKrf.Q:TO:iobm/IOS_FSM_FFd2.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/RESrr.Q:TO:iobm/IOS_FSM_FFd2.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/RESrf.Q:TO:iobm/IOS_FSM_FFd2.D:333
|
||||
TS_CLK_FSB:FROM:cs/nOverlay0.Q:TO:cs/nOverlay1.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:cs/nOverlay1.CE:200
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/Once.D:200
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:iobs/Once.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/Once.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/Once.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/Once.D:400
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/Once.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/Once.D:200
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/Once.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/Once.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/Once.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/Once.D:400
|
||||
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/Once.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:RefAck.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:cnt/RefDone.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:BERR_IOBS.D:200
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:BERR_IOBS.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:BERR_IOBS.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:BERR_IOBS.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:BERR_IOBS.D:400
|
||||
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:BERR_IOBS.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:IORW0.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IORW1.Q:TO:IORW0.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:IORW0.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:IORW0.D:200
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:IORW0.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:IORW0.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IORW0.D:400
|
||||
TS_CLK_FSB:FROM:IORW0.Q:TO:IORW0.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:TimeoutA.D:200
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:TimeoutA.Q:TO:TimeoutA.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:cs/nOverlay0.D:200
|
||||
TS_CLK_FSB:FROM:cs/nOverlay0.Q:TO:cs/nOverlay0.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:IOL0.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOL1.Q:TO:IOL0.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IOL0.CE:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:IOL0.CE:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:IOU0.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOU1.Q:TO:IOU0.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IOU0.CE:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:IOU0.CE:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:TimeoutB.D:200
|
||||
TS_CLK_FSB:FROM:TimeoutA.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:TimeoutB.Q:TO:TimeoutB.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/BERR0r.D:200
|
||||
TS_CLK_FSB:FROM:TimeoutB.Q:TO:fsb/BERR0r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/BERR0r.Q:TO:fsb/BERR0r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/BERR1r.D:200
|
||||
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:fsb/BERR1r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/BERR1r.Q:TO:fsb/BERR1r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/Ready0r.D:200
|
||||
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:fsb/Ready0r.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/Ready0r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready0r.Q:TO:fsb/Ready0r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/Ready1r.D:200
|
||||
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:fsb/Ready1r.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:fsb/Ready1r.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/Ready1r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:fsb/Ready1r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/Ready2r.D:200
|
||||
TS_CLK_FSB:FROM:TimeoutA.Q:TO:fsb/Ready2r.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/Ready2r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready2r.Q:TO:fsb/Ready2r.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:fsb/VPA.D:200
|
||||
TS_CLK_FSB:FROM:fsb/BERR0r.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:fsb/BERR1r.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:TimeoutB.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready0r.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready2r.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:TimeoutA.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:fsb/VPA.Q:TO:fsb/VPA.D:400
|
||||
TS_CLK_FSB:FROM:iobs/Load1.Q:TO:iobs/IOL1.CE:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:iobs/IORW1.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/IORW1.D:200
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/IORW1.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/IORW1.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/IORW1.D:400
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/IORW1.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IORW1.Q:TO:iobs/IORW1.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/IOReady.D:200
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/IOReady.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/IOReady.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:iobs/IOReady.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/IOReady.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:iobs/IOReady.D:400
|
||||
TS_CLK_FSB:FROM:iobs/Load1.Q:TO:iobs/IOU1.CE:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RAMDIS2.D:200
|
||||
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:ram/RAMDIS2.Q:TO:ram/RAMDIS2.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:nDTACK_FSB_OBUF.D:200
|
||||
TS_CLK_FSB:FROM:fsb/BERR0r.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:fsb/BERR1r.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:BERR_IOBS.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:TimeoutB.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready0r.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:ram/RAMReady.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready2r.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:TimeoutA.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:fsb/Ready1r.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOReady.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:nDTACK_FSB_OBUF.Q:TO:nDTACK_FSB_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RASEL.D:200
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RASEL.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd2.D:200
|
||||
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RS_FSM_FFd1.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RS_FSM_FFd1.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RS_FSM_FFd1.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd1.D:200
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RS_FSM_FFd1.D:400
|
||||
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RS_FSM_FFd1.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd3.D:200
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RS_FSM_FFd3.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/PS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:iobs/PS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/PS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/PS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:iobs/PS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/PS_FSM_FFd2.D:200
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/PS_FSM_FFd2.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/PS_FSM_FFd1.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:iobs/PS_FSM_FFd1.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/PS_FSM_FFd1.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<0>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefCnt<5>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<5>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<5>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<5>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<5>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<5>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/RefCnt<6>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefCnt<6>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<6>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<6>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<6>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<6>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<6>.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/BACTr.D:200
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<1>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<1>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<2>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<2>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<2>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<3>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<3>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<3>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<3>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<4>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<4>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<4>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<4>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<4>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:cnt/RefCnt<7>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:cnt/RefCnt<7>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:cnt/RefCnt<7>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<4>.Q:TO:cnt/RefCnt<7>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<3>.Q:TO:cnt/RefCnt<7>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<2>.Q:TO:cnt/RefCnt<7>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<0>.Q:TO:cnt/RefCnt<7>.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<1>.Q:TO:cnt/RefCnt<7>.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:RefAck.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:RefAck.D:400
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:iobs/Load1.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:iobs/Load1.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:iobs/Load1.D:200
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:iobs/Load1.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:iobs/Load1.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:iobs/Load1.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:ALE0S.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:ALE0S.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:IOREQ.D:400
|
||||
TS_CLK_FSB:FROM:iobs/IOACTr.Q:TO:IOREQ.D:400
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:IOREQ.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:IOREQ.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:IOREQ.D:200
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:IOREQ.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:IOREQ.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RAMDIS1.D:200
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RAMDIS1.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<5>.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefDone.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<6>.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:cnt/RefCnt<7>.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd1.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:ram/Once.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:ram/BACTr.Q:TO:ram/RAMReady.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:ram/RAMReady.D:200
|
||||
TS_CLK_FSB:FROM:ram/RASEL.Q:TO:nCAS_OBUF.D:200
|
||||
TS_CLK_FSB:FROM:nADoutLE1_OBUF.Q:TO:nADoutLE1_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:cs/nOverlay1.Q:TO:nADoutLE1_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:fsb/ASrf.Q:TO:nADoutLE1_OBUF.D:200
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd1.Q:TO:nADoutLE1_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:iobs/PS_FSM_FFd2.Q:TO:nADoutLE1_OBUF.D:400
|
||||
TS_CLK_FSB:FROM:iobs/Once.Q:TO:nADoutLE1_OBUF.D:400
|
||||
TS_CLK2X_IOB:FROM:nVMA_IOB_OBUF.Q:TO:nVMA_IOB_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:IOACT.Q:TO:nVMA_IOB_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:nVMA_IOB_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:nVMA_IOB_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:nVMA_IOB_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/VPArr.Q:TO:nVMA_IOB_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/VPArf.Q:TO:nVMA_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:nVMA_IOB_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:nVMA_IOB_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<0>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<0>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<0>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<0>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<0>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<0>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<1>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<1>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<1>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<1>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<1>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<1>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<2>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<2>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<2>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<2>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<2>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<2>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<3>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<3>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<3>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<3>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<3>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<3>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ES<4>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ES<4>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ES<4>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ES<4>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ES<4>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/Er2.Q:TO:iobm/ES<4>.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd5.Q:TO:iobm/IOS_FSM_FFd4.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd6.Q:TO:iobm/IOS_FSM_FFd5.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd7.Q:TO:iobm/IOS_FSM_FFd6.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<0>.Q:TO:iobm/ETACK.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<1>.Q:TO:iobm/ETACK.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<2>.Q:TO:iobm/ETACK.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<3>.Q:TO:iobm/ETACK.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/ES<4>.Q:TO:iobm/ETACK.D:666
|
||||
TS_CLK2X_IOB:FROM:nVMA_IOB_OBUF.Q:TO:iobm/ETACK.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:ALE0M.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd5.Q:TO:ALE0M.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd6.Q:TO:ALE0M.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd7.Q:TO:ALE0M.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:ALE0M.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd8.Q:TO:ALE0M.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOREQr.Q:TO:ALE0M.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:iobm/IOS_FSM_FFd1.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nAS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd5.Q:TO:nAS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nAS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd6.Q:TO:nAS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd7.Q:TO:nAS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nDinLE_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nDinLE_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nDoutOE_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd2.Q:TO:nDoutOE_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd5.Q:TO:nDoutOE_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nDoutOE_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd6.Q:TO:nDoutOE_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd7.Q:TO:nDoutOE_OBUF.D:666
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd6.Q:TO:nLDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd7.Q:TO:nLDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nLDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nLDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd5.Q:TO:nLDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd6.Q:TO:nUDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd7.Q:TO:nUDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd3.Q:TO:nUDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd4.Q:TO:nUDS_IOB_OBUF.D:333
|
||||
TS_CLK2X_IOB:FROM:iobm/IOS_FSM_FFd5.Q:TO:nUDS_IOB_OBUF.D:333
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,280 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="../RAM.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="../MXSE.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="../MXSE.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="../IOBS.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="../IOBM.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="../FSB.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="../CS.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="../CNT.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="../test/t_fsb_dtack.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="115"/>
|
||||
</file>
|
||||
<file xil_pn:name="../test/t_fsb_vpa.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="125"/>
|
||||
</file>
|
||||
<file xil_pn:name="../test/t_cs.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="126"/>
|
||||
</file>
|
||||
<file xil_pn:name="../test/t_cnt.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="135"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc95144xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|MXSE" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../MXSE.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MXSE" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="MXSE" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="TQ100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MXSE_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="MXSE_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MXSE_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MXSE_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/t_cs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.t_cs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.t_cs" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|t_cs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="MXSE" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-10-07T05:04:51" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6B0FD4AE1C6643EAADF0E314B8CE9ACF" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
set -tmpdir "xst/projnav.tmp"
|
||||
set -xsthdpdir "xst"
|
||||
run
|
||||
-ifn MXSE.prj
|
||||
-ifmt mixed
|
||||
-ofn MXSE
|
||||
-ofmt NGC
|
||||
-p xc9500xl
|
||||
-top MXSE
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-keep_hierarchy Yes
|
||||
-netlist_hierarchy As_Optimized
|
||||
-rtlview Yes
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case Maintain
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-mux_extract Yes
|
||||
-resource_sharing YES
|
||||
-iobuf YES
|
||||
-pld_mp YES
|
||||
-pld_xp YES
|
||||
-pld_ce YES
|
||||
-wysiwyg NO
|
||||
-equivalent_register_removal YES
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<center><big><big><b>System Settings</b></big></big></center><br>
|
||||
<A NAME="Environment Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='3'><B> Environment Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Environment Variable</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PATHEXT</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Path</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\ispLEVER_Classic2_0\ispcpld\bin;<br>C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;<br>C:\ispLEVER_Classic2_0\active-hdl\BIN;<br>C:\WinAVR-20100110\bin;<br>C:\WinAVR-20100110\utils\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files\Microchip\xc8\v2.31\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Program Files\PuTTY\;<br>C:\Program Files\WinMerge;<br>C:\Program Files\dotnet\;<br>C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;<br>C:\Users\zanek\AppData\Local\GitHubDesktop\bin;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem;<br>C:\Users\zanek\.dotnet\tools;<br>C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_DSP</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_PLANAHEAD</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Synthesis Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ifn</td>
|
||||
<td> </td>
|
||||
<td>MXSE.prj</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ifmt</td>
|
||||
<td> </td>
|
||||
<td>mixed</td>
|
||||
<td>MIXED</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofn</td>
|
||||
<td> </td>
|
||||
<td>MXSE</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofmt</td>
|
||||
<td> </td>
|
||||
<td>NGC</td>
|
||||
<td>NGC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc9500xl</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-top</td>
|
||||
<td> </td>
|
||||
<td>MXSE</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_mode</td>
|
||||
<td>Optimization Goal</td>
|
||||
<td>Speed</td>
|
||||
<td>SPEED</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_level</td>
|
||||
<td>Optimization Effort</td>
|
||||
<td>1</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iuc</td>
|
||||
<td>Use synthesis Constraints File</td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-keep_hierarchy</td>
|
||||
<td>Keep Hierarchy</td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-netlist_hierarchy</td>
|
||||
<td>Netlist Hierarchy</td>
|
||||
<td>As_Optimized</td>
|
||||
<td>as_optimized</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rtlview</td>
|
||||
<td>Generate RTL Schematic</td>
|
||||
<td>Yes</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bus_delimiter</td>
|
||||
<td>Bus Delimiter</td>
|
||||
<td><></td>
|
||||
<td><></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-verilog2001</td>
|
||||
<td>Verilog 2001</td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_encoding</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-safe_implementation</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-resource_sharing</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iobuf</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-equivalent_register_removal</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Translation Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-dd</td>
|
||||
<td> </td>
|
||||
<td>_ngo</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc95144xl-TQ100-10</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-uc</td>
|
||||
<td> </td>
|
||||
<td>C:/Users/zanek/Documents/GitHub/SE-030/cpld/MXSE.ucf</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Operating System Information"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='3'><B> Operating System Information </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Operating System Information</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>CPU Architecture/Speed</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Host</td>
|
||||
<td>ZanePC</td>
|
||||
<td>ZanePC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Name</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
<td>Microsoft , 64-bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Release</td>
|
||||
<td>major release (build 9200)</td>
|
||||
<td>major release (build 9200)</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
</BODY> </HTML>
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
var tmpStr = "";
|
||||
var waitWin;
|
||||
|
||||
function openWait() {
|
||||
waitWin = window.open("wait.htm", "wait",
|
||||
"toolbar=no,location=no,"+
|
||||
"directories=no,status=no,menubar=no,scrollbars=no,"+
|
||||
"resizable=no,width=300,height=50" );
|
||||
}
|
||||
|
||||
function closeWait() { if (waitWin) waitWin.close(); }
|
||||
|
||||
function setMsg(msg){
|
||||
|
||||
parent.leftnav.setAppletMsg( msg );
|
||||
// now send it reload forces
|
||||
// call to applet paint
|
||||
location.reload();
|
||||
}
|
||||
|
||||
function getMsg(){
|
||||
|
||||
return( parent.leftnav.getAppletMsg() );
|
||||
}
|
||||
|
||||
function resetMsg(){ parent.leftnav.setAppletMsg(""); }
|
||||
|
||||
function printAppletPkg() {
|
||||
if( isNS() ){
|
||||
setMsg("cmd printPkg ");
|
||||
}
|
||||
else{
|
||||
document.ChipViewerApplet.PrintPkg();
|
||||
}
|
||||
}
|
||||
|
||||
function showAppletGraphicMC(mc) {
|
||||
if( isNS() ){
|
||||
setMsg("cmd showMac " + mc);
|
||||
}
|
||||
else{
|
||||
document.ChipViewerApplet.ShowMac(mc);
|
||||
}
|
||||
}
|
||||
|
||||
function ShowMC() { showAppletGraphicMC(tmpStr); }
|
||||
|
||||
function showAppletGraphicFB(fb) {
|
||||
if( isNS() ){
|
||||
setMsg("cmd showFB " + fb);
|
||||
}
|
||||
else{
|
||||
document.ChipViewerApplet.ShowFB(fb);
|
||||
}
|
||||
}
|
||||
|
||||
function showAppletGraphicPin(pin) {
|
||||
if( isNS() ){
|
||||
setMsg("cmd showPin " + pin);
|
||||
}
|
||||
else{
|
||||
document.ChipViewerApplet.ShowPin(pin);
|
||||
}
|
||||
}
|
||||
|
||||
function ShowFB() { showAppletGraphicFB(tmpStr); }
|
||||
|
||||
function isNS() {
|
||||
return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) < 5) ) ? true : false;
|
||||
}
|
||||
|
||||
function isIE(){
|
||||
var agt=navigator.userAgent.toLowerCase();
|
||||
return( ( (agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1) ) ? true: false );
|
||||
}
|
||||
|
||||
function waitUntilOK() {
|
||||
if (!waitWin) openWait();
|
||||
if (isNS()) {
|
||||
if (document.ChipViewerApplet.isActive()) closeWait();
|
||||
else settimeout("waitUntilOK()",100);
|
||||
}
|
||||
else {
|
||||
if (document.ChipViewerApplet.readyState == 4) closeWait();
|
||||
else settimeout("waitUntilOK()",100);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// check that the applet if file has been generated
|
||||
// this can only be done if the applets been loaded.
|
||||
function fileExists(fileName){
|
||||
|
||||
if( document.ChipViewerApplet.readyState != 4 ) {
|
||||
window.alert("Navigation disabled until the applet is loaded." );
|
||||
}
|
||||
if( isIE() ){
|
||||
if( parent.leftnav.getAppletPermission() == 1 ){
|
||||
if( document.ChipViewerApplet.TestFileExists(fileName) == 1 ){
|
||||
window.alert("file exist tests true" );
|
||||
return( true );
|
||||
}
|
||||
}
|
||||
else{
|
||||
window.alert("file exist returns true no permission" );
|
||||
return( true );
|
||||
}
|
||||
}
|
||||
else{
|
||||
return( true );
|
||||
}
|
||||
window.alert("file exist returns false" );
|
||||
return( false );
|
||||
}
|
||||
|
||||
|
||||
|
||||
function setPermission(){
|
||||
|
||||
if( isIE() ){
|
||||
if( document.ChipViewerApplet.granted() ){
|
||||
parent.leftnav.setAppletPermission();
|
||||
}
|
||||
}
|
||||
else{
|
||||
return( true );
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
<html>
|
||||
<head>
|
||||
<title></title>
|
||||
</head>
|
||||
<frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" col="*">
|
||||
<frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
|
||||
<frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
|
||||
<frame name="leftnav" src="leftnav.htm" noresize marginwidth="0" marginheight="0">
|
||||
<frame name="content" src="summary.htm">
|
||||
</frameset>
|
||||
<frame name="eqns" src="eqns.htm" scrolling="no">
|
||||
</frameset>
|
||||
</html>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,71 @@
|
|||
<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
|
||||
|
||||
<html>
|
||||
|
||||
<!--(==============================================================)-->
|
||||
<!--(Document created with RoboEditor. )============================-->
|
||||
<!--(==============================================================)-->
|
||||
|
||||
<head>
|
||||
|
||||
<title>Text Report</title>
|
||||
|
||||
<!--(Meta)==========================================================-->
|
||||
|
||||
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
|
||||
<meta name=generator-major-version content=0.1>
|
||||
<meta name=generator-minor-version content=1>
|
||||
<meta name=filetype content=kadov>
|
||||
<meta name=filetype-version content=1>
|
||||
<meta name=page-count content=1>
|
||||
<meta name=layout-height content=375>
|
||||
<meta name=layout-width content=798>
|
||||
<meta name=date content="05 1, 2002 4:24:59 PM">
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
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|
||||
p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
|
||||
|
||||
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|
||||
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|
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||||
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||||
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|
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|
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|
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|
||||
</script><style>
|
||||
<!--
|
||||
div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
|
||||
p.WebHelpNavBar {text-align:right;}
|
||||
-->
|
||||
</style>
|
||||
</head>
|
||||
|
||||
<!--(Body)==========================================================-->
|
||||
|
||||
|
||||
<body>
|
||||
|
||||
|
||||
<h1>Text Report</h1>
|
||||
|
||||
<p class="whs1">Selecting Text
|
||||
Report from the left-hand frame will give you a printable text version
|
||||
of the fitter report. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->It
|
||||
contains sections similar to those of the XML report (a summary section,
|
||||
errors and warnings, mapped logic, function blocks, function block details,
|
||||
a text-graphical display of the pinout, and a summary of compiler options),
|
||||
but it is not easily navigable. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->It
|
||||
is best to use the text report only when you need to print out a hard
|
||||
copy of the fitter results.</p>
|
||||
|
||||
</body>
|
||||
|
||||
</html>
|
||||
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|
||||
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|
|||
<html>
|
||||
<head>
|
||||
<script src="XilinxD.js"> </script>
|
||||
<script src="plugin.js"> </script>
|
||||
|
||||
</head>
|
||||
<body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" >
|
||||
</body>
|
||||
</html>
|
||||
|
|
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|
|||
<html>
|
||||
<head>
|
||||
<script src="xilinxD.js"> </script>
|
||||
<script src="ns4plugin.js"> </script>
|
||||
|
||||
</head>
|
||||
<body onload="javascript:checkJre()" bgcolor="#ffffff" topmargin="0" leftmargin="0" marginheight="0" marginwidth="0" >
|
||||
</body>
|
||||
</html>
|
||||
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|
|||
<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
|
||||
<h3 align='center'>Equations</h3>
|
||||
<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
|
||||
<tr><td>
|
||||
</td></tr><tr><td>
|
||||
********** Mapped Logic **********
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
$OpTx$INV$223 <= ((A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND NOT nWE_FSB AND
|
||||
<br/> NOT fsb/Ready1r AND NOT iobs/IOReady AND NOT nADoutLE1)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||||
<br/> A_FSB(10) AND NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||||
<br/> NOT A_FSB(10) AND NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> NOT A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||||
<br/> A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> NOT A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||||
<br/> NOT A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||||
<br/> OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND
|
||||
<br/> NOT iobs/IOReady)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||||
<br/> NOT fsb/Ready0r AND NOT ram/RAMReady)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||||
<br/> NOT fsb/Ready1r AND NOT iobs/IOReady));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
|
||||
<br/> ALE0M_D <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||||
<br/> NOT iobm/IOREQr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd8));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_ALE0S: FDCPE port map (ALE0S,ALE0S_D,CLK_FSB,'0','0');
|
||||
<br/> ALE0S_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||||
</td></tr><tr><td>
|
||||
FTCPE_BERR_IOBS: FTCPE port map (BERR_IOBS,BERR_IOBS_T,CLK_FSB,'0','0');
|
||||
<br/> BERR_IOBS_T <= ((iobs/Once AND NOT BERR_IOBS AND IOBERR AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND fsb/ASrf AND nADoutLE1)
|
||||
<br/> OR (BERR_IOBS AND nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (iobs/Once AND BERR_IOBS AND NOT IOBERR AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
|
||||
<br/> OR (iobs/Once AND NOT BERR_IOBS AND IOBERR AND NOT nAS_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,CLK2X_IOB,'0','0');
|
||||
<br/> IOACT_D <= ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
|
||||
<br/> iobm/DTACKrf AND iobm/DTACKrr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
|
||||
<br/> iobm/RESrf AND iobm/RESrr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
|
||||
<br/> iobm/BERRrf AND iobm/BERRrr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
|
||||
<br/> iobm/DTACKrf AND iobm/DTACKrr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
|
||||
<br/> iobm/RESrf AND iobm/RESrr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||||
<br/> NOT iobm/IOREQr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd8)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND iobm/ETACK AND
|
||||
<br/> NOT iobm/IOREQr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND iobm/ETACK AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd8)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
|
||||
<br/> iobm/BERRrf AND iobm/BERRrr));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_IOBERR: FTCPE port map (IOBERR,IOBERR_T,CLK2X_IOB,'0','0');
|
||||
<br/> IOBERR_T <= ((NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||||
<br/> CLK_IOB AND iobm/BERRrf AND iobm/BERRrr)
|
||||
<br/> OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||||
<br/> CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
|
||||
<br/> OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||||
<br/> CLK_IOB AND iobm/RESrf AND iobm/RESrr)
|
||||
<br/> OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||||
<br/> CLK_IOB AND iobm/ETACK)
|
||||
<br/> OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||||
<br/> CLK_IOB AND iobm/ETACK)
|
||||
<br/> OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||||
<br/> CLK_IOB AND iobm/BERRrf AND iobm/BERRrr)
|
||||
<br/> OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||||
<br/> CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
|
||||
<br/> OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
|
||||
<br/> CLK_IOB AND iobm/RESrf AND iobm/RESrr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,CLK_FSB,'0','0',IOL0_CE);
|
||||
<br/> IOL0_D <= ((NOT nLDS_FSB AND nADoutLE1)
|
||||
<br/> OR (iobs/IOL1 AND NOT nADoutLE1));
|
||||
<br/> IOL0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,CLK_FSB,'0','0');
|
||||
<br/> IOREQ_D <= ((EXP14_.EXP)
|
||||
<br/> OR (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd1 AND
|
||||
<br/> fsb/ASrf)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_IORW0: FTCPE port map (IORW0,IORW0_T,CLK_FSB,'0','0');
|
||||
<br/> IORW0_T <= ((A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||||
<br/> fsb/ASrf AND nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> NOT IORW0 AND nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> NOT IORW0 AND nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||||
<br/> fsb/ASrf AND nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND IORW0 AND
|
||||
<br/> NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||||
<br/> nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND IORW0 AND
|
||||
<br/> NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND
|
||||
<br/> nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||||
<br/> NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||||
<br/> NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||||
<br/> OR (IORW0 AND NOT iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||||
<br/> OR (NOT IORW0 AND iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
|
||||
<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
|
||||
<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,CLK_FSB,'0','0',IOU0_CE);
|
||||
<br/> IOU0_D <= ((NOT nUDS_FSB AND nADoutLE1)
|
||||
<br/> OR (iobs/IOU1 AND NOT nADoutLE1));
|
||||
<br/> IOU0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(0) <= ((A_FSB(10) AND NOT ram/RASEL)
|
||||
<br/> OR (ram/RASEL AND A_FSB(1)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(1) <= ((A_FSB(11) AND NOT ram/RASEL)
|
||||
<br/> OR (ram/RASEL AND A_FSB(2)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(2) <= ((A_FSB(12) AND NOT ram/RASEL)
|
||||
<br/> OR (ram/RASEL AND A_FSB(3)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(3) <= ((A_FSB(13) AND NOT ram/RASEL)
|
||||
<br/> OR (ram/RASEL AND A_FSB(4)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(4) <= ((A_FSB(14) AND NOT ram/RASEL)
|
||||
<br/> OR (ram/RASEL AND A_FSB(5)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(5) <= ((A_FSB(15) AND NOT ram/RASEL)
|
||||
<br/> OR (ram/RASEL AND A_FSB(6)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(6) <= ((A_FSB(16) AND NOT ram/RASEL)
|
||||
<br/> OR (ram/RASEL AND A_FSB(7)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(7) <= ((A_FSB(17) AND NOT ram/RASEL)
|
||||
<br/> OR (ram/RASEL AND A_FSB(8)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(8) <= ((A_FSB(9) AND ram/RASEL)
|
||||
<br/> OR (A_FSB(18) AND NOT ram/RASEL));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(9) <= ((A_FSB(20) AND ram/RASEL)
|
||||
<br/> OR (A_FSB(19) AND NOT ram/RASEL));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(10) <= A_FSB(21);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
RA(11) <= A_FSB(19);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_RefAck: FDCPE port map (RefAck,RefAck_D,CLK_FSB,'0','0');
|
||||
<br/> RefAck_D <= (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1);
|
||||
</td></tr><tr><td>
|
||||
FTCPE_TimeoutA: FTCPE port map (TimeoutA,TimeoutA_T,CLK_FSB,'0','0');
|
||||
<br/> TimeoutA_T <= ((TimeoutA AND nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (NOT TimeoutA AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
|
||||
<br/> NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||||
<br/> NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
|
||||
<br/> OR (NOT TimeoutA AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
|
||||
<br/> NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
|
||||
<br/> NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_TimeoutB: FTCPE port map (TimeoutB,TimeoutB_T,CLK_FSB,'0','0');
|
||||
<br/> TimeoutB_T <= ((TimeoutB AND nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (TimeoutA AND NOT TimeoutB AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
|
||||
<br/> NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||||
<br/> NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
|
||||
<br/> OR (TimeoutA AND NOT TimeoutB AND NOT cnt/RefCnt(0) AND
|
||||
<br/> NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||||
<br/> NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cnt/RefCnt0: FTCPE port map (cnt/RefCnt(0),'1',CLK_FSB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cnt/RefCnt1: FTCPE port map (cnt/RefCnt(1),cnt/RefCnt(0),CLK_FSB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cnt/RefCnt2: FTCPE port map (cnt/RefCnt(2),cnt/RefCnt_T(2),CLK_FSB,'0','0');
|
||||
<br/> cnt/RefCnt_T(2) <= (cnt/RefCnt(0) AND cnt/RefCnt(1));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cnt/RefCnt3: FTCPE port map (cnt/RefCnt(3),cnt/RefCnt_T(3),CLK_FSB,'0','0');
|
||||
<br/> cnt/RefCnt_T(3) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cnt/RefCnt4: FTCPE port map (cnt/RefCnt(4),cnt/RefCnt_T(4),CLK_FSB,'0','0');
|
||||
<br/> cnt/RefCnt_T(4) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
|
||||
<br/> cnt/RefCnt(3));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cnt/RefCnt5: FTCPE port map (cnt/RefCnt(5),cnt/RefCnt_T(5),CLK_FSB,'0','0');
|
||||
<br/> cnt/RefCnt_T(5) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
|
||||
<br/> cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cnt/RefCnt6: FTCPE port map (cnt/RefCnt(6),cnt/RefCnt_T(6),CLK_FSB,'0','0');
|
||||
<br/> cnt/RefCnt_T(6) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(1) AND
|
||||
<br/> cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cnt/RefCnt7: FTCPE port map (cnt/RefCnt(7),cnt/RefCnt_T(7),CLK_FSB,'0','0');
|
||||
<br/> cnt/RefCnt_T(7) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
|
||||
<br/> cnt/RefCnt(1) AND cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_cnt/RefDone: FDCPE port map (cnt/RefDone,cnt/RefDone_D,CLK_FSB,'0','0');
|
||||
<br/> cnt/RefDone_D <= ((NOT cnt/RefDone AND NOT RefAck)
|
||||
<br/> OR (NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND
|
||||
<br/> NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND
|
||||
<br/> NOT cnt/RefCnt(7)));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_cs/nOverlay0: FTCPE port map (cs/nOverlay0,cs/nOverlay0_T,CLK_FSB,NOT nRES,'0');
|
||||
<br/> cs/nOverlay0_T <= ((NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay0 AND NOT nAS_FSB)
|
||||
<br/> OR (NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay0 AND fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_cs/nOverlay1: FDCPE port map (cs/nOverlay1,cs/nOverlay0,CLK_FSB,'0','0',cs/nOverlay1_CE);
|
||||
<br/> cs/nOverlay1_CE <= (nAS_FSB AND NOT fsb/ASrf);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT CLK_FSB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_fsb/BERR0r: FDCPE port map (fsb/BERR0r,fsb/BERR0r_D,CLK_FSB,'0','0');
|
||||
<br/> fsb/BERR0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (NOT TimeoutB AND NOT fsb/BERR0r)
|
||||
<br/> OR (A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||||
<br/> NOT fsb/BERR0r));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_fsb/BERR1r: FDCPE port map (fsb/BERR1r,fsb/BERR1r_D,CLK_FSB,'0','0');
|
||||
<br/> fsb/BERR1r_D <= ((NOT BERR_IOBS AND NOT fsb/BERR1r)
|
||||
<br/> OR (nAS_FSB AND NOT fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_fsb/Ready0r: FDCPE port map (fsb/Ready0r,fsb/Ready0r_D,CLK_FSB,'0','0');
|
||||
<br/> fsb/Ready0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||||
<br/> NOT fsb/Ready0r AND NOT ram/RAMReady)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_fsb/Ready1r: FDCPE port map (fsb/Ready1r,fsb/Ready1r_D,CLK_FSB,'0','0');
|
||||
<br/> fsb/Ready1r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND
|
||||
<br/> NOT iobs/IOReady)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||||
<br/> NOT fsb/Ready1r AND NOT iobs/IOReady)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND NOT nWE_FSB AND
|
||||
<br/> NOT fsb/Ready1r AND NOT iobs/IOReady AND NOT nADoutLE1));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_fsb/Ready2r: FDCPE port map (fsb/Ready2r,fsb/Ready2r_D,CLK_FSB,'0','0');
|
||||
<br/> fsb/Ready2r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||||
<br/> A_FSB(10) AND NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||||
<br/> NOT A_FSB(10) AND NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> NOT A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||||
<br/> A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> NOT A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||||
<br/> NOT A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_fsb/VPA: FTCPE port map (fsb/VPA,fsb/VPA_T,CLK_FSB,'0','0');
|
||||
<br/> fsb/VPA_T <= ((A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||||
<br/> NOT fsb/BERR0r AND fsb/VPA AND NOT $OpTx$INV$223)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT BERR_IOBS AND NOT fsb/BERR1r AND NOT fsb/VPA AND NOT nAS_FSB AND NOT $OpTx$INV$223)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT BERR_IOBS AND NOT fsb/BERR1r AND NOT fsb/VPA AND fsb/ASrf AND NOT $OpTx$INV$223)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT TimeoutB AND NOT fsb/BERR0r AND NOT fsb/VPA AND NOT nAS_FSB AND NOT $OpTx$INV$223)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT TimeoutB AND NOT fsb/BERR0r AND NOT fsb/VPA AND fsb/ASrf AND NOT $OpTx$INV$223)
|
||||
<br/> OR (NOT A_FSB(20) AND NOT TimeoutB AND NOT fsb/BERR0r AND fsb/VPA AND
|
||||
<br/> NOT $OpTx$INV$223)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT TimeoutB AND NOT fsb/BERR0r AND fsb/VPA AND
|
||||
<br/> NOT $OpTx$INV$223)
|
||||
<br/> OR (NOT A_FSB(22) AND NOT TimeoutB AND NOT fsb/BERR0r AND fsb/VPA AND
|
||||
<br/> NOT $OpTx$INV$223)
|
||||
<br/> OR (NOT A_FSB(21) AND NOT TimeoutB AND NOT fsb/BERR0r AND fsb/VPA AND
|
||||
<br/> NOT $OpTx$INV$223)
|
||||
<br/> OR (fsb/VPA AND nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(20) AND NOT BERR_IOBS AND NOT fsb/BERR1r AND fsb/VPA AND
|
||||
<br/> NOT $OpTx$INV$223)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT BERR_IOBS AND NOT fsb/BERR1r AND fsb/VPA AND
|
||||
<br/> NOT $OpTx$INV$223)
|
||||
<br/> OR (NOT A_FSB(22) AND NOT BERR_IOBS AND NOT fsb/BERR1r AND fsb/VPA AND
|
||||
<br/> NOT $OpTx$INV$223)
|
||||
<br/> OR (NOT A_FSB(21) AND NOT BERR_IOBS AND NOT fsb/BERR1r AND fsb/VPA AND
|
||||
<br/> NOT $OpTx$INV$223));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/BERRrr: FDCPE port map (iobm/BERRrr,NOT nBERR_IOB,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/DTACKrf: FDCPE port map (iobm/DTACKrf,NOT nDTACK_IOB,NOT CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/DTACKrr: FDCPE port map (iobm/DTACKrr,NOT nDTACK_IOB,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),CLK2X_IOB,'0','0');
|
||||
<br/> iobm/ES_T(0) <= ((iobm/ES(0) AND NOT iobm/Er AND iobm/Er2)
|
||||
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||||
<br/> NOT iobm/ES(3) AND NOT iobm/ES(4) AND iobm/Er)
|
||||
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||||
<br/> NOT iobm/ES(3) AND NOT iobm/ES(4) AND NOT iobm/Er2));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),CLK2X_IOB,'0','0');
|
||||
<br/> iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
|
||||
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
|
||||
<br/> OR (NOT iobm/Er AND iobm/Er2));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/ES2: FDCPE port map (iobm/ES(2),iobm/ES_D(2),CLK2X_IOB,'0','0');
|
||||
<br/> iobm/ES_D(2) <= ((NOT iobm/ES(0) AND NOT iobm/ES(2))
|
||||
<br/> OR (NOT iobm/ES(1) AND NOT iobm/ES(2))
|
||||
<br/> OR (NOT iobm/Er AND iobm/Er2)
|
||||
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2))
|
||||
<br/> OR (NOT iobm/ES(2) AND NOT iobm/ES(3) AND iobm/ES(4)));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),CLK2X_IOB,'0','0');
|
||||
<br/> iobm/ES_T(3) <= ((iobm/ES(3) AND NOT iobm/Er AND iobm/Er2)
|
||||
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND iobm/Er)
|
||||
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er2));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_iobm/ES4: FTCPE port map (iobm/ES(4),iobm/ES_T(4),CLK2X_IOB,'0','0');
|
||||
<br/> iobm/ES_T(4) <= ((iobm/ES(4) AND NOT iobm/Er AND iobm/Er2)
|
||||
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
||||
<br/> iobm/ES(3) AND iobm/Er)
|
||||
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
||||
<br/> iobm/ES(3) AND NOT iobm/Er2)
|
||||
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
|
||||
<br/> NOT iobm/ES(3) AND iobm/ES(4)));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/ETACK: FDCPE port map (iobm/ETACK,iobm/ETACK_D,CLK2X_IOB,'0','0');
|
||||
<br/> iobm/ETACK_D <= (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||||
<br/> NOT iobm/ES(3) AND iobm/ES(4));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E_IOB,NOT CLK_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/Er2: FDCPE port map (iobm/Er2,iobm/Er,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,NOT CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,CLK2X_IOB,'0','0');
|
||||
<br/> iobm/IOS_FSM_FFd2_D <= ((iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/ETACK)
|
||||
<br/> OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/BERRrf AND
|
||||
<br/> iobm/BERRrr)
|
||||
<br/> OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/DTACKrf AND
|
||||
<br/> iobm/DTACKrr)
|
||||
<br/> OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/RESrf AND
|
||||
<br/> iobm/RESrr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,CLK2X_IOB,'0','0');
|
||||
<br/> iobm/IOS_FSM_FFd3_D <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/ETACK)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/BERRrf AND
|
||||
<br/> iobm/BERRrr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/DTACKrf AND
|
||||
<br/> iobm/DTACKrr)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/RESrf AND
|
||||
<br/> iobm/RESrr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd7,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,CLK2X_IOB,'0','0');
|
||||
<br/> iobm/IOS_FSM_FFd7_D <= (NOT CLK_IOB AND iobm/IOREQr AND iobm/IOS_FSM_FFd8);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/IOS_FSM_FFd8: FDCPE port map (iobm/IOS_FSM_FFd8,iobm/IOS_FSM_FFd8_D,CLK2X_IOB,'0','0');
|
||||
<br/> iobm/IOS_FSM_FFd8_D <= ((NOT iobm/IOS_FSM_FFd8 AND NOT iobm/IOS_FSM_FFd1)
|
||||
<br/> OR (NOT CLK_IOB AND iobm/IOREQr AND NOT iobm/IOS_FSM_FFd1));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/RESrf: FDCPE port map (iobm/RESrf,NOT nRES,NOT CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/RESrr: FDCPE port map (iobm/RESrr,NOT nRES,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/VPArf: FDCPE port map (iobm/VPArf,NOT nVPA_IOB,NOT CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobm/VPArr: FDCPE port map (iobm/VPArr,NOT nVPA_IOB,CLK2X_IOB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,CLK_FSB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,CLK_FSB,'0','0',iobs/Load1);
|
||||
</td></tr><tr><td>
|
||||
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,CLK_FSB,'0','0');
|
||||
<br/> iobs/IORW1_T <= ((iobs/Once)
|
||||
<br/> OR (NOT nADoutLE1)
|
||||
<br/> OR (nWE_FSB AND iobs/IORW1)
|
||||
<br/> OR (NOT nWE_FSB AND NOT iobs/IORW1)
|
||||
<br/> OR (nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
|
||||
<br/> OR (NOT A_FSB(19) AND NOT A_FSB(23) AND A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(18) AND NOT A_FSB(23) AND A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(17) AND NOT A_FSB(23) AND A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(16) AND NOT A_FSB(23) AND A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> cs/nOverlay1)
|
||||
<br/> OR (NOT A_FSB(20) AND NOT A_FSB(23))
|
||||
<br/> OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/IORW1));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_iobs/IOReady: FTCPE port map (iobs/IOReady,iobs/IOReady_T,CLK_FSB,'0','0');
|
||||
<br/> iobs/IOReady_T <= ((iobs/IOReady AND nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (iobs/Once AND IOBERR AND iobs/IOReady AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
|
||||
<br/> OR (iobs/Once AND NOT IOBERR AND NOT iobs/IOReady AND NOT nAS_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
|
||||
<br/> OR (iobs/Once AND NOT IOBERR AND NOT iobs/IOReady AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND fsb/ASrf AND nADoutLE1));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,CLK_FSB,'0','0',iobs/Load1);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,CLK_FSB,'0','0');
|
||||
<br/> iobs/Load1_D <= ((iobs/Once)
|
||||
<br/> OR (NOT nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(18) AND NOT A_FSB(23) AND A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(17) AND NOT A_FSB(23) AND A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> cs/nOverlay1)
|
||||
<br/> OR (NOT A_FSB(19) AND NOT A_FSB(23) AND A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(16) AND NOT A_FSB(23) AND A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB)
|
||||
<br/> OR (NOT A_FSB(20) AND NOT A_FSB(23))
|
||||
<br/> OR (nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_iobs/Once: FTCPE port map (iobs/Once,iobs/Once_T,CLK_FSB,'0','0');
|
||||
<br/> iobs/Once_T <= ((A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND
|
||||
<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||||
<br/> NOT iobs/Once AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||||
<br/> NOT iobs/Once AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||||
<br/> fsb/ASrf)
|
||||
<br/> OR (iobs/Once AND nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_iobs/PS_FSM_FFd1: FDCPE port map (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,CLK_FSB,'0','0');
|
||||
<br/> iobs/PS_FSM_FFd1_D <= ((iobs/PS_FSM_FFd2)
|
||||
<br/> OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_iobs/PS_FSM_FFd2: FTCPE port map (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_T,CLK_FSB,'0','0');
|
||||
<br/> iobs/PS_FSM_FFd2_T <= ((iobs/PS_FSM_FFd1 AND iobs/IOACTr)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND
|
||||
<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT iobs/Once AND NOT nWE_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||||
<br/> OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
|
||||
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||||
<br/> NOT iobs/Once AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||||
<br/> NOT iobs/PS_FSM_FFd1)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND
|
||||
<br/> NOT iobs/Once AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||||
<br/> fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
|
||||
</td></tr><tr><td>
|
||||
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,CLK_FSB,'0','0');
|
||||
<br/> nADoutLE1_D <= ((NOT A_FSB(19) AND NOT A_FSB(23) AND A_FSB(21) AND nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(16) AND NOT A_FSB(23) AND A_FSB(21) AND nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
|
||||
<br/> nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(18) AND NOT A_FSB(23) AND A_FSB(21) AND nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(17) AND NOT A_FSB(23) AND A_FSB(21) AND nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> cs/nOverlay1 AND nADoutLE1)
|
||||
<br/> OR (iobs/Once AND nADoutLE1)
|
||||
<br/> OR (NOT A_FSB(20) AND NOT A_FSB(23) AND nADoutLE1)
|
||||
<br/> OR (nAS_FSB AND NOT fsb/ASrf AND nADoutLE1)
|
||||
<br/> OR (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||||
<br/> OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB,nAS_IOB_D,NOT CLK2X_IOB,'0','0');
|
||||
<br/> nAS_IOB_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nAoutOE <= '0';
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nBERR_FSB <= ((nAS_FSB)
|
||||
<br/> OR (NOT BERR_IOBS AND NOT fsb/BERR1r)
|
||||
<br/> OR (NOT TimeoutB AND NOT fsb/BERR0r)
|
||||
<br/> OR (A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND
|
||||
<br/> NOT fsb/BERR0r));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/RASEL,NOT CLK_FSB,'0','0');
|
||||
</td></tr><tr><td>
|
||||
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,CLK_FSB,'0','0');
|
||||
<br/> nDTACK_FSB_D <= ((A_FSB(23) AND BERR_IOBS AND TimeoutB AND nDTACK_FSB)
|
||||
<br/> OR (A_FSB(23) AND TimeoutB AND fsb/BERR1r AND nDTACK_FSB)
|
||||
<br/> OR (NOT A_FSB(22) AND TimeoutB AND fsb/BERR1r AND nDTACK_FSB)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND A_FSB(22) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||||
<br/> NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB)
|
||||
<br/> OR (EXP17_.EXP)
|
||||
<br/> OR (NOT A_FSB(20) AND TimeoutB AND fsb/BERR1r AND nDTACK_FSB)
|
||||
<br/> OR (NOT A_FSB(22) AND BERR_IOBS AND TimeoutB AND nDTACK_FSB)
|
||||
<br/> OR (A_FSB(21) AND TimeoutB AND fsb/BERR1r AND nDTACK_FSB)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND NOT fsb/Ready1r AND
|
||||
<br/> NOT iobs/IOReady AND nDTACK_FSB)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||||
<br/> NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||||
<br/> A_FSB(16) AND NOT A_FSB(22) AND A_FSB(21) AND cs/nOverlay1 AND NOT nWE_FSB AND
|
||||
<br/> NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB AND NOT nADoutLE1)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND A_FSB(22) AND
|
||||
<br/> A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r AND nDTACK_FSB)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND A_FSB(22) AND
|
||||
<br/> A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r AND nDTACK_FSB)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> NOT A_FSB(22) AND A_FSB(21) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND
|
||||
<br/> A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r AND
|
||||
<br/> nDTACK_FSB)
|
||||
<br/> OR (A_FSB(9) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||||
<br/> NOT A_FSB(22) AND A_FSB(21) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND
|
||||
<br/> NOT A_FSB(10) AND cs/nOverlay1 AND NOT TimeoutA AND NOT nWE_FSB AND NOT fsb/Ready2r AND
|
||||
<br/> nDTACK_FSB));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT CLK2X_IOB,'0','0');
|
||||
<br/> nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nDinOE <= ((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
|
||||
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT A_FSB(21) AND nWE_FSB AND
|
||||
<br/> NOT nAS_FSB));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_nDoutOE: FDCPE port map (nDoutOE,nDoutOE_D,CLK2X_IOB,'0','0');
|
||||
<br/> nDoutOE_D <= ((NOT IORW0)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd2));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB,nLDS_IOB_D,NOT CLK2X_IOB,'0','0');
|
||||
<br/> nLDS_IOB_D <= ((NOT IOL0)
|
||||
<br/> OR (IORW0 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nOE <= NOT ((nWE_FSB AND NOT nAS_FSB));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nRAMLWE <= NOT ((NOT nWE_FSB AND NOT nLDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
|
||||
<br/> NOT ram/RAMDIS1));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
|
||||
<br/> NOT ram/RAMDIS1));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nRAS <= NOT (((RefAck)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||||
<br/> NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nROMCS <= NOT (((NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21))
|
||||
<br/> OR (NOT A_FSB(20) AND NOT A_FSB(23) AND NOT A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1)));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nROMWE <= NOT ((NOT nWE_FSB AND NOT nAS_FSB));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB,nUDS_IOB_D,NOT CLK2X_IOB,'0','0');
|
||||
<br/> nUDS_IOB_D <= ((NOT IOU0)
|
||||
<br/> OR (IORW0 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5)
|
||||
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||||
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB,nVMA_IOB_T,CLK2X_IOB,'0','0');
|
||||
<br/> nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||||
<br/> NOT iobm/ES(3) AND NOT iobm/ES(4))
|
||||
<br/> OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
||||
<br/> NOT iobm/ES(3) AND NOT iobm/ES(4) AND IOACT AND iobm/VPArf AND iobm/VPArr));
|
||||
</td></tr><tr><td>
|
||||
</td></tr><tr><td>
|
||||
nVPA_FSB <= NOT ((fsb/VPA AND NOT nAS_FSB));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,CLK_FSB,'0','0');
|
||||
<br/> ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
|
||||
</td></tr><tr><td>
|
||||
FTCPE_ram/Once: FTCPE port map (ram/Once,ram/Once_T,CLK_FSB,'0','0');
|
||||
<br/> ram/Once_T <= ((NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
|
||||
<br/> OR (ram/Once AND nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_ram/RAMDIS1: FDCPE port map (ram/RAMDIS1,ram/RAMDIS1_D,CLK_FSB,'0','0');
|
||||
<br/> ram/RAMDIS1_D <= ((A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (nDinOE_OBUF.EXP)
|
||||
<br/> OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||||
<br/> OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||||
<br/> OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND
|
||||
<br/> cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||||
<br/> OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND NOT fsb/ASrf)
|
||||
<br/> OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
|
||||
<br/> OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
|
||||
<br/> OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/BACTr AND fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_ram/RAMDIS2: FTCPE port map (ram/RAMDIS2,ram/RAMDIS2_T,CLK_FSB,'0','0');
|
||||
<br/> ram/RAMDIS2_T <= ((NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||||
<br/> cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||||
<br/> cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
|
||||
<br/> OR (ram/RAMDIS2 AND nAS_FSB AND NOT fsb/ASrf)
|
||||
<br/> OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
|
||||
<br/> ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
|
||||
<br/> cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
|
||||
<br/> OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
|
||||
<br/> ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
|
||||
<br/> cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND ram/Once AND
|
||||
<br/> NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
|
||||
<br/> cnt/RefCnt(7))
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND ram/Once AND
|
||||
<br/> NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
|
||||
<br/> fsb/ASrf));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_ram/RAMReady: FDCPE port map (ram/RAMReady,ram/RAMReady_D,CLK_FSB,'0','0');
|
||||
<br/> ram/RAMReady_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd1)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
|
||||
<br/> OR (EXP36_.EXP)
|
||||
<br/> OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1)
|
||||
<br/> OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
|
||||
<br/> OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (NOT A_FSB(21) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (NOT A_FSB(21) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd1));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,CLK_FSB,'0','0');
|
||||
<br/> ram/RASEL_D <= ((ram/RS_FSM_FFd2.EXP)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (RA_5_OBUF.EXP)
|
||||
<br/> OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
|
||||
<br/> NOT fsb/ASrf)
|
||||
<br/> OR (NOT cnt/RefDone AND nAS_FSB AND ram/RS_FSM_FFd1 AND
|
||||
<br/> ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
|
||||
<br/> NOT fsb/ASrf)
|
||||
<br/> OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
|
||||
<br/> OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
|
||||
<br/> OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
|
||||
<br/> OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7)));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_ram/RS_FSM_FFd1: FTCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_T,CLK_FSB,'0','0');
|
||||
<br/> ram/RS_FSM_FFd1_T <= ((ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||||
<br/> NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
|
||||
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
|
||||
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||||
<br/> NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_ram/RS_FSM_FFd2: FTCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_T,CLK_FSB,'0','0');
|
||||
<br/> ram/RS_FSM_FFd2_T <= ((RA_1_OBUF.EXP)
|
||||
<br/> OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||||
<br/> NOT cnt/RefCnt(5) AND ram/BACTr)
|
||||
<br/> OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/BACTr AND
|
||||
<br/> NOT cnt/RefCnt(7))
|
||||
<br/> OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||||
<br/> NOT cnt/RefCnt(5) AND NOT fsb/ASrf)
|
||||
<br/> OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||||
<br/> NOT cnt/RefCnt(6) AND NOT fsb/ASrf)
|
||||
<br/> OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||||
<br/> NOT cnt/RefCnt(7) AND NOT fsb/ASrf)
|
||||
<br/> OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
||||
<br/> NOT cnt/RefCnt(6) AND ram/BACTr));
|
||||
</td></tr><tr><td>
|
||||
FTCPE_ram/RS_FSM_FFd3: FTCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,CLK_FSB,'0','0');
|
||||
<br/> ram/RS_FSM_FFd3_T <= ((A_FSB(22) AND NOT A_FSB(21) AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (A_FSB(22) AND cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3 AND NOT fsb/ASrf)
|
||||
<br/> OR (NOT cnt/RefDone AND NOT nAS_FSB AND ram/RS_FSM_FFd2 AND
|
||||
<br/> ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
|
||||
<br/> cnt/RefCnt(7))
|
||||
<br/> OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
||||
<br/> ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
|
||||
<br/> fsb/ASrf)
|
||||
<br/> OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (ram/Once AND cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
|
||||
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
||||
<br/> OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(5))
|
||||
<br/> OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(6))
|
||||
<br/> OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
||||
<br/> NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(7)));
|
||||
</td></tr><tr><td>
|
||||
Register Legend:
|
||||
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
|
||||
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
|
||||
<br/> LDCP (Q,D,G,CLR,PRE);
|
||||
</td></tr><tr><td>
|
||||
</td></tr>
|
||||
</table>
|
||||
<form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
|
||||
</tr></table></span></form>
|
||||
</body></html>
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 816 B |
Binary file not shown.
|
After Width: | Height: | Size: 1.5 KiB |
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,929 @@
|
|||
var eqnType = 0;
|
||||
var spcStr = " ";
|
||||
var nlStr = "<br>";
|
||||
var tabStr = spcStr + spcStr + spcStr + spcStr + spcStr;
|
||||
var nlTabStr = nlStr + tabStr;
|
||||
var rClrS = "<font color='blue'>";
|
||||
var rClrE = "</font>";
|
||||
var cClrS = "<font color='green'>";
|
||||
var cClrE = "</font>";
|
||||
|
||||
var abelOper = new Array();
|
||||
abelOper["GND"] = new Array("Gnd");
|
||||
abelOper["VCC"] = new Array("Vcc");
|
||||
abelOper["NOT"] = new Array(rClrS + "!" + rClrE);
|
||||
abelOper["AND"] = new Array(rClrS + "&" + rClrE);
|
||||
abelOper["OR"] = new Array(rClrS + "#" + rClrE);
|
||||
abelOper["XOR"] = new Array(rClrS + "$" + rClrE);
|
||||
abelOper["EQUAL_COLON"] = new Array(":= ");
|
||||
abelOper["EQUAL"] = new Array("= ");
|
||||
abelOper["ASSIGN"] = new Array("");
|
||||
abelOper["OPEN_NEGATE"] = new Array("(");
|
||||
abelOper["CLOSE_NEGATE"] = new Array(")");
|
||||
abelOper["OPEN_PTERM"] = new Array("");
|
||||
abelOper["CLOSE_PTERM"] = new Array("");
|
||||
abelOper["OPEN_BRACE"] = new Array("<");
|
||||
abelOper["CLOSE_BRACE"] = new Array(">");
|
||||
abelOper["INVALID_OPEN_BRACE"] = new Array("<");
|
||||
abelOper["INVALID_CLOSE_BRACE"] = new Array(">");
|
||||
|
||||
abelOper["ENDLN"] = new Array(";");
|
||||
abelOper["COMMENT"] = new Array("//");
|
||||
abelOper["IMPORT"] = new Array(";Imported pterms ");
|
||||
abelOper["GCK_COM"] = new Array("GCK");
|
||||
abelOper["GTS_COM"] = new Array("GTS");
|
||||
abelOper["GSR_COM"] = new Array("GSR");
|
||||
abelOper["OD_COM"] = new Array("Open Drain");
|
||||
abelOper["START_EQN"] = new Array("");
|
||||
abelOper["END_EQN"] = new Array("");
|
||||
|
||||
abelOper["_I"] = new Array(".I");
|
||||
abelOper["_T"] = new Array(".T");
|
||||
abelOper["_D"] = new Array(".D");
|
||||
abelOper["_C"] = new Array(".CLK");
|
||||
abelOper["_DEC"] = new Array(".DEC");
|
||||
abelOper["_LH"] = new Array(".LH");
|
||||
abelOper["_CLR"] = new Array(".AR");
|
||||
abelOper["_PRE"] = new Array(".AP");
|
||||
abelOper["_CE"] = new Array(".CE");
|
||||
abelOper["_OE"] = new Array(".OE");
|
||||
|
||||
abelOper["OE_START"] = new Array(" <= ");
|
||||
abelOper["OE_WHEN"] = new Array(" when ");
|
||||
abelOper["OE_EQUAL"] = new Array(" = ");
|
||||
abelOper["OE_ELSE"] = new Array(" else ");
|
||||
abelOper["B0"] = new Array("'0'");
|
||||
abelOper["B1"] = new Array("'1'");
|
||||
abelOper["BZ"] = new Array("'Z'");
|
||||
|
||||
abelOper["FD"] = new Array(".D");
|
||||
abelOper["FT"] = new Array(".T");
|
||||
abelOper["FDD"] = new Array(".DEC");
|
||||
abelOper["FTD"] = new Array(".T");
|
||||
abelOper["LD"] = new Array(".LH");
|
||||
abelOper["Q"] = new Array(".Q");
|
||||
|
||||
var vhdlOper = new Array();
|
||||
vhdlOper["GND"] = new Array("'0'");
|
||||
vhdlOper["VCC"] = new Array("'1'");
|
||||
vhdlOper["NOT"] = new Array(rClrS + "NOT " + rClrE);
|
||||
vhdlOper["AND"] = new Array(rClrS + "AND" + rClrE);
|
||||
vhdlOper["OR"] = new Array(rClrS + "OR" + rClrE);
|
||||
vhdlOper["XOR"] = new Array(rClrS + "XOR" + rClrE);
|
||||
vhdlOper["EQUAL_COLON"] = new Array("<= ");
|
||||
vhdlOper["EQUAL"] = new Array("<= ");
|
||||
vhdlOper["ASSIGN"] = new Array("");
|
||||
vhdlOper["OPEN_NEGATE"] = new Array("(");
|
||||
vhdlOper["CLOSE_NEGATE"] = new Array(")");
|
||||
vhdlOper["OPEN_PTERM"] = new Array("(");
|
||||
vhdlOper["CLOSE_PTERM"] = new Array(")");
|
||||
vhdlOper["OPEN_BRACE"] = new Array("(");
|
||||
vhdlOper["CLOSE_BRACE"] = new Array(")");
|
||||
vhdlOper["INVALID_OPEN_BRACE"] = new Array("<");
|
||||
vhdlOper["INVALID_CLOSE_BRACE"] = new Array(">");
|
||||
|
||||
vhdlOper["ENDLN"] = new Array(";");
|
||||
vhdlOper["COMMENT"] = new Array("--");
|
||||
vhdlOper["IMPORT"] = new Array("");
|
||||
vhdlOper["GCK_COM"] = new Array("GCK");
|
||||
vhdlOper["GTS_COM"] = new Array("GTS");
|
||||
vhdlOper["GSR_COM"] = new Array("GSR");
|
||||
vhdlOper["OD_COM"] = new Array("Open Drain");
|
||||
vhdlOper["START_EQN"] = new Array(rClrS + "port map" + rClrE + " (");
|
||||
vhdlOper["END_EQN"] = new Array(")");
|
||||
|
||||
vhdlOper["_I"] = new Array("_I");
|
||||
vhdlOper["_T"] = new Array("_T");
|
||||
vhdlOper["_D"] = new Array("_D");
|
||||
vhdlOper["_C"] = new Array("_C");
|
||||
vhdlOper["_DEC"] = new Array("_C");
|
||||
vhdlOper["_LH"] = new Array("_C");
|
||||
vhdlOper["_CLR"] = new Array("_CLR");
|
||||
vhdlOper["_PRE"] = new Array("_PRE");
|
||||
vhdlOper["_CE"] = new Array("_CE");
|
||||
vhdlOper["_OE"] = new Array("_OE");
|
||||
|
||||
vhdlOper["OE_START"] = new Array(" <= ");
|
||||
vhdlOper["OE_WHEN"] = new Array(" when ");
|
||||
vhdlOper["OE_EQUAL"] = new Array(" = ");
|
||||
vhdlOper["OE_ELSE"] = new Array(" else ");
|
||||
vhdlOper["B0"] = new Array("'0'");
|
||||
vhdlOper["B1"] = new Array("'1'");
|
||||
vhdlOper["BZ"] = new Array("'Z'");
|
||||
|
||||
vhdlOper["FD"] = new Array("FDCPE");
|
||||
vhdlOper["FT"] = new Array("FTCPE");
|
||||
vhdlOper["FDD"] = new Array("FDDCPE");
|
||||
vhdlOper["FTD"] = new Array("FTDCPE");
|
||||
vhdlOper["LD"] = new Array("LDCP");
|
||||
vhdlOper["Q"] = new Array("");
|
||||
|
||||
var verOper = new Array();
|
||||
verOper["GND"] = new Array("1'b0");
|
||||
verOper["VCC"] = new Array("1'b1");
|
||||
verOper["NOT"] = new Array(rClrS + "!" + rClrE);
|
||||
verOper["AND"] = new Array(rClrS + "&&" + rClrE);
|
||||
verOper["OR"] = new Array(rClrS + "||" + rClrE);
|
||||
verOper["XOR"] = new Array(rClrS + "XOR" + rClrE);
|
||||
verOper["EQUAL_COLON"] = new Array("= ");
|
||||
verOper["EQUAL"] = new Array("= ");
|
||||
verOper["ASSIGN"] = new Array("assign ");
|
||||
verOper["OPEN_NEGATE"] = new Array("(");
|
||||
verOper["CLOSE_NEGATE"] = new Array(")");
|
||||
verOper["OPEN_PTERM"] = new Array("(");
|
||||
verOper["CLOSE_PTERM"] = new Array(")");
|
||||
verOper["OPEN_BRACE"] = new Array("[");
|
||||
verOper["CLOSE_BRACE"] = new Array("]");
|
||||
verOper["INVALID_OPEN_BRACE"] = new Array("<");
|
||||
verOper["INVALID_CLOSE_BRACE"] = new Array(">");
|
||||
|
||||
verOper["ENDLN"] = new Array(";");
|
||||
verOper["COMMENT"] = new Array("//");
|
||||
verOper["IMPORT"] = new Array("");
|
||||
verOper["GCK_COM"] = new Array("GCK");
|
||||
verOper["GTS_COM"] = new Array("GTS");
|
||||
verOper["GSR_COM"] = new Array("GSR");
|
||||
verOper["OD_COM"] = new Array("Open Drain");
|
||||
verOper["START_EQN"] = new Array(" (");
|
||||
verOper["END_EQN"] = new Array(")");
|
||||
|
||||
verOper["_I"] = new Array("_I");
|
||||
verOper["_T"] = new Array("_T");
|
||||
verOper["_D"] = new Array("_D");
|
||||
verOper["_C"] = new Array("_C");
|
||||
verOper["_DEC"] = new Array("_C");
|
||||
verOper["_LH"] = new Array("_C");
|
||||
verOper["_CLR"] = new Array("_CLR");
|
||||
verOper["_PRE"] = new Array("_PRE");
|
||||
verOper["_CE"] = new Array("_CE");
|
||||
verOper["_OE"] = new Array("_OE");
|
||||
|
||||
verOper["OE_START"] = new Array(" = ");
|
||||
verOper["OE_WHEN"] = new Array(" ? ");
|
||||
verOper["OE_EQUAL"] = new Array("");
|
||||
verOper["OE_ELSE"] = new Array(" : ");
|
||||
verOper["B0"] = new Array("1'b0");
|
||||
verOper["B1"] = new Array("1'b1");
|
||||
verOper["BZ"] = new Array("1'bz");
|
||||
|
||||
verOper["FD"] = new Array("FDCPE");
|
||||
verOper["FT"] = new Array("FTCPE");
|
||||
verOper["FDD"] = new Array("FDDCPE");
|
||||
verOper["FTD"] = new Array("FTDCPE");
|
||||
verOper["LD"] = new Array("LDCP");
|
||||
verOper["Q"] = new Array("");
|
||||
|
||||
var operator = abelOper;
|
||||
|
||||
var pterms = new Array();
|
||||
var d1 = new Array();
|
||||
var d2 = new Array();
|
||||
var clk = new Array();
|
||||
var set = new Array();
|
||||
var rst = new Array();
|
||||
var trst = new Array();
|
||||
var d1imp = new Array();
|
||||
var d2imp = new Array();
|
||||
var clkimp = new Array();
|
||||
var setimp = new Array();
|
||||
var rstimp = new Array();
|
||||
var trstimp = new Array();
|
||||
var gblclk = new Array();
|
||||
var gblset = new Array();
|
||||
var gblrst = new Array();
|
||||
var gbltrst = new Array();
|
||||
var ce = new Array();
|
||||
var ceimp = new Array();
|
||||
var prld = new Array();
|
||||
var specSig = new Array();
|
||||
var clkNegs = new Array();
|
||||
var setNegs = new Array();
|
||||
var rstNegs = new Array();
|
||||
var trstNegs = new Array();
|
||||
var ceNegs = new Array();
|
||||
var fbnand = new Array();
|
||||
var inreg = new Array();
|
||||
var iostyle = new Array();
|
||||
|
||||
var dOneLit = true;
|
||||
|
||||
function setOper(type) {
|
||||
if (type == "1") { operator = vhdlOper; eqnType = 1; }
|
||||
else if (type == "2") { operator = verOper; eqnType = 2; }
|
||||
else { operator = abelOper; eqnType = 0; }
|
||||
}
|
||||
|
||||
function isXC95() {
|
||||
if (device.indexOf("95") != -1) return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
function is9500() {
|
||||
if ((device.indexOf("95") != -1) &&
|
||||
(device.indexOf("XL") == -1) &&
|
||||
(device.indexOf("XV") == -1)) return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
function retSigType(s) {
|
||||
var sigType = sigTypes[s];
|
||||
var str = operator["Q"];
|
||||
if (sigType == "D") str = operator["FD"];
|
||||
else if (sigType == "T") str = operator["FT"];
|
||||
else if (sigType.indexOf("LATCH") != -1) str = operator["LD"];
|
||||
else if (sigType.indexOf("DDEFF") != -1) str = operator["FDD"];
|
||||
else if (sigType.indexOf("DEFF") != -1) str = operator["FD"];
|
||||
else if (sigType.indexOf("DDFF") != -1) str = operator["FDD"];
|
||||
else if (sigType.indexOf("TDFF") != -1) str = operator["FTD"];
|
||||
else if (sigType.indexOf("DFF") != -1) str = operator["FD"];
|
||||
else if (sigType.indexOf("TFF") != -1) str = operator["FT"];
|
||||
return str;
|
||||
}
|
||||
|
||||
function retSigIndex(signal) {
|
||||
for (s=0; s<signals.length; s++) { if (signals[s] == signal) return s; }
|
||||
return -1;
|
||||
}
|
||||
|
||||
function retSigName(signal) {
|
||||
var str = "";
|
||||
if (specSig[signal]) str += specSig[signal];
|
||||
else str += signal;
|
||||
|
||||
var idx1 = str.indexOf(operator["INVALID_OPEN_BRACE"]);
|
||||
var idx2 = str.indexOf(operator["INVALID_CLOSE_BRACE"]);
|
||||
if ((idx1 != -1) && (idx2 != -1))
|
||||
str = str.substring(0,idx1) + operator["OPEN_BRACE"] +
|
||||
str.substring(idx1+1,idx2) + operator["CLOSE_BRACE"] +
|
||||
str.substring(idx2+1,str.length);
|
||||
return str;
|
||||
}
|
||||
|
||||
function removePar(signal) {
|
||||
var str = signal;
|
||||
|
||||
var idx = str.indexOf(operator["OPEN_BRACE"]);
|
||||
if (idx != -1)
|
||||
str = str.substring(0,idx) +
|
||||
str.substring(idx+1,str.indexOf(operator["CLOSE_BRACE"]));
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
|
||||
function isOneLiteral(str) {
|
||||
if ((str.indexOf(operator["AND"]) != -1) ||
|
||||
(str.indexOf(operator["OR"]) != -1) ||
|
||||
(str.indexOf(operator["XOR"]) != -1)) return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
function updateName(signal, index) {
|
||||
var str;
|
||||
|
||||
var idx = signal.indexOf(operator["OPEN_BRACE"]);
|
||||
if (idx != -1)
|
||||
str = signal.substring(0,idx) +
|
||||
index + signal.substring(idx);
|
||||
else str = signal + index;
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retPterm(pt) {
|
||||
var str = "";
|
||||
if (!pterms[pt]) {
|
||||
if (specSig[pt]) pt = specSig[pt];
|
||||
return pt;
|
||||
}
|
||||
|
||||
if (pterms[pt].length > 1) str += operator["OPEN_PTERM"];
|
||||
for (p=0; p<pterms[pt].length; p++) {
|
||||
var sig = pterms[pt][p];
|
||||
if (sig.indexOf("xPUP_0") != -1) continue;
|
||||
if (p>0) str += " " + operator["AND"] + " ";
|
||||
var neg = 0;
|
||||
if (sig.indexOf("/") != -1) {
|
||||
sig = sig.substring(1, sig.length);
|
||||
str += operator["NOT"];
|
||||
neg = 1;
|
||||
}
|
||||
|
||||
str += retSigName(sig);
|
||||
}
|
||||
if (pterms[pt].length > 1) str += operator["CLOSE_PTERM"];
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retFBMC(str) {
|
||||
return str.substring(0,str.length-2) + nlStr + tabStr;
|
||||
}
|
||||
|
||||
function retD1D2(signal) {
|
||||
var str = "";
|
||||
|
||||
dOneLit = true;
|
||||
if (d1[signal]) {
|
||||
var currImp = "";
|
||||
for (i=0; i<d1[signal].length; i++) {
|
||||
if (!eqnType && d1imp[signal] && (d1imp[signal][i] == "1")) {
|
||||
if ((currImp != retFBMC(d1[signal][i])) &&
|
||||
(d1[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(d1[signal][i]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(d1[signal][i]);
|
||||
}
|
||||
|
||||
if (d2[signal]) str += nlTabStr + operator["XOR"]+ spcStr;
|
||||
}
|
||||
|
||||
if (d2[signal]) {
|
||||
var currImp = "";
|
||||
for (i=0; i<d2[signal].length; i++) {
|
||||
if (!eqnType && d2imp[signal] && (d2imp[signal][i] == "1")) {
|
||||
if ((currImp != retFBMC(d2[signal][i])) &&
|
||||
(d2[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(d2[signal][i]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(d2[signal][i]);
|
||||
}
|
||||
}
|
||||
|
||||
if (str == "GND") str = operator["GND"];
|
||||
else if (str == "VCC") str = operator["VCC"];
|
||||
else if (!isOneLiteral(str)) {
|
||||
dOneLit = false;
|
||||
|
||||
var type = retSigType(retSigIndex(signal));
|
||||
if ((type == operator["FD"]) ||
|
||||
(type == operator["FDD"])) type = operator["_D"];
|
||||
else if ((type == operator["FT"]) ||
|
||||
(type == operator["FTD"])) type = operator["_T"];
|
||||
else if (type == operator["LD"] && eqnType) type = "_D";
|
||||
|
||||
var tmpStr = updateName(retSigName(signal), type);
|
||||
tmpStr += spcStr + operator["EQUAL_COLON"];
|
||||
var idx = retSigIndex(signal);
|
||||
if (eqnType && sigNegs[idx] == "ON") tmpStr += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
str = tmpStr + str;
|
||||
if (eqnType && sigNegs[idx] == "ON") str += operator["CLOSE_NEGATE"];
|
||||
str += operator["ENDLN"];
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retClk(signal) {
|
||||
var str = "";
|
||||
|
||||
if (clk[signal]) {
|
||||
if (clk[signal].length == 1) {
|
||||
var pterm = retPterm(clk[signal][0]);
|
||||
if (clkNegs[signal]) {
|
||||
str += operator["NOT"];
|
||||
if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"];
|
||||
}
|
||||
str += pterm;
|
||||
if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"];
|
||||
}
|
||||
else {
|
||||
if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
var currImp = "";
|
||||
for (i=0; i<clk[signal].length; i++) {
|
||||
if (!eqnType && clkimp[signal] && (clkimp[signal][i] == "1")) {
|
||||
if ((currImp != retFBMC(clk[signal][i])) &&
|
||||
(clk[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(clk[signal][i]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(clk[signal][i]);
|
||||
}
|
||||
if (clkNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
str += operator["ENDLN"];
|
||||
}
|
||||
}
|
||||
else if (gblclk[signal]) {
|
||||
if (gblclk[signal].length == 1) {
|
||||
var pterm = retPterm(gblclk[signal][0]);
|
||||
if (clkNegs[signal]) {
|
||||
str += operator["NOT"];
|
||||
if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"];
|
||||
}
|
||||
str += pterm;
|
||||
if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"];
|
||||
}
|
||||
else {
|
||||
if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
for (i=0; i<gblclk[signal].length; i++) {
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(gblclk[signal][i]);
|
||||
}
|
||||
if (clkNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
str += operator["ENDLN"] + tabStr + cClrS +
|
||||
operator["COMMENT"] + spcStr + operator["GCK_COM"] + cClrE;
|
||||
}
|
||||
}
|
||||
else if (eqnType) str += operator["B0"];
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retRst(signal) {
|
||||
var str = "";
|
||||
|
||||
if (rst[signal]) {
|
||||
if (rst[signal].length == 1) {
|
||||
var currImp;
|
||||
if (!eqnType && rstimp[signal] && (rstimp[signal][0] == "1")) {
|
||||
if ((currImp != retFBMC(rst[signal][i])) &&
|
||||
(rst[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(rst[signal][0]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (rstNegs[signal]) str += operator["NOT"];
|
||||
str += retPterm(rst[signal][0]);
|
||||
}
|
||||
else {
|
||||
var currImp = "";
|
||||
if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
for (i=0; i<rst[signal].length; i++) {
|
||||
if (!eqnType && rstimp[signal] && (rstimp[signal][i] == "1")) {
|
||||
if ((currImp != retFBMC(rst[signal][i])) &&
|
||||
(rst[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(rst[signal][i]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(rst[signal][i]);
|
||||
}
|
||||
if (rstNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
str += operator["ENDLN"];
|
||||
}
|
||||
}
|
||||
else if (gblrst[signal]) {
|
||||
if (gblrst[signal].length == 1) {
|
||||
if (rstNegs[signal]) str += operator["NOT"];
|
||||
str += retPterm(gblrst[signal][0]);
|
||||
}
|
||||
else {
|
||||
if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
for (i=0; i<gblrst[signal].length; i++) {
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(gblrst[signal][i]);
|
||||
}
|
||||
if (rstNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
str += operator["ENDLN"] + tabStr + cClrS +
|
||||
operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE;
|
||||
}
|
||||
}
|
||||
else if (eqnType) str += operator["B0"];
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retSet(signal) {
|
||||
var str = "";
|
||||
|
||||
if (set[signal]) {
|
||||
if (set[signal].length == 1) {
|
||||
var currImp = "";
|
||||
if (!eqnType && setimp[signal] && (setimp[signal][0] == "1")) {
|
||||
if ((currImp != retFBMC(set[signal][i])) &&
|
||||
(set[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(set[signal][0]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (setNegs[signal]) str += operator["NOT"];
|
||||
str += retPterm(set[signal][0]);
|
||||
}
|
||||
else {
|
||||
var currImp = "";
|
||||
if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
for (i=0; i<set[signal].length; i++) {
|
||||
if (!eqnType && setimp[signal] && (setimp[signal][i] == "1")) {
|
||||
if ((currImp != retFBMC(set[signal][i])) &&
|
||||
(set[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(set[signal][i]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(set[signal][i]);
|
||||
}
|
||||
if (setNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
str += operator["ENDLN"];
|
||||
}
|
||||
}
|
||||
else if (gblset[signal]) {
|
||||
if (gblset[signal].length == 1) {
|
||||
if (setNegs[signal]) str += operator["NOT"];
|
||||
str += retPterm(gblset[signal][0]);
|
||||
}
|
||||
else {
|
||||
if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
for (i=0; i<gblset[signal].length; i++) {
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(gblset[signal][i]);
|
||||
}
|
||||
if (setNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
str += operator["ENDLN"] + tabStr + cClrS +
|
||||
operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE;
|
||||
}
|
||||
}
|
||||
else if (eqnType) str += operator["B0"];
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retCE(signal) {
|
||||
var str = "";
|
||||
|
||||
if (ce[signal]) {
|
||||
if (ce[signal].length == 1) {
|
||||
var currImp = "";
|
||||
if (!eqnType && ceimp[signal] && (ceimp[signal][0] == "1")) {
|
||||
if ((currImp != retFBMC(ce[signal][i])) &&
|
||||
(ce[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(ce[signal][0]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (ceNegs[signal]) str += operator["NOT"];
|
||||
str += retPterm(ce[signal][0]);
|
||||
}
|
||||
else {
|
||||
var currImp = "";
|
||||
if (ceNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
for (i=0; i<ce[signal].length; i++) {
|
||||
if (!eqnType && ceimp[signal] && (ceimp[signal][i] == "1")) {
|
||||
if ((currImp != retFBMC(ce[signal][i])) &&
|
||||
(ce[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(ce[signal][i]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(ce[signal][i]);
|
||||
}
|
||||
if (ceNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
str += operator["ENDLN"];
|
||||
}
|
||||
}
|
||||
else if (eqnType) str += operator["B1"];
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retTrst(signal) {
|
||||
var str = "";
|
||||
if (trst[signal]) {
|
||||
if (trstNegs[signal])
|
||||
str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
for (i=0; i<trst[signal].length; i++) {
|
||||
var currImp = "";
|
||||
if (!eqnType && trstimp[signal] && (trstimp[signal][0] == "1")) {
|
||||
if ((currImp != retFBMC(trst[signal][i])) &&
|
||||
(trst[signal][i].indexOf("FB") == 0)) {
|
||||
currImp = retFBMC(trst[signal][0]);
|
||||
str += nlStr + operator["IMPORT"] + currImp;
|
||||
}
|
||||
}
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(trst[signal][i]);
|
||||
}
|
||||
if (trstNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
}
|
||||
else if (gbltrst[signal]) {
|
||||
if (trstNegs[signal])
|
||||
str += operator["NOT"] + operator["OPEN_NEGATE"];
|
||||
for (i=0; i<gbltrst[signal].length; i++) {
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(gbltrst[signal][i]);
|
||||
}
|
||||
if (trstNegs[signal]) str += operator["CLOSE_NEGATE"];
|
||||
}
|
||||
|
||||
str += operator["ENDLN"];
|
||||
return str;
|
||||
}
|
||||
|
||||
function retEqn(signal) {
|
||||
var str = inregStr = "";
|
||||
var iStr = qStr = "";
|
||||
var dStr = dEqn = "";
|
||||
var cStr = cEqn = "";
|
||||
var clrStr = clrEqn = "";
|
||||
var preStr = preEqn = "";
|
||||
var ceStr = ceEqn = "";
|
||||
var oeStr = oeEqn = "";
|
||||
var sigName = retSigName(signal);
|
||||
|
||||
var type = retSigType(retSigIndex(signal));
|
||||
|
||||
if (gbltrst[signal] || trst[signal]) iStr = operator["_I"];
|
||||
if (eqnType) qStr = updateName(sigName, iStr);
|
||||
|
||||
if (inreg[signal]) {
|
||||
if (!eqnType)
|
||||
inregStr = operator["COMMENT"] + " Direct Input Register" + nlStr;
|
||||
dStr = retSigName(inreg[signal][0]);
|
||||
}
|
||||
else dStr = retD1D2(signal);
|
||||
if (eqnType && !dOneLit) {
|
||||
dEqn = dStr;
|
||||
dStr = dStr.substring(0,dStr.indexOf(operator["EQUAL_COLON"]));
|
||||
}
|
||||
else if (!eqnType) {
|
||||
if (!dOneLit) dStr = dStr.substring(dStr.indexOf(operator["EQUAL_COLON"])+2);
|
||||
if (sigNegs[retSigIndex(signal)] == "ON") dEqn += operator["NOT"];
|
||||
dEqn += sigName;
|
||||
if ((type == operator["FT"]) ||
|
||||
(type == operator["FTD"])) dEqn += operator["_T"];
|
||||
else if ((type == operator["FD"]) ||
|
||||
(type == operator["FTD"])||
|
||||
(type == operator["LD"])) dEqn += operator["_D"];
|
||||
dEqn += " ";
|
||||
if ((type != operator["Q"]) && (type != operator["LD"]))
|
||||
dEqn += operator["EQUAL_COLON"];
|
||||
else dEqn += operator["EQUAL"];
|
||||
dEqn += dStr;
|
||||
if (dOneLit) {
|
||||
dEqn += operator["ENDLN"];
|
||||
if (iostyle[signal] && iostyle[signal].indexOf("OD"))
|
||||
dEqn += tabStr + operator["COMMENT"] + " " + operator["OD_COM"];
|
||||
}
|
||||
}
|
||||
|
||||
cStr = retClk(signal);
|
||||
if (eqnType && !isOneLiteral(cStr)){
|
||||
cEqn = cStr;
|
||||
if (cEqn.indexOf(operator["ENDLN"]) == -1)
|
||||
cEqn += operator["ENDLN"];
|
||||
cStr = updateName(sigName, operator["_C"]);
|
||||
}
|
||||
else if (!eqnType && cStr) {
|
||||
cEqn += cStr;
|
||||
cStr = tabStr + sigName;
|
||||
if (type == operator["LD"]) cStr += operator["_LH"];
|
||||
else if (type == operator["FDD"]) cStr += operator["_DEC"];
|
||||
else cStr += operator["_C"];
|
||||
if (cEqn.indexOf(operator["ENDLN"]) == -1)
|
||||
cEqn += operator["ENDLN"];
|
||||
if (gblclk[signal]) cEqn += tabStr + operator["COMMENT"] + " " + operator["GCK_COM"];
|
||||
}
|
||||
|
||||
clrStr = retRst(signal);
|
||||
if (eqnType && !isOneLiteral(clrStr)){
|
||||
clrEqn = clrStr;
|
||||
if (cEqn.indexOf(operator["ENDLN"]) == -1)
|
||||
clrEqn += operator["ENDLN"];
|
||||
clrStr = updateName(sigName, operator["_CLR"]);
|
||||
}
|
||||
else if (!eqnType && clrStr) {
|
||||
clrEqn += clrStr;
|
||||
clrStr = tabStr + sigName + operator["_CLR"];
|
||||
if (clrEqn.indexOf(operator["ENDLN"]) == -1)
|
||||
clrEqn += operator["ENDLN"];
|
||||
if (gblrst[signal]) clrEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"];
|
||||
}
|
||||
|
||||
preStr = retSet(signal);
|
||||
if (eqnType && !isOneLiteral(preStr)){
|
||||
preEqn = preStr;
|
||||
if (cEqn.indexOf(operator["ENDLN"]) == -1)
|
||||
preEqn += operator["ENDLN"];
|
||||
preStr = updateName(sigName, operator["_PRE"]);
|
||||
}
|
||||
else if (!eqnType && preStr) {
|
||||
preEqn += preStr;
|
||||
preStr = tabStr + sigName + operator["_PRE"];
|
||||
if (preEqn.indexOf(operator["ENDLN"]) == -1)
|
||||
preEqn += operator["ENDLN"];
|
||||
if (gblset[signal]) preEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"];
|
||||
}
|
||||
|
||||
if (!is9500()) {
|
||||
ceStr = retCE(signal);
|
||||
if (eqnType && !isOneLiteral(ceStr)){
|
||||
ceEqn = ceStr;
|
||||
if (cEqn.indexOf(operator["ENDLN"]) == -1)
|
||||
ceEqn += operator["ENDLN"];
|
||||
ceStr = updateName(sigName, operator["_CE"]);
|
||||
}
|
||||
else if (!eqnType && ceStr) {
|
||||
ceEqn += ceStr;
|
||||
ceStr = tabStr + sigName + operator["_CE"];
|
||||
if (ceEqn.indexOf(operator["ENDLN"]) == -1)
|
||||
ceEqn += operator["ENDLN"];
|
||||
}
|
||||
}
|
||||
|
||||
if (eqnType && gbltrst[signal]) oeEqn = retTrst(signal);
|
||||
else if (!eqnType && (trst[signal] || gbltrst[signal])) oeEqn = retTrst(signal);
|
||||
|
||||
var newline = false;
|
||||
if ((type == "") && (clrStr == "")) {
|
||||
str += operator["ASSIGN"] + qStr + " " + operator["EQUAL"];
|
||||
if (dOneLit) str += dStr;
|
||||
else str += dEqn.substring(dEqn.indexOf(operator["EQUAL"])+2);
|
||||
if (oeEqn != "") {
|
||||
var oeStr = updateName(sigName, operator["_OE"]);
|
||||
if (eqnType == 1) {
|
||||
str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr +
|
||||
operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] +
|
||||
operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"];
|
||||
}
|
||||
else if (eqnType == 2) {
|
||||
str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] +
|
||||
oeStr + operator["OE_WHEN"] + qStr +
|
||||
operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"];
|
||||
}
|
||||
str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (eqnType == 1) {
|
||||
str += type + "_" + removePar(retSigName(signal)) +
|
||||
": " + type + " " + operator["START_EQN"] +
|
||||
qStr + ", " + dStr + ", " + cStr + ", " +
|
||||
clrStr + ", " + preStr;
|
||||
if (!is9500() && (type != operator["LD"])) str += ", " + ceStr;
|
||||
str += operator["END_EQN"] + operator["ENDLN"];
|
||||
newline = true;
|
||||
}
|
||||
else if (eqnType == 2) {
|
||||
str += type + " " +
|
||||
type + "_" + removePar(retSigName(signal)) +
|
||||
operator["START_EQN"] +
|
||||
qStr + ", " + dStr + ", " + cStr + ", " +
|
||||
clrStr + ", " + preStr;
|
||||
if (!is9500() && (type != operator["LD"])) str += ", " + ceStr;
|
||||
str += operator["END_EQN"] + operator["ENDLN"];
|
||||
newline = true;
|
||||
}
|
||||
|
||||
if (dEqn != "") {
|
||||
if (newline) str += nlStr;
|
||||
if (inregStr) str += inregStr;
|
||||
str += operator["ASSIGN"] + dEqn;
|
||||
}
|
||||
|
||||
if (cEqn != "") {
|
||||
if (newline || !eqnType) str += nlStr;
|
||||
str += operator["ASSIGN"] + cStr + " " + operator["EQUAL"] + " " + cEqn;
|
||||
}
|
||||
|
||||
if (clrEqn != "") {
|
||||
if (newline || !eqnType) str += nlStr;
|
||||
str += operator["ASSIGN"] + clrStr + " " + operator["EQUAL"] + " " + clrEqn;
|
||||
}
|
||||
|
||||
|
||||
if (preEqn != "") {
|
||||
if (newline || !eqnType) str += nlStr;
|
||||
str += operator["ASSIGN"] + preStr + " " + operator["EQUAL"] + " " + preEqn;
|
||||
}
|
||||
|
||||
if (ceEqn != "") {
|
||||
if (newline || !eqnType) str += nlStr;
|
||||
str += operator["ASSIGN"] + ceStr + " " + operator["EQUAL"] + " " + ceEqn;
|
||||
}
|
||||
|
||||
if (oeEqn != "") {
|
||||
if (eqnType == 1) {
|
||||
// var oeStr = updateName(sigName, operator["_OE"]);
|
||||
var oeStr = sigName;
|
||||
str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr +
|
||||
operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] +
|
||||
operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"];
|
||||
// str += nlStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
|
||||
}
|
||||
else if (eqnType == 2) {
|
||||
// var oeStr = updateName(sigName, operator["_OE"]);
|
||||
var oeStr = sigName;
|
||||
str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + oeStr + operator["OE_WHEN"] + qStr +
|
||||
operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"];
|
||||
// str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
|
||||
}
|
||||
else {
|
||||
var oeStr = sigName + operator["_OE"];
|
||||
if (gbltrst[signal])
|
||||
oeEqn += tabStr + operator["COMMENT"] + " " + operator["GTS_COM"];
|
||||
str += nlStr + tabStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (iostyle[signal] && iostyle[signal].indexOf("OD")) {
|
||||
if (str.indexOf("//") == -1)
|
||||
str += tabStr + operator["COMMENT"] + " " + operator["OD_COM"];
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retFamily() {
|
||||
var family = "xc9500";
|
||||
if (device.indexOf("XC2C") != -1) {
|
||||
if (device.indexOf("S") != -1) family = "cr2s";
|
||||
else family = "xbr";
|
||||
}
|
||||
else if (device.indexOf("XCR3") != -1) family = "xpla3";
|
||||
else {
|
||||
if (device.indexOf("XL") != -1) family = "xc9500xl";
|
||||
if (device.indexOf("XV") != -1) family = "xc9500xv";
|
||||
}
|
||||
|
||||
return family;
|
||||
}
|
||||
|
||||
function retDesign() { return design; }
|
||||
|
||||
function getPterm(pt, type) {
|
||||
if (type) return type + " = " + retPterm(pt);
|
||||
return "PT" + pt.substring(pt.indexOf('_')+1,pt.length) + " = " + retPterm(pt);
|
||||
}
|
||||
|
||||
function getPRLDName(prld) {
|
||||
if (eqnType != 0) return prld;
|
||||
else if (prld == "VCC") return "S";
|
||||
return "R";
|
||||
}
|
||||
|
||||
function retFbnand(signal) {
|
||||
var str = operator["COMMENT"] + spcStr + "Foldback NAND";
|
||||
str += nlStr + retSigName(signal) + spcStr + operator["EQUAL"] + spcStr;
|
||||
for (i=0; i<fbnand[signal].length; i++) {
|
||||
if (i>0) str += nlTabStr + operator["OR"] + spcStr;
|
||||
str += retPterm(fbnand[signal][i]);
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function getEqn(signal) { return retEqn(signal); }
|
||||
|
||||
function retUimPterm(pt) {
|
||||
var str = "";
|
||||
if (!uimPterms[pt]) return pt;
|
||||
for (p=0; p<uimPterms[pt].length; p++) {
|
||||
if (p>0) str += spcStr + operator["AND"] + spcStr;
|
||||
var sig = uimPterms[pt][p];
|
||||
if (sig.indexOf("/") != -1) sig = sig.substring(1, sig.length);
|
||||
|
||||
str += retSigName(sig);
|
||||
}
|
||||
return str;
|
||||
}
|
||||
|
||||
function retUimEqn(signal) {
|
||||
var str = operator["COMMENT"] + spcStr + "FC Node" + nlStr;
|
||||
var neg = 0;
|
||||
if (uimSigNegs[s] == "ON") str += operator["NOT"];
|
||||
str += retSigName(signal) + spcStr + operator["EQUAL"];
|
||||
str += retUimPterm(signal) + ";";
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
function retLegend(url) {
|
||||
var str = "";
|
||||
if (!eqnType && !isXC95()) {
|
||||
str = "Legend: " + "<" + "signame" + ">" + ".COMB = combinational node mapped to ";
|
||||
str += "the same physical macrocell as the FastInput \"signal\" (not logically related)";
|
||||
}
|
||||
else if (eqnType) {
|
||||
str = "Register Legend:";
|
||||
if (is9500()) {
|
||||
str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE);";
|
||||
str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE);";
|
||||
str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);";
|
||||
}
|
||||
else if (retFamily() == "xbr") {
|
||||
str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);";
|
||||
str += nlTabStr + "FDDCPE (Q,D,C,CLR,PRE,CE);";
|
||||
str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);";
|
||||
str += nlTabStr + "FTDCPE (Q,D,C,CLR,PRE,CE);";
|
||||
str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);";
|
||||
}
|
||||
else {
|
||||
str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);";
|
||||
str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);";
|
||||
str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);";
|
||||
}
|
||||
}
|
||||
return str;
|
||||
}
|
||||
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 20 KiB |
|
|
@ -0,0 +1,13 @@
|
|||
<html>
|
||||
<head>
|
||||
<script>
|
||||
function init() {
|
||||
document.open();
|
||||
document.write(parent.leftnav.document.options.htmlStr.value);
|
||||
document.close();
|
||||
}
|
||||
</script>
|
||||
</head>
|
||||
<body onload="javascript:init()">
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
|
||||
|
||||
<html>
|
||||
|
||||
<!--(==============================================================)-->
|
||||
<!--(Document created with RoboEditor. )============================-->
|
||||
<!--(==============================================================)-->
|
||||
|
||||
<head>
|
||||
|
||||
<title>Equations</title>
|
||||
|
||||
<!--(Meta)==========================================================-->
|
||||
|
||||
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
|
||||
<meta name=generator-major-version content=0.1>
|
||||
<meta name=generator-minor-version content=1>
|
||||
<meta name=filetype content=kadov>
|
||||
<meta name=filetype-version content=1>
|
||||
<meta name=page-count content=1>
|
||||
<meta name=layout-height content=582>
|
||||
<meta name=layout-width content=798>
|
||||
<meta name=date content="05 1, 2002 4:30:09 PM">
|
||||
|
||||
|
||||
|
||||
</head>
|
||||
|
||||
<!--(Body)==========================================================-->
|
||||
|
||||
|
||||
<body>
|
||||
|
||||
<h1>Equations</h1>
|
||||
|
||||
<p><span style="font-size: 10pt; font-family: arial, sans-serif;">The Equations
|
||||
page provides a list of equations organized by signal name. <!--kadov_tag{{<spaces>}}--> <!--kadov_tag{{</spaces>}}-->You
|
||||
can use the pulldown menu in the left-hand frame of the page to select
|
||||
ABEL, VHDL, or Verilog as your language of display.</span> </p>
|
||||
|
||||
<p><img src="xml8.jpg"
|
||||
x-maintain-ratio=TRUE
|
||||
style="border: none;
|
||||
width: 181px;
|
||||
height: 448px;
|
||||
float: none;"
|
||||
width=181
|
||||
height=448
|
||||
border=0></p>
|
||||
|
||||
</body>
|
||||
|
||||
</html>
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
var infoList = new Array();
|
||||
var warnList = new Array();
|
||||
var errorList = new Array();
|
||||
|
||||
function updateError(type) {
|
||||
with (document.options) {
|
||||
switch (type) {
|
||||
case 0:
|
||||
if (info.checked) parent.leftnav.document.options.info.value = 1;
|
||||
else parent.leftnav.document.options.info.value = 0;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
if (warn.checked) parent.leftnav.document.options.warn.value = 1;
|
||||
else parent.leftnav.document.options.warn.value = 0;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
if (error.checked) parent.leftnav.document.options.error.value = 1;
|
||||
else parent.leftnav.document.options.error.value = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
parent.leftnav.showError();
|
||||
}
|
||||
|
||||
function init() {
|
||||
if (!document.options) return;
|
||||
with (document.options) {
|
||||
if (parent.leftnav.document.options.info.value == 1) info.checked = 1;
|
||||
else info.checked = 0;
|
||||
if (parent.leftnav.document.options.warn.value == 1) warn.checked = 1;
|
||||
else warn.checked = 0;
|
||||
if (parent.leftnav.document.options.error.value == 1) error.checked = 1;
|
||||
else error.checked = 0;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
function showError(url) { parent.leftnav.showErrorLink(url); }
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 5.5 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 3.5 KiB |
|
|
@ -0,0 +1,91 @@
|
|||
<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
|
||||
|
||||
<html>
|
||||
|
||||
<!--(==============================================================)-->
|
||||
<!--(Document created with RoboEditor. )============================-->
|
||||
<!--(==============================================================)-->
|
||||
|
||||
<head>
|
||||
|
||||
<title>Errors</title>
|
||||
|
||||
<!--(Meta)==========================================================-->
|
||||
|
||||
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
|
||||
<meta name=generator-major-version content=0.1>
|
||||
<meta name=generator-minor-version content=1>
|
||||
<meta name=filetype content=kadov>
|
||||
<meta name=filetype-version content=1>
|
||||
<meta name=page-count content=1>
|
||||
<meta name=layout-height content=715>
|
||||
<meta name=layout-width content=798>
|
||||
<meta name=date content="05 1, 2002 4:22:26 PM">
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
<!--
|
||||
p.whs1 {font-family: arial, sans-serif; font-size: 10pt;}
|
||||
p.whs2 {font-family: arial, sans-serif; font-size: 10pt;}
|
||||
p.whs3 {font-family: arial, sans-serif; font-size: 10pt;}
|
||||
|
||||
--></style><script language="javascript" title="WebHelpInlineScript">
|
||||
<!--
|
||||
function reDo() {
|
||||
if (innerWidth != origWidth || innerHeight != origHeight)
|
||||
location.reload();
|
||||
}
|
||||
if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
|
||||
origWidth = innerWidth;
|
||||
origHeight = innerHeight;
|
||||
onresize = reDo;
|
||||
}
|
||||
//-->
|
||||
</script><style>
|
||||
<!--
|
||||
div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
|
||||
p.WebHelpNavBar {text-align:right;}
|
||||
-->
|
||||
</style>
|
||||
</head>
|
||||
|
||||
<!--(Body)==========================================================-->
|
||||
|
||||
|
||||
<body>
|
||||
|
||||
|
||||
<h1>Errors/Warnings</h1>
|
||||
|
||||
<p class="whs1">The Errors/Warnings
|
||||
section of the report lists all of the error, warning, and information
|
||||
messages generated by the fitter. By default, this section will display
|
||||
the number of each kind of message you have and the full text of the messages,
|
||||
but checkboxes at the top of the screen allow you to filter message details
|
||||
as you choose. </p>
|
||||
|
||||
<p class="whs2">Checking all
|
||||
the boxes will give you a display like this:</p>
|
||||
|
||||
<p><SCRIPT LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='xml6.jpg' x-maintain-ratio='TRUE' width='540' height='254' border='0'>");}
|
||||
else
|
||||
{ document.write("<img src='xml6.jpg' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 254px; float: none;' width='540' height='254' border='0'>");}
|
||||
//--></SCRIPT></p>
|
||||
|
||||
<p class="whs3">Deselecting
|
||||
the Warning box in this particular example would result in this less detailed
|
||||
display:</p>
|
||||
|
||||
<p><SCRIPT LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='xml7.jpg' x-maintain-ratio='TRUE' width='576' height='226' border='0'>");}
|
||||
else
|
||||
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|
||||
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|
||||
|
||||
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|
||||
|
||||
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|
||||
|
|
@ -0,0 +1,13 @@
|
|||
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||||
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|
||||
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|
||||
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|
||||
</head>
|
||||
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|
||||
<span id="error" class="pgRef"><h3 align="center">Errors and Warnings</h3>
|
||||
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|
||||
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||||
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|
||||
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|
||||
</html>
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
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|
||||
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|
||||
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|
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|
||||
</head>
|
||||
<body class="pgBgnd">
|
||||
<h3 align="center">Failure Table</h3>
|
||||
<table width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th align="left">Signal Name</th>
|
||||
<th align="left">FB1</th>
|
||||
<th align="left">FB2</th>
|
||||
<th align="left">FB3</th>
|
||||
<th align="left">FB4</th>
|
||||
</tr>
|
||||
<tr class="pgHeader">
|
||||
<th align="left">Signal Name</th>
|
||||
<th align="left">FB5</th>
|
||||
<th align="left">FB6</th>
|
||||
<th align="left">FB7</th>
|
||||
<th align="left">FB8</th>
|
||||
</tr>
|
||||
</table>
|
||||
<table width="90%" border="1" cellpadding="0" cellspacing="0"><table width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr><td>Legend:</td></tr>
|
||||
<tr><td> ce - signal clock enable cannot be placed</td></tr>
|
||||
<tr><td> clk - signal clock cannot be placed</td></tr>
|
||||
<tr><td> fbi - insufficient function block inputs available to place signal</td></tr>
|
||||
<tr><td> io - insufficient I/O pins available to place output</td></tr>
|
||||
<tr><td> loc - signal cannot be placed in this FB because it is assigned to a different FB</td></tr>
|
||||
<tr><td> mc - insufficient macrocells available to place signal</td></tr>
|
||||
<tr><td> oe - signal output enable cannot be placed</td></tr>
|
||||
<tr><td> pt - insufficient product terms available to place signal</td></tr>
|
||||
<tr><td> sr - signal set/reset cannot be placed</td></tr>
|
||||
<tr><td> unk - unknown reason for failure - Please contact Xilinx Support</td></tr>
|
||||
</table></table>
|
||||
</body>
|
||||
<form><span class="pgRef"><table width="90%" align="center"><tr>
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<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
|
||||
</tr></table></span></form>
|
||||
</html>
|
||||
|
|
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|
|||
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|
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|
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|
||||
<html>
|
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<head>
|
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<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
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|
||||
<meta name="layout-height" content="1506">
|
||||
<meta name="layout-width" content="639">
|
||||
<meta name="date" content="05 24, 2002 5:49:09 PM">
|
||||
<meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD (Windows NT 5.0; U) [Netscape]">
|
||||
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||||
<title>Failure Table</title>
|
||||
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||||
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||||
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||||
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<!--(Body)==========================================================-->
|
||||
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|
||||
<body>
|
||||
|
||||
<h1>
|
||||
Failure Table</h1>
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
Failure Table section provides a table listing all logic failing to be
|
||||
placed as well as the cause for failure to fit for each individual Function
|
||||
Block. </font>The user can use this table to determine primary cause of
|
||||
failure and try to correct it.</span><!--begin!kadov{{-->
|
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<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><!--begin!kadov{{-->
|
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<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span
|
||||
style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
Failure Table contains the following: </font></span>
|
||||
<ul type="disc" class="whs1">
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
signal name </font></span></li>
|
||||
</ul>
|
||||
|
||||
<div class="whs2"><span style="font-weight: bold;
|
||||
font-family: arial, sans-serif;
|
||||
font-size: 10pt;"><font size=-1><b>Note:</span><span
|
||||
style="font-family: arial, sans-serif; font-size: 10pt;"></b>
|
||||
Clicking on the signal name will open a new window with the equations for
|
||||
that signal. </font></span></div>
|
||||
|
||||
<ul type="disc" class="whs3">
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>A
|
||||
column for each Function Block in device, with reason for failure to fit
|
||||
for each FB</font></span></li>
|
||||
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>A
|
||||
legend at the bottom listing all possible reasons for failure</font></span></li>
|
||||
</ul>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
Binary file not shown.
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@ -0,0 +1,77 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsum" class="pgRef"><h3 align="center">Function Blocks</h3>
|
||||
<table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th>Function Block</th>
|
||||
<th>Macrocells Used/Total</th>
|
||||
<th>Function Block Inputs Used/Total</th>
|
||||
<th>Product Terms Used/Total</th>
|
||||
<th>Pins Used/Total</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center"><a href="javascript:showFBDetail('FB1');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB1</a></td>
|
||||
<td align="center">7 / 18</td>
|
||||
<td align="center">37 / 54</td>
|
||||
<td align="center">81 / 90</td>
|
||||
<td align="center">10 / 11</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center"><a href="javascript:showFBDetail('FB2');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB2</a></td>
|
||||
<td align="center">18 / 18</td>
|
||||
<td align="center">25 / 54</td>
|
||||
<td align="center">49 / 90</td>
|
||||
<td align="center">6 / 10</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center"><a href="javascript:showFBDetail('FB3');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB3</a></td>
|
||||
<td align="center">14 / 18</td>
|
||||
<td align="center">39 / 54</td>
|
||||
<td align="center">81 / 90</td>
|
||||
<td align="center">6 / 10</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center"><a href="javascript:showFBDetail('FB4');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB4</a></td>
|
||||
<td align="center">9 / 18</td>
|
||||
<td align="center">25 / 54</td>
|
||||
<td align="center">81 / 90</td>
|
||||
<td align="center">10 / 10</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center"><a href="javascript:showFBDetail('FB5');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB5</a></td>
|
||||
<td align="center">4 / 18</td>
|
||||
<td align="center">7 / 54</td>
|
||||
<td align="center">4 / 90</td>
|
||||
<td align="center">3 / 10</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center"><a href="javascript:showFBDetail('FB6');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB6</a></td>
|
||||
<td align="center">18 / 18</td>
|
||||
<td align="center">23 / 54</td>
|
||||
<td align="center">26 / 90</td>
|
||||
<td align="center">10 / 10</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center"><a href="javascript:showFBDetail('FB7');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB7</a></td>
|
||||
<td align="center">18 / 18</td>
|
||||
<td align="center">22 / 54</td>
|
||||
<td align="center">34 / 90</td>
|
||||
<td align="center">10 / 10</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center"><a href="javascript:showFBDetail('FB8');" onmouseover="window.status='goto Function Block detail'; return true;" onmouseout="window.status=''">FB8</a></td>
|
||||
<td align="center">18 / 18</td>
|
||||
<td align="center">36 / 54</td>
|
||||
<td align="center">55 / 90</td>
|
||||
<td align="center">10 / 10</td>
|
||||
</tr>
|
||||
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|
||||
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||||
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|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
function showFBApplet(fb) { parent.leftnav.showAppletFB(fb); }
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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@ -0,0 +1,264 @@
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|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
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||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
|
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|
||||
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|
||||
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|
||||
<option value="FB3">FB3</option>
|
||||
<option value="FB4">FB4</option>
|
||||
<option value="FB5">FB5</option>
|
||||
<option value="FB6">FB6</option>
|
||||
<option value="FB7">FB7</option>
|
||||
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|
||||
<td width="33%" valign="center" align="right"></td>
|
||||
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|
||||
<tr class="pgHeader">
|
||||
<th width="10%">Signal Name</th>
|
||||
<th width="10%">Total Product Terms</th>
|
||||
<th width="30%">Product Terms</th>
|
||||
<th width="10%">Location</th>
|
||||
<th width="10%">Power Mode</th>
|
||||
<th width="10%">Pin Number</th>
|
||||
<th width="10%">PinType</th>
|
||||
<th width="10%">Pin Use</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC1</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC2</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">11</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<11>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nDTACK_FSB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nDTACK_FSB</a></td>
|
||||
<td align="center" width="10%">25</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB1_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB1_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a> <a href="Javascript:showPT('FB1_2_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_3</a> <a href="Javascript:showPT('FB1_2_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_4</a> <a href="Javascript:showPT('FB1_2_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_5</a> <a href="Javascript:showPT('FB1_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a> <a href="Javascript:showPT('FB1_3_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_2</a> <a href="Javascript:showPT('FB1_3_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_3</a> <a href="Javascript:showPT('FB1_3_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_4</a> <a href="Javascript:showPT('FB1_3_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_5</a> <a href="Javascript:showPT('FB1_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a> <a href="Javascript:showPT('FB1_4_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_2</a> <a href="Javascript:showPT('FB1_4_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_3</a> <a href="Javascript:showPT('FB1_4_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_4</a> <a href="Javascript:showPT('FB1_4_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_5</a> <a href="Javascript:showPT('FB1_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a> <a href="Javascript:showPT('FB1_5_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_2</a> <a href="Javascript:showPT('FB1_5_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_3</a> <a href="Javascript:showPT('FB1_5_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_4</a> <a href="Javascript:showPT('FB1_5_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_5</a> <a href="Javascript:showPT('FB1_6_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_1</a> <a href="Javascript:showPT('FB1_6_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_2</a> <a href="Javascript:showPT('FB1_6_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_3</a> <a href="Javascript:showPT('FB1_6_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_4</a> <a href="Javascript:showPT('FB1_6_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC3</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">12</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC4</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC5</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">13</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<13>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC6</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">14</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<14>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC7</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC8</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">15</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<15>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nADoutLE1')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nADoutLE1</a></td>
|
||||
<td align="center" width="10%">13</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB1_10_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_3</a> <a href="Javascript:showPT('FB1_10_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_4</a> <a href="Javascript:showPT('FB1_10_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_5</a> <a href="Javascript:showPT('FB1_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('FB1_8_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_2</a> <a href="Javascript:showPT('FB1_8_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_3</a> <a href="Javascript:showPT('FB1_8_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_4</a> <a href="Javascript:showPT('FB1_8_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_5</a> <a href="Javascript:showPT('FB1_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a> <a href="Javascript:showPT('FB1_9_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_2</a> <a href="Javascript:showPT('FB1_9_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_3</a> <a href="Javascript:showPT('FB1_9_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_4</a> <a href="Javascript:showPT('FB1_9_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC9</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">16</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('fsbBERR0r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/BERR0r</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB1_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a> <a href="Javascript:showPT('FB1_10_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_2</a> <a href="Javascript:showPT('FB1_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC10</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC11</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">17</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<1>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('fsbReady2r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/Ready2r</a></td>
|
||||
<td align="center" width="10%">5</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB1_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a> <a href="Javascript:showPT('FB1_12_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_2</a> <a href="Javascript:showPT('FB1_12_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_3</a> <a href="Javascript:showPT('FB1_12_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_4</a> <a href="Javascript:showPT('FB1_12_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC12</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">18</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<2>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC13</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('OpTxINV223_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$INV$223</a></td>
|
||||
<td align="center" width="10%">10</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB1_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB1_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a> <a href="Javascript:showPT('FB1_13_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_3</a> <a href="Javascript:showPT('FB1_13_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_4</a> <a href="Javascript:showPT('FB1_13_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_5</a> <a href="Javascript:showPT('FB1_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB1_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a> <a href="Javascript:showPT('FB1_14_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_3</a> <a href="Javascript:showPT('FB1_14_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_4</a> <a href="Javascript:showPT('FB1_14_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC14</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">19</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<6>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC15</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">20</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'nUDS_FSB'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('IORW0')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IORW0</a></td>
|
||||
<td align="center" width="10%">14</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB1_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB1_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a> <a href="Javascript:showPT('FB1_15_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_3</a> <a href="Javascript:showPT('FB1_15_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_4</a> <a href="Javascript:showPT('FB1_15_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_5</a> <a href="Javascript:showPT('FB1_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB1_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB1_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB1_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a> <a href="Javascript:showPT('FB1_16_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_5</a> <a href="Javascript:showPT('FB1_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a> <a href="Javascript:showPT('FB1_17_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_3</a> <a href="Javascript:showPT('FB1_17_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_4</a> <a href="Javascript:showPT('FB1_17_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC16</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('IOREQ')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOREQ</a></td>
|
||||
<td align="center" width="10%">11</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB1_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a> <a href="Javascript:showPT('FB1_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB1_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB1_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB1_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB1_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a> <a href="Javascript:showPT('FB1_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('FB1_1_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_2</a> <a href="Javascript:showPT('FB1_1_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_3</a> <a href="Javascript:showPT('FB1_1_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_4</a> <a href="Javascript:showPT('FB1_1_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC17</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">22</td>
|
||||
<td width="8%" align="center">I/O/GCK1</td>
|
||||
<td align="center" width="10%">GCK</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC18</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
</table></span></div>
|
||||
<div id="tipBox"></div>
|
||||
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
|
||||
<li>A_FSB<10></li>
|
||||
<li>A_FSB<11></li>
|
||||
<li>A_FSB<12></li>
|
||||
<li>A_FSB<13></li>
|
||||
<li>A_FSB<14></li>
|
||||
<li>A_FSB<15></li>
|
||||
<li>A_FSB<16></li>
|
||||
<li>A_FSB<17></li>
|
||||
<li>A_FSB<18></li>
|
||||
<li>A_FSB<19></li>
|
||||
<li>A_FSB<20></li>
|
||||
<li>A_FSB<21></li>
|
||||
<li>A_FSB<22></li>
|
||||
<li>A_FSB<23></li>
|
||||
<li>A_FSB<9></li>
|
||||
<li><a href="Javascript:showEqn('BERR_IOBS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">BERR_IOBS</a></li>
|
||||
<li><a href="Javascript:showEqn('IORW0')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IORW0</a></li>
|
||||
<li><a href="Javascript:showEqn('TimeoutA')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">TimeoutA</a></li>
|
||||
<li><a href="Javascript:showEqn('TimeoutB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">TimeoutB</a></li>
|
||||
<li><a href="Javascript:showEqn('csnOverlay1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cs/nOverlay1</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbASrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/ASrf</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbBERR0r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/BERR0r</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbBERR1r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/BERR1r</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbReady0r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/Ready0r</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbReady1r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/Ready1r</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbReady2r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/Ready2r</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsIOACTr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOACTr</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsIORW1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IORW1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsIOReady_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOReady</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsOnce_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/Once</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsPS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/PS_FSM_FFd1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsPS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/PS_FSM_FFd2</a></li>
|
||||
<li><a href="Javascript:showEqn('nADoutLE1')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nADoutLE1</a></li>
|
||||
<li>nAS_FSB</li>
|
||||
<li><a href="Javascript:showEqn('nDTACK_FSB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nDTACK_FSB</a></li>
|
||||
<li>nWE_FSB</li>
|
||||
<li><a href="Javascript:showEqn('ramRAMReady_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMReady</a></li>
|
||||
</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center"><input type="button" onclick="javascript:showFB('FB2')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next"></td></tr></table></td>
|
||||
<td align="right">
|
||||
<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
|
||||
</td>
|
||||
</tr></table></span></form>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,267 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
|
||||
<td width="33%" valign="center" align="left"></td>
|
||||
<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
|
||||
<option value="FB2" selected>FB2</option>
|
||||
<option value="FB3">FB3</option>
|
||||
<option value="FB4">FB4</option>
|
||||
<option value="FB5">FB5</option>
|
||||
<option value="FB6">FB6</option>
|
||||
<option value="FB7">FB7</option>
|
||||
<option value="FB8">FB8</option></select></form></td>
|
||||
<td width="33%" valign="center" align="right"></td>
|
||||
</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th width="10%">Signal Name</th>
|
||||
<th width="10%">Total Product Terms</th>
|
||||
<th width="30%">Product Terms</th>
|
||||
<th width="10%">Location</th>
|
||||
<th width="10%">Power Mode</th>
|
||||
<th width="10%">Pin Number</th>
|
||||
<th width="10%">PinType</th>
|
||||
<th width="10%">Pin Use</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOS_FSM_FFd7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd7</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC1</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOS_FSM_FFd6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd6</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC2</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">99</td>
|
||||
<td width="8%" align="center">I/O/GSR</td>
|
||||
<td align="center" width="10%">GSR/I</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOS_FSM_FFd5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd5</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC3</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOS_FSM_FFd4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd4</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC4</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd1</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC5</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td width="8%" align="center">I/O/GTS3</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmBERRrr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/BERRrr</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_6_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC6</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td width="8%" align="center">I/O/GTS4</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmBERRrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/BERRrf</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_7_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC7</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOS_FSM_FFd8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd8</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('FB2_8_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC8</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td width="8%" align="center">I/O/GTS1</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ALE0M')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ALE0M</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a> <a href="Javascript:showPT('FB2_9_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC9</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">4</td>
|
||||
<td width="8%" align="center">I/O/GTS2</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd2</a></td>
|
||||
<td align="center" width="10%">4</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a> <a href="Javascript:showPT('FB2_10_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_2</a> <a href="Javascript:showPT('FB2_10_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_3</a> <a href="Javascript:showPT('FB2_10_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_4</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC10</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nLDS_IOB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nLDS_IOB</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a> <a href="Javascript:showPT('FB2_11_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_2</a> <a href="Javascript:showPT('FB2_11_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC11</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">6</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nUDS_IOB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nUDS_IOB</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a> <a href="Javascript:showPT('FB2_12_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_2</a> <a href="Javascript:showPT('FB2_12_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC12</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">7</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOS_FSM_FFd3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd3</a></td>
|
||||
<td align="center" width="10%">5</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB2_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a> <a href="Javascript:showPT('FB2_13_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_3</a> <a href="Javascript:showPT('FB2_13_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_4</a> <a href="Javascript:showPT('FB2_13_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC13</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<0></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB2_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC14</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">8</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nDoutOE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nDoutOE</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB2_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC15</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">9</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('IOBERR')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOBERR</a></td>
|
||||
<td align="center" width="10%">8</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_15_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_3</a> <a href="Javascript:showPT('FB2_15_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_4</a> <a href="Javascript:showPT('FB2_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB2_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB2_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB2_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a> <a href="Javascript:showPT('FB2_16_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_5</a> <a href="Javascript:showPT('FB2_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC16</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nAS_IOB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nAS_IOB</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC17</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">10</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('IOACT')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOACT</a></td>
|
||||
<td align="center" width="10%">10</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB2_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB2_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB2_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB2_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB2_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a> <a href="Javascript:showPT('FB2_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('FB2_1_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_2</a> <a href="Javascript:showPT('FB2_1_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_3</a> <a href="Javascript:showPT('FB2_1_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_4</a> <a href="Javascript:showPT('FB2_1_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC18</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
</table></span></div>
|
||||
<div id="tipBox"></div>
|
||||
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
|
||||
<li>A_FSB<10></li>
|
||||
<li>A_FSB<1></li>
|
||||
<li>CLK_IOB</li>
|
||||
<li><a href="Javascript:showEqn('IOBERR')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOBERR</a></li>
|
||||
<li><a href="Javascript:showEqn('IOL0')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOL0</a></li>
|
||||
<li><a href="Javascript:showEqn('IORW0')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IORW0</a></li>
|
||||
<li><a href="Javascript:showEqn('IOU0')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOU0</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmBERRrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/BERRrf</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmBERRrr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/BERRrr</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmDTACKrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/DTACKrf</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmDTACKrr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/DTACKrr</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmETACK_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ETACK</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOREQr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOREQr</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd2</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd3</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd4</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd5</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd6</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd7</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd8</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmRESrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/RESrf</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmRESrr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/RESrr</a></li>
|
||||
<li>nBERR_IOB</li>
|
||||
<li><a href="Javascript:showEqn('ramRASEL_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RASEL</a></li>
|
||||
</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
|
||||
<input type="button" onclick="javascript:showFB('FB1')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
|
||||
|
||||
<input type="button" onclick="javascript:showFB('FB3')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
|
||||
</td></tr></table></td>
|
||||
<td align="right">
|
||||
<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
|
||||
</td>
|
||||
</tr></table></span></form>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
|
||||
<td width="33%" valign="center" align="left"></td>
|
||||
<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
|
||||
<option value="FB2">FB2</option>
|
||||
<option value="FB3" selected>FB3</option>
|
||||
<option value="FB4">FB4</option>
|
||||
<option value="FB5">FB5</option>
|
||||
<option value="FB6">FB6</option>
|
||||
<option value="FB7">FB7</option>
|
||||
<option value="FB8">FB8</option></select></form></td>
|
||||
<td width="33%" valign="center" align="right"></td>
|
||||
</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th width="10%">Signal Name</th>
|
||||
<th width="10%">Total Product Terms</th>
|
||||
<th width="30%">Product Terms</th>
|
||||
<th width="10%">Location</th>
|
||||
<th width="10%">Power Mode</th>
|
||||
<th width="10%">Pin Number</th>
|
||||
<th width="10%">PinType</th>
|
||||
<th width="10%">Pin Use</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC1</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC2</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">23</td>
|
||||
<td width="8%" align="center">I/O/GCK2</td>
|
||||
<td align="center" width="10%">GCK</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsIORW1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IORW1</a></td>
|
||||
<td align="center" width="10%">15</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB3_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a> <a href="Javascript:showPT('FB3_2_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_3</a> <a href="Javascript:showPT('FB3_2_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_4</a> <a href="Javascript:showPT('FB3_2_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_5</a> <a href="Javascript:showPT('FB3_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a> <a href="Javascript:showPT('FB3_3_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_2</a> <a href="Javascript:showPT('FB3_3_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_3</a> <a href="Javascript:showPT('FB3_3_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_4</a> <a href="Javascript:showPT('FB3_3_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_5</a> <a href="Javascript:showPT('FB3_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a> <a href="Javascript:showPT('FB3_4_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_2</a> <a href="Javascript:showPT('FB3_4_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_3</a> <a href="Javascript:showPT('FB3_4_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_4</a> <a href="Javascript:showPT('FB3_4_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC3</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmETACK_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ETACK</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_5_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_4</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC4</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nRAS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nRAS</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a> <a href="Javascript:showPT('FB3_5_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_2</a> <a href="Javascript:showPT('FB3_5_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC5</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">24</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsPS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/PS_FSM_FFd1</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_6_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_1</a> <a href="Javascript:showPT('FB3_6_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC6</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">25</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<5>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsIOReady_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOReady</a></td>
|
||||
<td align="center" width="10%">4</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_7_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_1</a> <a href="Javascript:showPT('FB3_7_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_2</a> <a href="Javascript:showPT('FB3_7_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_3</a> <a href="Javascript:showPT('FB3_7_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_4</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC7</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('BERR_IOBS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">BERR_IOBS</a></td>
|
||||
<td align="center" width="10%">4</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_7_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_5</a> <a href="Javascript:showPT('FB3_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('FB3_8_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_2</a> <a href="Javascript:showPT('FB3_8_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC8</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">27</td>
|
||||
<td width="8%" align="center">I/O/GCK3</td>
|
||||
<td align="center" width="10%">GCK/I</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramRS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd1</a></td>
|
||||
<td align="center" width="10%">5</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_8_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_4</a> <a href="Javascript:showPT('FB3_8_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_5</a> <a href="Javascript:showPT('FB3_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a> <a href="Javascript:showPT('FB3_9_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_2</a> <a href="Javascript:showPT('FB3_9_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC9</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">28</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'nVPA_IOB'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramOnce_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/Once</a></td>
|
||||
<td align="center" width="10%">5</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a> <a href="Javascript:showPT('FB3_10_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_2</a> <a href="Javascript:showPT('FB3_10_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_3</a> <a href="Javascript:showPT('FB3_9_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_3</a> <a href="Javascript:showPT('FB3_9_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC10</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nVMA_IOB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nVMA_IOB</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_10_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_4</a> <a href="Javascript:showPT('FB3_10_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC11</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">29</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsPS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/PS_FSM_FFd2</a></td>
|
||||
<td align="center" width="10%">10</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a> <a href="Javascript:showPT('FB3_11_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_2</a> <a href="Javascript:showPT('FB3_11_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_3</a> <a href="Javascript:showPT('FB3_11_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_4</a> <a href="Javascript:showPT('FB3_11_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_5</a> <a href="Javascript:showPT('FB3_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a> <a href="Javascript:showPT('FB3_12_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_2</a> <a href="Javascript:showPT('FB3_12_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_3</a> <a href="Javascript:showPT('FB3_12_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_4</a> <a href="Javascript:showPT('FB3_12_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC12</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">30</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC13</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsOnce_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/Once</a></td>
|
||||
<td align="center" width="10%">11</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB3_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a> <a href="Javascript:showPT('FB3_13_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_3</a> <a href="Javascript:showPT('FB3_13_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_4</a> <a href="Javascript:showPT('FB3_13_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_5</a> <a href="Javascript:showPT('FB3_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB3_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a> <a href="Javascript:showPT('FB3_14_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_3</a> <a href="Javascript:showPT('FB3_14_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_4</a> <a href="Javascript:showPT('FB3_14_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_5</a> <a href="Javascript:showPT('FB3_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC14</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">32</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nRAMLWE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nRAMLWE</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC15</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">33</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('fsbReady1r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/Ready1r</a></td>
|
||||
<td align="center" width="10%">5</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB3_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB3_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB3_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a> <a href="Javascript:showPT('FB3_16_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC16</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC17</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">34</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsLoad1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/Load1</a></td>
|
||||
<td align="center" width="10%">13</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB3_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a> <a href="Javascript:showPT('FB3_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a> <a href="Javascript:showPT('FB3_17_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_3</a> <a href="Javascript:showPT('FB3_17_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_4</a> <a href="Javascript:showPT('FB3_17_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_5</a> <a href="Javascript:showPT('FB3_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB3_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB3_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB3_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB3_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a> <a href="Javascript:showPT('FB3_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('FB3_1_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_2</a> <a href="Javascript:showPT('FB3_1_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC18</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
</table></span></div>
|
||||
<div id="tipBox"></div>
|
||||
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
|
||||
<li>A_FSB<16></li>
|
||||
<li>A_FSB<17></li>
|
||||
<li>A_FSB<18></li>
|
||||
<li>A_FSB<19></li>
|
||||
<li>A_FSB<20></li>
|
||||
<li>A_FSB<21></li>
|
||||
<li>A_FSB<22></li>
|
||||
<li>A_FSB<23></li>
|
||||
<li><a href="Javascript:showEqn('BERR_IOBS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">BERR_IOBS</a></li>
|
||||
<li><a href="Javascript:showEqn('IOACT')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOACT</a></li>
|
||||
<li><a href="Javascript:showEqn('IOBERR')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOBERR</a></li>
|
||||
<li><a href="Javascript:showEqn('RefAck')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RefAck</a></li>
|
||||
<li><a href="Javascript:showEqn('csnOverlay1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cs/nOverlay1</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbASrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/ASrf</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbReady1r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/Ready1r</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<0></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<1></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<2></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<3></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<4></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmVPArf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/VPArf</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmVPArr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/VPArr</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsIOACTr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOACTr</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsIORW1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IORW1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsIOReady_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOReady</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsOnce_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/Once</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsPS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/PS_FSM_FFd1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsPS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/PS_FSM_FFd2</a></li>
|
||||
<li><a href="Javascript:showEqn('nADoutLE1')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nADoutLE1</a></li>
|
||||
<li>nAS_FSB</li>
|
||||
<li>nLDS_FSB</li>
|
||||
<li><a href="Javascript:showEqn('nVMA_IOB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nVMA_IOB</a></li>
|
||||
<li>nWE_FSB</li>
|
||||
<li><a href="Javascript:showEqn('ramOnce_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/Once</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRAMDIS1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMDIS1</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRAMDIS2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMDIS2</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd1</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd2</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd3</a></li>
|
||||
</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
|
||||
<input type="button" onclick="javascript:showFB('FB2')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
|
||||
|
||||
<input type="button" onclick="javascript:showFB('FB4')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
|
||||
</td></tr></table></td>
|
||||
<td align="right">
|
||||
<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
|
||||
</td>
|
||||
</tr></table></span></form>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
|
||||
<td width="33%" valign="center" align="left"></td>
|
||||
<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
|
||||
<option value="FB2">FB2</option>
|
||||
<option value="FB3">FB3</option>
|
||||
<option value="FB4" selected>FB4</option>
|
||||
<option value="FB5">FB5</option>
|
||||
<option value="FB6">FB6</option>
|
||||
<option value="FB7">FB7</option>
|
||||
<option value="FB8">FB8</option></select></form></td>
|
||||
<td width="33%" valign="center" align="right"></td>
|
||||
</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th width="10%">Signal Name</th>
|
||||
<th width="10%">Total Product Terms</th>
|
||||
<th width="30%">Product Terms</th>
|
||||
<th width="10%">Location</th>
|
||||
<th width="10%">Power Mode</th>
|
||||
<th width="10%">Pin Number</th>
|
||||
<th width="10%">PinType</th>
|
||||
<th width="10%">Pin Use</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC1</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<1></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('FB4_1_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC2</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">87</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC3</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramRS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd2</a></td>
|
||||
<td align="center" width="10%">13</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB4_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a> <a href="Javascript:showPT('FB4_2_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_3</a> <a href="Javascript:showPT('FB4_2_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_4</a> <a href="Javascript:showPT('FB4_2_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_5</a> <a href="Javascript:showPT('FB4_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a> <a href="Javascript:showPT('FB4_3_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_2</a> <a href="Javascript:showPT('FB4_3_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_3</a> <a href="Javascript:showPT('FB4_3_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_4</a> <a href="Javascript:showPT('FB4_3_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_5</a> <a href="Javascript:showPT('FB4_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a> <a href="Javascript:showPT('FB4_4_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_2</a> <a href="Javascript:showPT('FB4_4_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC4</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC5</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">89</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<16>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramRASEL_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RASEL</a></td>
|
||||
<td align="center" width="10%">20</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_4_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_4</a> <a href="Javascript:showPT('FB4_4_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_5</a> <a href="Javascript:showPT('FB4_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a> <a href="Javascript:showPT('FB4_5_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_2</a> <a href="Javascript:showPT('FB4_5_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_3</a> <a href="Javascript:showPT('FB4_5_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_4</a> <a href="Javascript:showPT('FB4_5_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_5</a> <a href="Javascript:showPT('FB4_6_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_1</a> <a href="Javascript:showPT('FB4_6_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_2</a> <a href="Javascript:showPT('FB4_6_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_3</a> <a href="Javascript:showPT('FB4_6_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_4</a> <a href="Javascript:showPT('FB4_6_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_5</a> <a href="Javascript:showPT('FB4_7_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_1</a> <a href="Javascript:showPT('FB4_7_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_2</a> <a href="Javascript:showPT('FB4_7_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_3</a> <a href="Javascript:showPT('FB4_7_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_4</a> <a href="Javascript:showPT('FB4_7_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_5</a> <a href="Javascript:showPT('FB4_8_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_3</a> <a href="Javascript:showPT('FB4_8_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_4</a> <a href="Javascript:showPT('FB4_8_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC6</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">90</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<17>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC7</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<5></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('FB4_8_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC8</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">91</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC9</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">92</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<18>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramRAMDIS1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMDIS1</a></td>
|
||||
<td align="center" width="10%">18</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a> <a href="Javascript:showPT('FB4_10_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_2</a> <a href="Javascript:showPT('FB4_10_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_3</a> <a href="Javascript:showPT('FB4_10_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_4</a> <a href="Javascript:showPT('FB4_10_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_5</a> <a href="Javascript:showPT('FB4_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a> <a href="Javascript:showPT('FB4_11_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_2</a> <a href="Javascript:showPT('FB4_11_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_3</a> <a href="Javascript:showPT('FB4_11_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_4</a> <a href="Javascript:showPT('FB4_11_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_5</a> <a href="Javascript:showPT('FB4_12_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_3</a> <a href="Javascript:showPT('FB4_12_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_4</a> <a href="Javascript:showPT('FB4_12_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_5</a> <a href="Javascript:showPT('FB4_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a> <a href="Javascript:showPT('FB4_9_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_2</a> <a href="Javascript:showPT('FB4_9_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_3</a> <a href="Javascript:showPT('FB4_9_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_4</a> <a href="Javascript:showPT('FB4_9_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC10</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC11</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">93</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<20>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nDinOE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nDinOE</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a> <a href="Javascript:showPT('FB4_12_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC12</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">94</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC13</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramRAMReady_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMReady</a></td>
|
||||
<td align="center" width="10%">16</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB4_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a> <a href="Javascript:showPT('FB4_13_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_3</a> <a href="Javascript:showPT('FB4_13_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_4</a> <a href="Javascript:showPT('FB4_13_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_5</a> <a href="Javascript:showPT('FB4_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB4_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a> <a href="Javascript:showPT('FB4_14_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_3</a> <a href="Javascript:showPT('FB4_14_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_4</a> <a href="Javascript:showPT('FB4_14_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_5</a> <a href="Javascript:showPT('FB4_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB4_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a> <a href="Javascript:showPT('FB4_15_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_3</a> <a href="Javascript:showPT('FB4_15_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_4</a> <a href="Javascript:showPT('FB4_15_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_5</a> <a href="Javascript:showPT('FB4_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC14</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">95</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<22>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC15</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">96</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<7>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC16</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nRAMUWE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nRAMUWE</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC17</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">97</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramRAMDIS2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMDIS2</a></td>
|
||||
<td align="center" width="10%">7</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB4_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a> <a href="Javascript:showPT('FB4_17_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_3</a> <a href="Javascript:showPT('FB4_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB4_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB4_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB4_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB4_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC18</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
</table></span></div>
|
||||
<div id="tipBox"></div>
|
||||
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
|
||||
<li>A_FSB<11></li>
|
||||
<li>A_FSB<15></li>
|
||||
<li>A_FSB<20></li>
|
||||
<li>A_FSB<21></li>
|
||||
<li>A_FSB<22></li>
|
||||
<li>A_FSB<23></li>
|
||||
<li>A_FSB<2></li>
|
||||
<li>A_FSB<6></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<5></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<6></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<7></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefDone_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefDone</a></li>
|
||||
<li><a href="Javascript:showEqn('csnOverlay1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cs/nOverlay1</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbASrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/ASrf</a></li>
|
||||
<li>nAS_FSB</li>
|
||||
<li>nUDS_FSB</li>
|
||||
<li>nWE_FSB</li>
|
||||
<li><a href="Javascript:showEqn('ramBACTr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/BACTr</a></li>
|
||||
<li><a href="Javascript:showEqn('ramOnce_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/Once</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRAMDIS1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMDIS1</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRAMDIS2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMDIS2</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRASEL_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RASEL</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd1</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd2</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd3</a></li>
|
||||
</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
|
||||
<input type="button" onclick="javascript:showFB('FB3')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
|
||||
|
||||
<input type="button" onclick="javascript:showFB('FB5')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
|
||||
</td></tr></table></td>
|
||||
<td align="right">
|
||||
<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
|
||||
</td>
|
||||
</tr></table></span></form>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,235 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
|
||||
<td width="33%" valign="center" align="left"></td>
|
||||
<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
|
||||
<option value="FB2">FB2</option>
|
||||
<option value="FB3">FB3</option>
|
||||
<option value="FB4">FB4</option>
|
||||
<option value="FB5" selected>FB5</option>
|
||||
<option value="FB6">FB6</option>
|
||||
<option value="FB7">FB7</option>
|
||||
<option value="FB8">FB8</option></select></form></td>
|
||||
<td width="33%" valign="center" align="right"></td>
|
||||
</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th width="10%">Signal Name</th>
|
||||
<th width="10%">Total Product Terms</th>
|
||||
<th width="30%">Product Terms</th>
|
||||
<th width="10%">Location</th>
|
||||
<th width="10%">Power Mode</th>
|
||||
<th width="10%">Pin Number</th>
|
||||
<th width="10%">PinType</th>
|
||||
<th width="10%">Pin Use</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC1</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nROMCS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nROMCS</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB5_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB5_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC2</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">35</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC3</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC4</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC5</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">36</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC6</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">37</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC7</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC8</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">39</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC9</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">40</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC10</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC11</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">41</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC12</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">42</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC13</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC14</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">43</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%">(unused)</td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> </td>
|
||||
<td align="center" width="10%">MC15</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">46</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'E_IOB'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmVPArr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/VPArr</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB5_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC16</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmEr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/Er</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB5_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC17</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">49</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'nDTACK_IOB'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefCnt0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<0></a></td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('VCC')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC18</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
</table></span></div>
|
||||
<div id="tipBox"></div>
|
||||
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
|
||||
<li>A_FSB<20></li>
|
||||
<li>A_FSB<21></li>
|
||||
<li>A_FSB<22></li>
|
||||
<li>A_FSB<23></li>
|
||||
<li>E_IOB</li>
|
||||
<li><a href="Javascript:showEqn('csnOverlay1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cs/nOverlay1</a></li>
|
||||
<li>nVPA_IOB</li>
|
||||
</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
|
||||
<input type="button" onclick="javascript:showFB('FB4')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
|
||||
|
||||
<input type="button" onclick="javascript:showFB('FB6')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
|
||||
</td></tr></table></td>
|
||||
<td align="right">
|
||||
<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
|
||||
</td>
|
||||
</tr></table></span></form>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,265 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
|
||||
<td width="33%" valign="center" align="left"></td>
|
||||
<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
|
||||
<option value="FB2">FB2</option>
|
||||
<option value="FB3">FB3</option>
|
||||
<option value="FB4">FB4</option>
|
||||
<option value="FB5">FB5</option>
|
||||
<option value="FB6" selected>FB6</option>
|
||||
<option value="FB7">FB7</option>
|
||||
<option value="FB8">FB8</option></select></form></td>
|
||||
<td width="33%" valign="center" align="right"></td>
|
||||
</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th width="10%">Signal Name</th>
|
||||
<th width="10%">Total Product Terms</th>
|
||||
<th width="30%">Product Terms</th>
|
||||
<th width="10%">Location</th>
|
||||
<th width="10%">Power Mode</th>
|
||||
<th width="10%">Pin Number</th>
|
||||
<th width="10%">PinType</th>
|
||||
<th width="10%">Pin Use</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramBACTr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/BACTr</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC1</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<3></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB6_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC2</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">74</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsIOACTr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOACTr</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC3</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('fsbASrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/ASrf</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC4</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefCnt3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<3></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC5</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">76</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<23>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<4></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_6_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_1</a> <a href="Javascript:showPT('FB6_6_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC6</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">77</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefCnt2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<2></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_7_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC7</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefCnt1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<1></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC8</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">78</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<3>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nCAS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nCAS</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC9</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">79</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RefAck')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RefAck</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC10</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ALE0S')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ALE0S</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC11</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">80</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<21>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nOE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nOE</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC12</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">81</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsIOU1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOU1</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB6_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC13</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobsIOL1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOL1</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB6_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC14</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">82</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<19>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nROMWE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nROMWE</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC15</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">85</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('IOU0')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOU0</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB6_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB6_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC16</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nVPA_FSB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nVPA_FSB</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC17</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">86</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('IOL0')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOL0</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB6_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB6_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB6_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC18</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
</table></span></div>
|
||||
<div id="tipBox"></div>
|
||||
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
|
||||
<li>A_FSB<13></li>
|
||||
<li>A_FSB<14></li>
|
||||
<li>A_FSB<4></li>
|
||||
<li>A_FSB<5></li>
|
||||
<li><a href="Javascript:showEqn('IOACT')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOACT</a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<0></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<1></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<2></a></li>
|
||||
<li><a href="Javascript:showEqn('fsbASrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/ASrf</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbVPA_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/VPA</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsIOL1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOL1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsIOU1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/IOU1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsLoad1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/Load1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsPS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/PS_FSM_FFd1</a></li>
|
||||
<li><a href="Javascript:showEqn('iobsPS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobs/PS_FSM_FFd2</a></li>
|
||||
<li><a href="Javascript:showEqn('nADoutLE1')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nADoutLE1</a></li>
|
||||
<li>nAS_FSB</li>
|
||||
<li>nLDS_FSB</li>
|
||||
<li>nUDS_FSB</li>
|
||||
<li>nWE_FSB</li>
|
||||
<li><a href="Javascript:showEqn('ramRASEL_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RASEL</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd1</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd2</a></li>
|
||||
</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
|
||||
<input type="button" onclick="javascript:showFB('FB5')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
|
||||
|
||||
<input type="button" onclick="javascript:showFB('FB7')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
|
||||
</td></tr></table></td>
|
||||
<td align="right">
|
||||
<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
|
||||
</td>
|
||||
</tr></table></span></form>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
|
||||
<td width="33%" valign="center" align="left"></td>
|
||||
<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
|
||||
<option value="FB2">FB2</option>
|
||||
<option value="FB3">FB3</option>
|
||||
<option value="FB4">FB4</option>
|
||||
<option value="FB5">FB5</option>
|
||||
<option value="FB6">FB6</option>
|
||||
<option value="FB7" selected>FB7</option>
|
||||
<option value="FB8">FB8</option></select></form></td>
|
||||
<td width="33%" valign="center" align="right"></td>
|
||||
</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th width="10%">Signal Name</th>
|
||||
<th width="10%">Total Product Terms</th>
|
||||
<th width="30%">Product Terms</th>
|
||||
<th width="10%">Location</th>
|
||||
<th width="10%">Power Mode</th>
|
||||
<th width="10%">Pin Number</th>
|
||||
<th width="10%">PinType</th>
|
||||
<th width="10%">Pin Use</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmVPArf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/VPArf</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC1</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<7></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB7_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC2</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">50</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmRESrr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/RESrr</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC3</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmRESrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/RESrf</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC4</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmIOREQr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOREQr</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC5</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">52</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<8>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA8_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<8></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_6_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_1</a> <a href="Javascript:showPT('FB7_6_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC6</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">53</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmEr2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/Er2</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_7_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC7</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmDTACKrr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/DTACKrr</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC8</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">54</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<4>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA9_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<9></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a> <a href="Javascript:showPT('FB7_9_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC9</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">55</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmDTACKrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/DTACKrf</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC10</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmES3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<3></a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a> <a href="Javascript:showPT('FB7_11_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_2</a> <a href="Javascript:showPT('FB7_11_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC11</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">56</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'nBERR_IOB'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA11_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<11></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC12</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">58</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmES1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<1></a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB7_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a> <a href="Javascript:showPT('FB7_13_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC13</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmES0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<0></a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB7_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a> <a href="Javascript:showPT('FB7_14_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC14</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">59</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<9>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nADoutLE0')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nADoutLE0</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC15</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">60</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmES4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<4></a></td>
|
||||
<td align="center" width="10%">4</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB7_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB7_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB7_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC16</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nDinLE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nDinLE</a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC17</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">61</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('iobmES2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<2></a></td>
|
||||
<td align="center" width="10%">5</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB7_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a> <a href="Javascript:showPT('FB7_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB7_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB7_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB7_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC18</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
</table></span></div>
|
||||
<div id="tipBox"></div>
|
||||
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
|
||||
<li><a href="Javascript:showEqn('ALE0M')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ALE0M</a></li>
|
||||
<li><a href="Javascript:showEqn('ALE0S')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ALE0S</a></li>
|
||||
<li>A_FSB<17></li>
|
||||
<li>A_FSB<18></li>
|
||||
<li>A_FSB<19></li>
|
||||
<li>A_FSB<20></li>
|
||||
<li>A_FSB<8></li>
|
||||
<li>A_FSB<9></li>
|
||||
<li><a href="Javascript:showEqn('IOREQ')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">IOREQ</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<0></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<1></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<2></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<3></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmES4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/ES<4></a></li>
|
||||
<li><a href="Javascript:showEqn('iobmEr_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/Er</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmEr2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/Er2</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd3</a></li>
|
||||
<li><a href="Javascript:showEqn('iobmIOS_FSM_FFd4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">iobm/IOS_FSM_FFd4</a></li>
|
||||
<li>nDTACK_IOB</li>
|
||||
<li>nRES</li>
|
||||
<li>nVPA_IOB</li>
|
||||
<li><a href="Javascript:showEqn('ramRASEL_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RASEL</a></li>
|
||||
</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center">
|
||||
<input type="button" onclick="javascript:showFB('FB6')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev">
|
||||
|
||||
<input type="button" onclick="javascript:showFB('FB8')" onmouseover="window.status='show next Function Block'; return true;" onmouseout="window.status=''" value="next">
|
||||
</td></tr></table></td>
|
||||
<td align="right">
|
||||
<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
|
||||
</td>
|
||||
</tr></table></span></form>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,274 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="tooltips.js"></script><script src="fbs.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<body class="pgBgnd" id="XC95144XL">
|
||||
<span id="fbsel" class="pgRef"><table cellspacing="0" cellpadding="0" border="0" width="90%" align="center"><tr>
|
||||
<td width="33%" valign="center" align="left"></td>
|
||||
<td width="33%" valign="center" align="center"><form name="fbopt"><select onchange="javascript:showFB(document.fbopt.fbType.options[document.fbopt.fbType.options.selectedIndex].value)" name="fbType"><option value="FB1">FB1</option>
|
||||
<option value="FB2">FB2</option>
|
||||
<option value="FB3">FB3</option>
|
||||
<option value="FB4">FB4</option>
|
||||
<option value="FB5">FB5</option>
|
||||
<option value="FB6">FB6</option>
|
||||
<option value="FB7">FB7</option>
|
||||
<option value="FB8" selected>FB8</option></select></form></td>
|
||||
<td width="33%" valign="center" align="right"></td>
|
||||
</tr></table></span><div><span id="fbdata" class="pgRef"><table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
|
||||
<tr class="pgHeader">
|
||||
<th width="10%">Signal Name</th>
|
||||
<th width="10%">Total Product Terms</th>
|
||||
<th width="30%">Product Terms</th>
|
||||
<th width="10%">Location</th>
|
||||
<th width="10%">Power Mode</th>
|
||||
<th width="10%">Pin Number</th>
|
||||
<th width="10%">PinType</th>
|
||||
<th width="10%">Pin Use</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('fsbVPA_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/VPA</a></td>
|
||||
<td align="center" width="10%">14</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_18_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_2</a> <a href="Javascript:showPT('FB8_18_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_3</a> <a href="Javascript:showPT('FB8_18_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_4</a> <a href="Javascript:showPT('FB8_18_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_5</a> <a href="Javascript:showPT('FB8_1_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_1</a> <a href="Javascript:showPT('FB8_1_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_2</a> <a href="Javascript:showPT('FB8_1_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_3</a> <a href="Javascript:showPT('FB8_1_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_4</a> <a href="Javascript:showPT('FB8_1_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">1_5</a> <a href="Javascript:showPT('FB8_2_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_1</a> <a href="Javascript:showPT('FB8_2_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_2</a> <a href="Javascript:showPT('FB8_2_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_3</a> <a href="Javascript:showPT('FB8_2_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_4</a> <a href="Javascript:showPT('FB8_2_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">2_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC1</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nBERR_FSB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nBERR_FSB</a></td>
|
||||
<td align="center" width="10%">4</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_3_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_2</a> <a href="Javascript:showPT('FB8_3_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_3</a> <a href="Javascript:showPT('FB8_3_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_4</a> <a href="Javascript:showPT('FB8_3_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC2</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">63</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefCnt6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<6></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_3_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">3_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC3</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefCnt5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<5></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_4_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">4_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC4</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefCnt4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<4></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_5_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">5_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC5</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">64</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<12>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<2></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_6_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_1</a> <a href="Javascript:showPT('FB8_6_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">6_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC6</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">65</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('fsbBERR1r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/BERR1r</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_7_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_1</a> <a href="Javascript:showPT('FB8_7_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">7_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC7</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('csnOverlay1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cs/nOverlay1</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_8_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_1</a> <a href="Javascript:showPT('FB8_8_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">8_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC8</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">66</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'nWE_FSB'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<6></a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_9_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_1</a> <a href="Javascript:showPT('FB8_9_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">9_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC9</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">67</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('csnOverlay0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cs/nOverlay0</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_10_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_1</a> <a href="Javascript:showPT('FB8_10_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">10_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC10</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefDone_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefDone</a></td>
|
||||
<td align="center" width="10%">2</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_11_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_1</a> <a href="Javascript:showPT('FB8_11_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">11_2</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC11</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">68</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'A_FSB<10>'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('RA10_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RA<10></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_12_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">12_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC12</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">70</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('fsbReady0r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/Ready0r</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_13_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_1</a> <a href="Javascript:showPT('FB8_13_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_2</a> <a href="Javascript:showPT('FB8_13_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">13_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC13</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('TimeoutB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">TimeoutB</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_14_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_1</a> <a href="Javascript:showPT('FB8_14_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_2</a> <a href="Javascript:showPT('FB8_14_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">14_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC14</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">71</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'nLDS_FSB'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('nAoutOE')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">nAoutOE</a></td>
|
||||
<td align="center" width="10%">0</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('GND')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''"></a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC15</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">72</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%">O</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('ramRS_FSM_FFd3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd3</a></td>
|
||||
<td align="center" width="10%">11</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_15_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_1</a> <a href="Javascript:showPT('FB8_15_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_2</a> <a href="Javascript:showPT('FB8_15_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_3</a> <a href="Javascript:showPT('FB8_15_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">15_4</a> <a href="Javascript:showPT('FB8_16_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_1</a> <a href="Javascript:showPT('FB8_16_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_2</a> <a href="Javascript:showPT('FB8_16_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_3</a> <a href="Javascript:showPT('FB8_16_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_4</a> <a href="Javascript:showPT('FB8_16_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">16_5</a> <a href="Javascript:showPT('FB8_17_4')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_4</a> <a href="Javascript:showPT('FB8_17_5')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_5</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC16</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('TimeoutA')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">TimeoutA</a></td>
|
||||
<td align="center" width="10%">3</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_17_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_1</a> <a href="Javascript:showPT('FB8_17_2')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_2</a> <a href="Javascript:showPT('FB8_17_3')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">17_3</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC17</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%">73</td>
|
||||
<td width="8%" align="center">I/O</td>
|
||||
<td align="center" width="10%"><a href="#" onmouseover="this._tip = 'nAS_FSB'; window.status='Input Signal'; return true;" onmouseout="window.status=''" class="tipBoxCursor">I</a></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center" width="10%"><a href="Javascript:showEqn('cntRefCnt7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<7></a></td>
|
||||
<td align="center" width="10%">1</td>
|
||||
<td align="center" width="30%"> <a href="Javascript:showPT('FB8_18_1')" onmouseover="window.status='show Pterm'; return true;" onmouseout="window.status=''">18_1</a>
|
||||
</td>
|
||||
<td align="center" width="10%">MC18</td>
|
||||
<td align="center" width="10%">STD</td>
|
||||
<td align="center" width="10%"> </td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
<td align="center" width="10%">(b)</td>
|
||||
</tr>
|
||||
</table></span></div>
|
||||
<div id="tipBox"></div>
|
||||
<br><span id="fbsiguse" class="pgRef"><b>Signals Used By Logic in Function Block</b><br><ol>
|
||||
<li><a href="Javascript:showEqn('OpTxINV223_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">$OpTx$INV$223</a></li>
|
||||
<li>A_FSB<12></li>
|
||||
<li>A_FSB<16></li>
|
||||
<li>A_FSB<20></li>
|
||||
<li>A_FSB<21></li>
|
||||
<li>A_FSB<22></li>
|
||||
<li>A_FSB<23></li>
|
||||
<li>A_FSB<3></li>
|
||||
<li>A_FSB<7></li>
|
||||
<li><a href="Javascript:showEqn('BERR_IOBS')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">BERR_IOBS</a></li>
|
||||
<li><a href="Javascript:showEqn('RefAck')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">RefAck</a></li>
|
||||
<li><a href="Javascript:showEqn('TimeoutA')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">TimeoutA</a></li>
|
||||
<li><a href="Javascript:showEqn('TimeoutB')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">TimeoutB</a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<0></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<1></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<2></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<3></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt4_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<4></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt5_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<5></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt6_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<6></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefCnt7_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefCnt<7></a></li>
|
||||
<li><a href="Javascript:showEqn('cntRefDone_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cnt/RefDone</a></li>
|
||||
<li><a href="Javascript:showEqn('csnOverlay0_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cs/nOverlay0</a></li>
|
||||
<li><a href="Javascript:showEqn('csnOverlay1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">cs/nOverlay1</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbASrf_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/ASrf</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbBERR0r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/BERR0r</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbBERR1r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/BERR1r</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbReady0r_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/Ready0r</a></li>
|
||||
<li><a href="Javascript:showEqn('fsbVPA_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">fsb/VPA</a></li>
|
||||
<li>nAS_FSB</li>
|
||||
<li><a href="Javascript:showEqn('ramOnce_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/Once</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRAMReady_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RAMReady</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRASEL_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RASEL</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd1_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd1</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd2_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd2</a></li>
|
||||
<li><a href="Javascript:showEqn('ramRS_FSM_FFd3_SPECSIG')" onmouseover="window.status='show Equation'; return true;" onmouseout="window.status=''">ram/RS_FSM_FFd3</a></li>
|
||||
</ol></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="center"><table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td width="100%" align="center"><input type="button" onclick="javascript:showFB('FB7')" onmouseover="window.status='show previous Function Block'; return true;" onmouseout="window.status=''" value="prev"></td></tr></table></td>
|
||||
<td align="right">
|
||||
<input type="button" onclick="javascript:showLegend('logiclegend.htm')" onmouseover="window.status='show Legend'; return true;" onmouseout="window.status=''" value="legend"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page">
|
||||
</td>
|
||||
</tr></table></span></form>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<meta name="generator" content="RoboHELP by eHelp Corporation - www.ehelp.com">
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<meta name="filetype-version" content="1">
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<meta name="page-count" content="1">
|
||||
<meta name="layout-height" content="3556">
|
||||
<meta name="layout-width" content="670">
|
||||
<meta name="date" content="05 24, 2002 6:03:49 PM">
|
||||
<meta name="GENERATOR" content="Mozilla/4.79 [en]C-CCK-MCD (Windows NT 5.0; U) [Netscape]">
|
||||
<title>Function Block Specifics</title>
|
||||
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|
||||
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|
||||
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|
||||
<!--(Meta)==========================================================-->
|
||||
<style>
|
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|
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|
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|
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|
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|
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|
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||||
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|
||||
<body>
|
||||
|
||||
<h1>
|
||||
Function Block Specifics</h1>
|
||||
|
||||
<div class="whs1">To access specific details for a particular function
|
||||
block, click on that function block in either the <a href="maplogicdoc.htm">Mapped
|
||||
Logic</a>, <a href="mapinputdoc.htm">Mapped Inputs</a>, or <a href="fbsdoc.htm" style="font-family: arial, sans-serif; font-size: 10pt;">Function
|
||||
Blocks</a> sections of the fitter report. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->The
|
||||
function block details page displays a table of details about the particular
|
||||
function block you selected, a view button you can click to show a graphical
|
||||
display of the function block, and a pulldown menu you can use to select
|
||||
other function blocks to see.</div>
|
||||
|
||||
|
||||
<p class="whs2">The Table
|
||||
|
||||
<p class="whs3">The View
|
||||
<p><script LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='xml5.jpg' x-maintain-ratio='TRUE' width='648' height='397' border='0'>");}
|
||||
else
|
||||
{ document.write("<img src='xml5.jpg' x-maintain-ratio='TRUE' style='border: none; width: 648px; height: 397px; float: none;' width='648' height='397' border='0'>");}
|
||||
//--></script>
|
||||
|
||||
<h4 class="whs4">
|
||||
<a NAME="table"></a>The Table</h4>
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
table at the top of the function block details page provides the following
|
||||
information about the function block:</font></span>
|
||||
<ul type="disc" class="whs5">
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
signal name </font></span></li>
|
||||
</ul>
|
||||
|
||||
<div class="whs6"><span style="font-weight: bold;
|
||||
font-family: arial, sans-serif;
|
||||
font-size: 10pt;"><font size=-1><b>Note:</span><span
|
||||
style="font-family: arial, sans-serif; font-size: 10pt;"></b>
|
||||
Clicking on a signal name will open a new window with the equations for
|
||||
that signal. </font></span></div>
|
||||
|
||||
<ul type="disc" class="whs7">
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
total product terms used </font></span></li>
|
||||
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><!--kadov_tag{{<spaces>}}--><font size=-1> <!--kadov_tag{{</spaces>}}-->A
|
||||
list of product terms</font></span></li>
|
||||
</ul>
|
||||
|
||||
<div class="whs8"><span style="font-weight: bold;
|
||||
font-family: arial, sans-serif;
|
||||
font-size: 10pt;"><font size=-1><b>Note:</span><span
|
||||
style="font-family: arial, sans-serif; font-size: 10pt;"></b>
|
||||
Clicking on a <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->product
|
||||
term will open a new window with the equations for that term. </font></span></div>
|
||||
|
||||
<ul type="disc" class="whs9">
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
macrocell number in which the function block is located</font></span></li>
|
||||
</ul>
|
||||
|
||||
<div class="whs10"><span style="font-family: arial, sans-serif; font-size: 10pt;"><span
|
||||
style="font-weight: bold;"><font size=-1><b>Note:</span></b>
|
||||
Clicking on the underscored macrocell number will provide a graphical display
|
||||
of the macrocell that looks like this:</font></span></div>
|
||||
|
||||
|
||||
<p class="whs11"><script LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' width='540' height='420' border='0'>");}
|
||||
else
|
||||
{ document.write("<img src='macrocell.gif' x-maintain-ratio='TRUE' style='border: none; width: 540px; height: 420px; float: none;' width='540' height='420' border='0'>");}
|
||||
//--></script>
|
||||
.
|
||||
<ul type="disc" class="whs12">
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
power mode</font></span></li>
|
||||
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
pin number - an asterisk "*" indicates a user assignment</font></span></li>
|
||||
</ul>
|
||||
|
||||
<ul type="disc" class="whs13">
|
||||
<div class="whs14"><span style="font-family: arial, sans-serif; font-size: 10pt;"><span
|
||||
style="font-weight: bold;"><font size=-1><b>N</span></b>ote:</span><span style="font-family: arial, sans-serif; font-size: 10pt;">
|
||||
Clicking on the underscored pin number will provide the pin layout diagram
|
||||
for the highlighted pin. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Rolling
|
||||
your mouse over the colored pin will pop up a tooltip with the signal name
|
||||
assigned to the pin, the I/O standard, <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->the
|
||||
I/O style, the slew rate, and/or any constraints assigned to the pin:</font></span></div>
|
||||
</ul>
|
||||
|
||||
<div class="whs15"><script LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' width='309' height='312' border='0'>");}
|
||||
else
|
||||
{ document.write("<img src='pin.gif' x-maintain-ratio='TRUE' style='border: none; width: 309px; height: 312px; float: none;' width='309' height='312' border='0'>");}
|
||||
//--></script>
|
||||
</div>
|
||||
|
||||
<ul type="disc" class="whs16">
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
pin type</font></span></li>
|
||||
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>The
|
||||
pin use </font></span></li>
|
||||
|
||||
<li class="kadov-p" class="kadov-p">
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1><i>XPLA3
|
||||
only</i> - The GCK (Global Clock Signal) mapping </font></span></li>
|
||||
</ul>
|
||||
|
||||
<div class="whs17"><span style="font-weight: bold;
|
||||
font-family: arial, sans-serif;
|
||||
font-size: 10pt;"><font size=-1><b>Note:</span><span
|
||||
style="font-family: arial, sans-serif; font-size: 10pt;"></b>
|
||||
Moving your mouse cursor over an "I" in the Pin Use column will display
|
||||
that input signal as a tooltip.</font></span></div>
|
||||
|
||||
<br><span style="font-family: arial, sans-serif; font-size: 10pt;">
|
||||
<br><span style="font-family: arial, sans-serif; font-size: 10pt;"><i>XBR
|
||||
only</i> - Below the resource table there is another table listing the
|
||||
<b>Function Block Control Term</b> usage, the product term mapped to the
|
||||
control term is listed. Clicking on the product term will bring up a pop-up
|
||||
window displaying that product term.
|
||||
<blockquote>
|
||||
<li>
|
||||
CTC - control term clock</li>
|
||||
|
||||
<li>
|
||||
CTR - control term reset</li>
|
||||
|
||||
<li>
|
||||
CTS - control term set</li>
|
||||
|
||||
<li>
|
||||
CTE - control term output enable</li>
|
||||
</blockquote>
|
||||
|
||||
<p><br><span style="font-family: arial, sans-serif; font-size: 10pt;"><font size=-1>Below
|
||||
this table you will find a list of signals used by logic in the function
|
||||
block you are viewing. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->The
|
||||
list displays output signals as links. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Clicking
|
||||
on an output signal link will open a new window showing the equations for
|
||||
that signal.</font></span><!--begin!kadov{{-->
|
||||
<br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->
|
||||
|
||||
<p class="whs18"><span style="font-family: arial, sans-serif;
|
||||
font-size: 10pt;
|
||||
font-weight: bold;"><font size=-1><b>Note:</span><span
|
||||
style="font-family: arial, sans-serif; font-size: 10pt;"><!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}--></b>There
|
||||
is also a <script LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' width='68' height='28' border='0'>");}
|
||||
else
|
||||
{ document.write("<img src='legend.gif' x-maintain-ratio='TRUE' style='border: none; width: 68px; height: 28px; float: none;' width='68' height='28' border='0'>");}
|
||||
//--></script>
|
||||
button
|
||||
below the table. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Click
|
||||
this button to open a new window describing all of the acronyms used in
|
||||
the function block table. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->You
|
||||
can select either brief descriptions or more detailed descriptions by clicking
|
||||
the "Verbose" button at the top of the window.</font></span>
|
||||
<h4 class="whs19">
|
||||
<a NAME="view"></a>The View</h4>
|
||||
|
||||
<div class="whs20">When you click on the <script LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' width='61' height='53' border='0'>");}
|
||||
else
|
||||
{ document.write("<img src='view.gif' x-maintain-ratio='TRUE' style='border: none; width: 61px; height: 53px; float: none;' width='61' height='53' border='0'>");}
|
||||
//--></script>
|
||||
button
|
||||
above the table, a new window will open with a graphical display of the
|
||||
function block you are examining. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->The
|
||||
pins are all color-coded: input pins are green, output pins are blue, and
|
||||
clocks are magenta:</div>
|
||||
|
||||
|
||||
<p class="whs21"><script LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='fb1.gif' x-maintain-ratio='TRUE' width='482' height='378' border='0'>");}
|
||||
else
|
||||
{ document.write("<img src='fb1.gif' x-maintain-ratio='TRUE' style='border: none; width: 482px; height: 378px; float: none;' width='482' height='378' border='0'>");}
|
||||
//--></script>
|
||||
|
||||
|
||||
<p class="whs22">Right-click anywhere within the window to pull up a menu
|
||||
that allows you to zoom in or out for easier viewing. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->
|
||||
|
||||
<p class="whs23">This menu also allows you choose to see all of the input
|
||||
connections, all of the output connections, or both at once. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->Like
|
||||
the pins, the signals are color-coded: inputs are red, outputs are yellow,
|
||||
and macrocell connections are aqua:
|
||||
|
||||
<p class="whs24"><script LANGUAGE="JavaScript"><!--
|
||||
if (navigator.appName=="Netscape")
|
||||
{ document.write("<img src='fb.gif' x-maintain-ratio='TRUE' width='497' height='377' border='0'>");}
|
||||
else
|
||||
{ document.write("<img src='fb.gif' x-maintain-ratio='TRUE' style='border: none; width: 497px; height: 377px; float: none;' width='497' height='377' border='0'>");}
|
||||
//--></script>
|
||||
|
||||
|
||||
<p class="whs25">To examine the signals of single pins, simply click the
|
||||
pin whose signals you wish to see. <!--kadov_tag{{<spaces>}}--><!--kadov_tag{{</spaces>}}-->To
|
||||
examine multiple pins without having to see everything at once, hold down
|
||||
the control key while you click the pins you want to view.
|
||||
|
||||
<p class="whs26">To view the signals for individual macrocells:
|
||||
<ul type="disc" class="whs27">
|
||||
<div class="whs28">Click the inside edge of the macrocell to display its
|
||||
macrocell connections and inputs.</div>
|
||||
|
||||
|
||||
<p class="whs29">Click the outer edge to display its output signals
|
||||
|
||||
<p class="whs30">Click in the center to display everything
|
||||
|
||||
<p class="whs31">Double click in the center to open a new window with a
|
||||
detailed macrocell diagram</ul>
|
||||
|
||||
<div class="whs32"></div>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
|
||||
|
||||
<html>
|
||||
|
||||
<!--(==============================================================)-->
|
||||
<!--(Document created with RoboEditor. )============================-->
|
||||
<!--(==============================================================)-->
|
||||
|
||||
<head>
|
||||
|
||||
<title>Function Blocks</title>
|
||||
|
||||
<!--(Meta)==========================================================-->
|
||||
|
||||
<meta name=generator content="RoboHELP by eHelp Corporation - www.ehelp.com">
|
||||
<meta name=generator-major-version content=0.1>
|
||||
<meta name=generator-minor-version content=1>
|
||||
<meta name=filetype content=kadov>
|
||||
<meta name=filetype-version content=1>
|
||||
<meta name=page-count content=1>
|
||||
<meta name=layout-height content=405>
|
||||
<meta name=layout-width content=615>
|
||||
<meta name=date content="05 24, 2002 5:49:51 PM">
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
<!--
|
||||
ul.whs1 {list-style: disc;}
|
||||
|
||||
--></style><script language="javascript" title="WebHelpInlineScript">
|
||||
<!--
|
||||
function reDo() {
|
||||
if (innerWidth != origWidth || innerHeight != origHeight)
|
||||
location.reload();
|
||||
}
|
||||
if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
|
||||
origWidth = innerWidth;
|
||||
origHeight = innerHeight;
|
||||
onresize = reDo;
|
||||
}
|
||||
//-->
|
||||
</script><style>
|
||||
<!--
|
||||
div.WebHelpPopupMenu {position:absolute; left:0px; top:0px; z-index:4; visibility:hidden;}
|
||||
p.WebHelpNavBar {text-align:right;}
|
||||
-->
|
||||
</style>
|
||||
</head>
|
||||
|
||||
<!--(Body)==========================================================-->
|
||||
|
||||
|
||||
<body>
|
||||
|
||||
|
||||
<h1>Function Blocks</h1>
|
||||
|
||||
<span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The Function
|
||||
Blocks page provides a summary of all function blocks' resources. Clicking
|
||||
on one of the function blocks in the summary table will display the <a href="fbs_FBdoc.htm">specific details</a> for that function block. <!--kadov_tag{{<spaces>}}--> </FONT></span><!--kadov_tag{{</spaces>}}-->
|
||||
|
||||
<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}-->
|
||||
|
||||
|
||||
<!--begin!kadov{{--><br><!--}}end!kadov--><!--kadov_tag{{<implicit_p>}}--><span
|
||||
style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The summary table
|
||||
contains the following: <!--kadov_tag{{<spaces>}}--> </FONT></span><!--kadov_tag{{</spaces>}}-->
|
||||
|
||||
<ul type="disc" class="whs1">
|
||||
|
||||
<li class=kadov-p
|
||||
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
|
||||
function block</FONT></span></li>
|
||||
|
||||
<li class=kadov-p
|
||||
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
|
||||
number of macrocell used </FONT></span></li>
|
||||
|
||||
<li class=kadov-p
|
||||
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
|
||||
number of function block inputs used </FONT></span></li>
|
||||
|
||||
<li class=kadov-p
|
||||
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
|
||||
number of product terms used</FONT></span></li>
|
||||
|
||||
<li class=kadov-p
|
||||
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
|
||||
pins used</FONT></span></li>
|
||||
|
||||
<li class=kadov-p
|
||||
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
|
||||
local control terms used</FONT></span></li>
|
||||
|
||||
<li class=kadov-p
|
||||
class=kadov-p><span style="font-family: arial, sans-serif; font-size: 10pt;"><FONT SIZE=2 style="font-size:10pt;">The
|
||||
number of foldback NANDs used (CoolRunner only)</FONT></span></li>
|
||||
</ul>
|
||||
|
||||
</body>
|
||||
|
||||
</html>
|
||||
Binary file not shown.
|
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|
After Width: | Height: | Size: 22 KiB |
|
|
@ -0,0 +1,17 @@
|
|||
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<title>genmsg</title>
|
||||
</head>
|
||||
<body>
|
||||
|
||||
<br>
|
||||
<dl>
|
||||
<dd>
|
||||
This file is currently being generated. Please recheck the link after some
|
||||
time for this report data.</dd>
|
||||
</dl>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 7.7 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 940 B |
|
|
@ -0,0 +1,14 @@
|
|||
<html>
|
||||
<head>
|
||||
<title></title>
|
||||
</head>
|
||||
<frameset frameborder="NO" framespacing="0" border="0" rows="94,*,0,0" cols="*">
|
||||
<frame name="topnav" src="../tim/topnav.htm" scrolling="no" noresize marginwidth="0" marginheight="0">
|
||||
<frameset frameborder="NO" framespacing="0" border="0" cols="125,*">
|
||||
<frame name="leftnav" src="leftnav.htm" noresize marginwidth="0" marginheight="0">
|
||||
<frame name="content" src="summary.htm">
|
||||
</frameset>
|
||||
<frame name="eqns" src="eqns.htm" scrolling="no">
|
||||
</frameset>
|
||||
</html>
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<script src="maplogic.js"></script><link rel="stylesheet" type="text/css" href="style.css">
|
||||
</head>
|
||||
<span id="maplog" class="pgRef"><h3 align="center">Unmapped Inputs</h3>
|
||||
<table width="90%" border="1" cellpadding="0" cellspacing="0"><tr class="pgHeader">
|
||||
<th width="28%">Signal Name</th>
|
||||
<th align="center">User Assignment</th>
|
||||
</tr></table></span><form><span class="pgRef"><table width="90%" align="center"><tr>
|
||||
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||||
<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
|
||||
</tr></table></span></form>
|
||||
</html>
|
||||
|
|
@ -0,0 +1 @@
|
|||
function showInputLeft() { parent.leftnav.showInputLeft(); }
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue