Commit Graph

313 Commits

Author SHA1 Message Date
transistor
f9e018742b Refactored how UI interfacing will work 2021-10-21 21:55:27 -07:00
transistor
fab763a867 Added rough host window updating options for future reference 2021-10-21 20:59:26 -07:00
transistor
bff90e8f9f Updated cargo with workspaces 2021-10-20 19:54:13 -07:00
transistor
8d39d84545 Refactored to separate out the commands, and machine configs
Machine definitions are now in their own module and can be
optionally compiled in, and there is now a console and soon
to be gui version of the compiled binary, with individual
binaries for each machine
2021-10-20 15:53:25 -07:00
transistor
e81a5d430a Fixed some bugs and added the ROXd instruction 2021-10-19 19:50:42 -07:00
transistor
3579529764 Minor fixes and refactoring 2021-10-19 11:33:51 -07:00
transistor
492027fa7a Fixed a bug in bit field instruction decode
We were trying to decode the effective address before fetching the
second instruction word for bitfield instructions, which was causing
it to use the wrong word for the offset:width information, which was
preventing the shell from printing to the screen after boot
2021-10-18 21:41:42 -07:00
transistor
2d8e5f6359 Added support for long word MUL and DIV instructions 2021-10-18 21:22:57 -07:00
transistor
b88b0a890c Updated tests for new addressing modes 2021-10-18 16:34:55 -07:00
transistor
731c89845e Added MC68020+ addressing modes 2021-10-18 15:44:42 -07:00
transistor
3fc76335d0 Moved m68k instruction types to their own file 2021-10-18 12:05:10 -07:00
transistor
32d2d591ce Added bit field instructions, and fixed some bugs 2021-10-17 21:18:59 -07:00
transistor
758621c410 Fixed bug in indexing modes 2021-10-17 11:13:46 -07:00
transistor
1262cbd8c0 Modified to use a common trait to derive other traits 2021-10-17 10:39:43 -07:00
transistor
4bdbe7c7f0 Refactored a bit
Now all traits are in the devices file, and host adapters will be
in under src/host/.
2021-10-16 20:30:50 -07:00
transistor
93c9307829 Moved I/O to a separate thread
but I'm not happy with it, and will likely change it in future,
possibly to use two threads and two sets of channels to pass chars
back and forth
2021-10-16 16:11:50 -07:00
transistor
853626584e Once again modified how the memory addressing works 2021-10-16 10:58:27 -07:00
transistor
24e050a840 Added supervisor checks 2021-10-16 10:01:14 -07:00
transistor
ffd4faa9a3 Fixed decode of EXT, and fixed some bugs with 020+ code 2021-10-15 14:37:31 -07:00
transistor
1732c90f5b Added formatter for Instruction to output assembly 2021-10-15 11:12:47 -07:00
transistor
eba1f9c9fc Fixed bug with ANDtoSR, which was actually using "or" 2021-10-14 22:04:14 -07:00
transistor
72457aca5c Minor changes 2021-10-14 21:53:42 -07:00
transistor
43b1abfa19 Minor changes 2021-10-14 21:16:31 -07:00
transistor
e558fc01bf Refactored and fixed some warnings 2021-10-11 15:16:04 -07:00
transistor
91825e1cb9 Added a bunch of unit tests 2021-10-11 15:04:39 -07:00
transistor
39ecd1b0d9 Added decode for ABCD and SBCD 2021-10-10 20:47:51 -07:00
transistor
94141e112e Reorganized decode and add some support for other m68k processors 2021-10-10 14:26:54 -07:00
transistor
b588563acc Updated readme 2021-10-09 20:35:52 -07:00
transistor
fbb5153121 Refactored mc68681 to make a common port struct and fixed a bug in DIV 2021-10-09 17:35:23 -07:00
transistor
f0637e81f1 Added separate interrupt controller 2021-10-09 11:00:32 -07:00
transistor
c4f41d73ab Put the types and traits from system into new devices file 2021-10-08 23:11:52 -07:00
transistor
8bb43f61ee Fixed interrupts and added tx enable for OS buffered output 2021-10-08 10:52:15 -07:00
transistor
ecbaf6a68b Added interrupt triggering from mc68681 2021-10-07 13:57:50 -07:00
transistor
7bd7f3e64f Added cpu to system, and refactored m68k a bit 2021-10-07 11:35:15 -07:00
transistor
73d11ddb79 Switched to using Rc<RefCell<Box<dyn Trait>>> for devices 2021-10-07 09:41:01 -07:00
transistor
e186637f49 Refactored such that System is the top level object 2021-10-06 16:14:56 -07:00
transistor
5ea2ccc128 Added TRAP instruction and exception handling 2021-10-05 21:53:18 -07:00
transistor
59019d9c8e Refactored address space again 2021-10-05 19:58:22 -07:00
transistor
f2a23a21cb Added ROd instruction and fixed bug with MOVEM 2021-10-05 16:22:21 -07:00
transistor
f5283730c2 Added start of ata device 2021-10-04 13:02:58 -07:00
transistor
e561c533ef Added stack tracer and fixed bug with CMPA instruction 2021-10-04 11:13:10 -07:00
transistor
2f54c18fcf Modified memory operations to be simpler 2021-10-03 21:05:10 -07:00
transistor
dd21771bb3 Added better processing of debug commands, and timers 2021-10-03 20:45:50 -07:00
transistor
bc7fee5221 Updated readme 2021-10-03 10:00:58 -07:00
transistor
338e68a1d9 Fixed some erroneous instruction decodes and added binaries 2021-10-03 09:55:20 -07:00
transistor
10e905674b Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags
With ADDA, SUBA, and ADDQ/SUBQ when the target is an address register, the condition
flags should not be changed, but the code was changing them, which caused problems.
I've fixed it by making the ADD/SUB executions check for an address target and
will not update flags in that case.  This should only occur when the actual instruction
was an ADDA or ADDQ with an address register target
2021-10-02 21:59:28 -07:00
transistor
98883e3daa Added the Asd, LINK, and UNLK instructions 2021-10-02 15:35:08 -07:00
transistor
80c8fe9797 Fixed bug with PC offsets and the value of PC when calculated 2021-10-02 09:48:21 -07:00
transistor
4b577ad403 Separated debugging code into its own file 2021-10-02 09:35:25 -07:00
transistor
38bcf0af3f Reorganized state and decoding into their own structs 2021-10-02 08:47:20 -07:00