Commit Graph

68 Commits

Author SHA1 Message Date
transistor
b165e18fac Added ADDX/SUBX instructions to m68k 2021-12-01 15:40:41 -08:00
transistor
0f2f989775 Fixed bug in m68k with Extend flag in shift instructions 2021-12-01 10:45:24 -08:00
transistor
03f23da544 Added A and F instructions to m68k 2021-11-23 11:45:11 -08:00
transistor
f601290771 Fixed bug in MOVEM and added tests for it
It was previously decrementing addresses if the direction was from
registers to memory, but that's incorrect.  It should increment the
address always when using an addressing mode other than the ARecDec
mode.  I also added a memory location to the test cases to test the
MOVEM instruction by comparing what memory was read/written (but it's
only one u32 because that's the minimum we need)
2021-11-19 09:55:31 -08:00
transistor
02b10c5b32 Changed msp to ssp to match docs 2021-11-18 12:13:36 -08:00
transistor
a342ef3b86 Added MOVEP and more tests to m68k and IM to z80 2021-11-15 20:52:19 -08:00
transistor
a00d7b2f26 Fixed warnings 2021-11-13 11:39:20 -08:00
transistor
e0d863a845 Fixed overflow bug in m68k 2021-11-13 10:54:59 -08:00
transistor
7d2a4e4b44 Fixed m68k overflow flags (almost) 2021-11-04 21:29:52 -07:00
transistor
8ba506cc11 Added tracing mode to debugger 2021-11-04 13:32:51 -07:00
transistor
2cb21d7b8d Fixed a number of instruction bugs with m68k 2021-11-03 23:55:50 -07:00
transistor
bd5a798fa1 Fixed bug in ADDA/SUBA instructions 2021-11-03 15:30:38 -07:00
transistor
58fc9ac827 Moved the debugger out of m68k 2021-11-01 16:51:45 -07:00
transistor
93c080eae6 Fixed interrupts
Previously the m68k wasn't masking interrupts with an equal priorty.
I also modified how they work, such that the cpus will check the
controller rather than wait for the notification call
2021-10-29 22:02:29 -07:00
transistor
c1ca666aa4 Simplified event queue 2021-10-29 20:06:15 -07:00
transistor
250c0e83d2 Minor fixes 2021-10-29 15:05:41 -07:00
transistor
892f93f053 Added BusPort to more accurately emulate the bus requests of the 68k
The BusPort is created before the CPU and is passed to it.  It can
have an offset, limit the address sizes, and break up bus request
beyond a certain number of bytes into multiple requests
2021-10-26 21:32:25 -07:00
transistor
1ad7ad1807 Added Debuggable trait and added tests 2021-10-26 12:17:59 -07:00
transistor
0b17b0fc8c Modified timer to store its own start time 2021-10-25 19:29:39 -07:00
transistor
089f25903b Added adjustable frequency to m68k, and added log levels 2021-10-25 10:29:13 -07:00
transistor
fd894f0638 Modified to use a nanosecond clock 2021-10-23 22:22:02 -07:00
transistor
e81a5d430a Fixed some bugs and added the ROXd instruction 2021-10-19 19:50:42 -07:00
transistor
3579529764 Minor fixes and refactoring 2021-10-19 11:33:51 -07:00
transistor
2d8e5f6359 Added support for long word MUL and DIV instructions 2021-10-18 21:22:57 -07:00
transistor
b88b0a890c Updated tests for new addressing modes 2021-10-18 16:34:55 -07:00
transistor
731c89845e Added MC68020+ addressing modes 2021-10-18 15:44:42 -07:00
transistor
3fc76335d0 Moved m68k instruction types to their own file 2021-10-18 12:05:10 -07:00
transistor
32d2d591ce Added bit field instructions, and fixed some bugs 2021-10-17 21:18:59 -07:00
transistor
758621c410 Fixed bug in indexing modes 2021-10-17 11:13:46 -07:00
transistor
1262cbd8c0 Modified to use a common trait to derive other traits 2021-10-17 10:39:43 -07:00
transistor
4bdbe7c7f0 Refactored a bit
Now all traits are in the devices file, and host adapters will be
in under src/host/.
2021-10-16 20:30:50 -07:00
transistor
24e050a840 Added supervisor checks 2021-10-16 10:01:14 -07:00
transistor
ffd4faa9a3 Fixed decode of EXT, and fixed some bugs with 020+ code 2021-10-15 14:37:31 -07:00
transistor
eba1f9c9fc Fixed bug with ANDtoSR, which was actually using "or" 2021-10-14 22:04:14 -07:00
transistor
72457aca5c Minor changes 2021-10-14 21:53:42 -07:00
transistor
e558fc01bf Refactored and fixed some warnings 2021-10-11 15:16:04 -07:00
transistor
94141e112e Reorganized decode and add some support for other m68k processors 2021-10-10 14:26:54 -07:00
transistor
fbb5153121 Refactored mc68681 to make a common port struct and fixed a bug in DIV 2021-10-09 17:35:23 -07:00
transistor
f0637e81f1 Added separate interrupt controller 2021-10-09 11:00:32 -07:00
transistor
c4f41d73ab Put the types and traits from system into new devices file 2021-10-08 23:11:52 -07:00
transistor
8bb43f61ee Fixed interrupts and added tx enable for OS buffered output 2021-10-08 10:52:15 -07:00
transistor
ecbaf6a68b Added interrupt triggering from mc68681 2021-10-07 13:57:50 -07:00
transistor
7bd7f3e64f Added cpu to system, and refactored m68k a bit 2021-10-07 11:35:15 -07:00
transistor
73d11ddb79 Switched to using Rc<RefCell<Box<dyn Trait>>> for devices 2021-10-07 09:41:01 -07:00
transistor
e186637f49 Refactored such that System is the top level object 2021-10-06 16:14:56 -07:00
transistor
5ea2ccc128 Added TRAP instruction and exception handling 2021-10-05 21:53:18 -07:00
transistor
59019d9c8e Refactored address space again 2021-10-05 19:58:22 -07:00
transistor
f2a23a21cb Added ROd instruction and fixed bug with MOVEM 2021-10-05 16:22:21 -07:00
transistor
f5283730c2 Added start of ata device 2021-10-04 13:02:58 -07:00
transistor
e561c533ef Added stack tracer and fixed bug with CMPA instruction 2021-10-04 11:13:10 -07:00