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a3517bf054
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Author SHA1 Message Date
Zane Kaminski
a3517bf054 Revert "Updated slew rate/current strength assignments" 
This reverts commit 691c076b4d.
 2021-04-20 05:50:09 -04:00
Zane Kaminski
691c076b4d Updated slew rate/current strength assignments 2021-04-20 05:43:37 -04:00
Zane Kaminski
fc376ce5d8 Latch config DIP switches at boot 
Also rearranged GR8RAM.v
 2021-04-20 04:23:57 -04:00
Zane Kaminski
0ca3f17cd5 Works better? 2021-04-20 04:10:26 -04:00
Zane Kaminski
d88ccfb802 Documentation update 2021-04-20 01:49:44 -04:00
Zane Kaminski
c0e7733ba1 Add "ZK, GF" to board 2021-04-20 01:47:09 -04:00
Zane Kaminski
72d2609e63 Fabbed 2021-04-19 05:43:21 -04:00
Zane Kaminski
dc38e1f668 Sorta works 2021-04-19 02:57:51 -04:00
Zane Kaminski
6bcd3a0740 Added CKE back 2021-04-18 20:24:58 -04:00
Zane Kaminski
b899bfc4ad Sorta works 2021-04-18 06:01:08 -04:00
Zane Kaminski
6eb7960003 Remove CKE 2021-04-18 03:59:56 -04:00
Zane Kaminski
bc9fb27129 Make apple boot 
Apple boots but SDRAM not working. Register R/W/increment works
 2021-04-18 03:54:45 -04:00
Zane Kaminski
6e2e916561 Create FrontIsom.png 2021-04-12 04:27:58 -04:00
Zane Kaminski
b46fe84724 Update RAM Map 2021-04-12 03:46:33 -04:00
Zane Kaminski
c4844b9646 idk 2021-04-11 15:39:19 -04:00
Zane Kaminski
b0b8b0dc6c Works? 2021-04-03 03:44:42 -04:00
Zane Kaminski
9eec9bf7b9 ugh 2021-03-19 16:38:48 -04:00
Zane Kaminski
116abb1a6f before remove UFM 2021-03-19 14:23:33 -04:00
Zane Kaminski
52b3716342 hmm 2021-03-19 06:59:22 -04:00
Zane Kaminski
9ac2ba97ae better 2021-03-19 06:45:31 -04:00
Zane Kaminski
3816ecd0a1 ugh 2021-03-19 02:56:20 -04:00
Zane Kaminski
a444cc31aa idk 2021-03-15 13:40:59 -04:00
Zane Kaminski
e5da11855d Remove old CPLD stuff 2021-03-15 13:40:41 -04:00
Zane Kaminski
db594211fa Fabbed 2021-02-17 19:29:24 -05:00
Zane Kaminski
9f0867fe56 reset button detect 2020-10-25 05:22:14 -04:00
Zane Kaminski
7d6776e480 Board done? 2020-10-07 23:32:57 -04:00
Zane Kaminski
3091ea4d32 Sketch of verilog 2020-10-07 23:32:29 -04:00
Zane Kaminski
4beed0e635 Added label images 2020-05-30 04:50:23 -04:00
Zane Kaminski
817cbd25fd Update .gitignore 2020-05-15 22:51:14 -04:00
Zane Kaminski
9e108f656c Update .gitignore 2020-05-15 18:49:20 -04:00
Zane Kaminski
66c0973cdf Many changes 2020-03-10 18:54:44 -04:00
Zane Kaminski
7e41906335 Put FullIOEN back 2020-02-26 03:37:20 -05:00
Zane Kaminski
209afbc5c5 Added transfer counters 2020-02-26 03:34:33 -05:00
Zane Kaminski
6a33e1adb0 Added separate configuration section 2020-02-26 03:31:20 -05:00
Zane Kaminski
156aa66473 Cleanup 2020-02-26 03:15:36 -05:00
Zane Kaminski
593f5cb010 Removed inhibit output 2020-02-26 03:14:33 -05:00
Zane Kaminski
76bceb089d Moved REGEN and IOROMEN (no functional change) 2020-02-26 03:14:13 -05:00
Zane Kaminski
4575818d63 Removed SetWR and FullIOEN 2020-02-26 02:13:35 -05:00
Zane Kaminski
d9e9038a4d Comments, no actual changes to CPLD verilog 2020-02-16 22:03:57 -05:00
Zane Kaminski
b29662bcab Fixed previous problem, working again 2020-02-16 00:11:12 -05:00
Zane Kaminski
79789a9e8b Doesn't work but committing for posterity 2020-02-15 23:15:54 -05:00
Zane Kaminski
911557e38b Removed AVR-JTAG-10 connector footprint 2020-02-09 03:40:57 -05:00
Zane Kaminski
90875fd58f Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev 2020-01-26 15:15:07 -05:00
Zane Kaminski
c02ffbbe6a Separated CSDBEN 2020-01-26 15:13:37 -05:00
Zane Kaminski
2bc381ebc5 Removed state counter reset 2019-12-21 01:46:05 -05:00
Zane Kaminski
6e135d4305 Fixed bugs in new PLD stuff 2019-10-20 22:41:24 -04:00
Zane Kaminski
f471e04244 New PLD revision 
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
 2019-10-18 15:07:38 -04:00
Zane Kaminski
a8eb7940fe Recompiled just to be sure 2019-10-13 21:18:41 -04:00
Zane Kaminski
d80b9dc727 Switch library location, fixed datasheet fields 2019-10-13 02:04:29 -04:00
Zane Kaminski
3de72a352c Update GR8RAM-render.png 2019-10-13 02:04:13 -04:00