Thomas Harte
9a2f32795f
Revokes stack-local storage non-optimisation.
2020-10-15 21:03:10 -04:00
Thomas Harte
28da1a724a
Introduces Jeek816 test case.
2020-10-12 21:43:44 -04:00
Thomas Harte
5dc3cd3a2f
Starts using Jeek816 for a basic native-mode audit. Fixes absolute long addressing.
2020-10-11 22:02:46 -04:00
Thomas Harte
3039a445f0
Ups the 65816 test machine to a full 16mb RAM.
2020-10-11 21:18:01 -04:00
Thomas Harte
6892ac13e8
Corrects BIT. All 65816-applicable Wolfgang Lorenz tests now pass.
2020-10-10 17:47:33 -04:00
Thomas Harte
7966592fae
Corrects ROL d.
2020-10-10 11:22:23 -04:00
Thomas Harte
c01bc784b9
Slightly reduces branching.
2020-10-09 22:21:55 -04:00
Thomas Harte
451f83ba51
Corrects emulation-mode read-modify-writes not to empty the data buffer.
2020-10-09 22:14:42 -04:00
Thomas Harte
b439f40fe2
Corrects INC and DEC.
2020-10-09 22:04:25 -04:00
Thomas Harte
7dde7cc743
Implements altered direct indexed addressing in emulation mode.
2020-10-08 22:02:14 -04:00
Thomas Harte
0418f51ef2
Takes a shot at emulation-mode 'exceptions'.
...
It's just RTI and correct decimal SBC left of the official 6502s now, I think.
2020-10-08 17:52:13 -04:00
Thomas Harte
19aea85184
Corrects CMP, CPX, CPY carry flags.
2020-10-07 21:23:29 -04:00
Thomas Harte
f7b119ffe1
Moves temporary logging, fixes branch instructions.
2020-10-07 19:57:58 -04:00
Thomas Harte
18e8d6ce06
Makes an effort to factor out the 6502's [lazy] flags.
...
This is preparatory to deciding which instructions, if any, are worth factoring out.
2020-10-05 22:23:33 -04:00
Thomas Harte
ef1a514785
Introduces 6502Selector, for picking either a 6502 or a 65816 based on a single template parameter.
2020-09-28 21:35:46 -04:00
Thomas Harte
6635876e7e
Performs a bare factoring out of the 6502 bus handler.
2020-09-28 18:43:53 -04:00
Thomas Harte
ad8a2e2cb9
Corrects a long-standing naming obscurity.
2020-09-27 22:19:42 -04:00
Thomas Harte
91229a1dbd
Adds overt fallthrough attributes.
2020-06-19 23:22:29 -04:00
Thomas Harte
73131735fa
Further qmake warning corrections.
2020-05-30 19:31:17 -04:00
Thomas Harte
267006782f
Starts to add Qt target; resolves many build warnings.
2020-05-30 00:37:06 -04:00
Thomas Harte
8b76d4007e
Starts adding State for the 68000.
2020-05-14 22:46:40 -04:00
Thomas Harte
7c9d9ee048
Adds basic Z80 state.
2020-05-13 20:15:22 -04:00
Thomas Harte
25996ce180
Further doubles down on construction syntax for type conversions.
2020-05-09 23:00:39 -04:00
Thomas Harte
cc357a6afa
Removes boilerplate from header.
2020-04-02 19:15:57 -04:00
Thomas Harte
dfc1c7d358
Separates 6502 State object to make it optional.
...
Also makes a few minor const improvements while I'm poking around.
2020-04-02 19:11:27 -04:00
Thomas Harte
7ed8e33622
Eliminates unused 6502 counter.
2020-04-02 18:49:28 -04:00
Thomas Harte
a491650c8b
Adds safety asserts.
2020-03-30 21:39:31 -04:00
Thomas Harte
95c68c76e1
Corrects use of StructImpl.
2020-03-30 00:27:40 -04:00
Thomas Harte
edc553fa1d
Removes duplicative 'register'.
2020-03-29 22:58:00 -04:00
Thomas Harte
4f2ebad8e0
Takes a shot a set_state.
2020-03-29 22:50:30 -04:00
Thomas Harte
cfb75b58ca
Pulls all 6502 MicroOp sequences into the main operations_ table.
...
This will make state restoration somewhat more tractable.
2020-03-29 18:36:41 -04:00
Thomas Harte
4fbe983527
Provisionally adds State and get_state to the 6502.
...
`set_state` may be a little more complicated, requiring a way to advance in single-cycle steps **without applying bus accesses**.
2020-03-28 00:33:27 -04:00
Thomas Harte
a51fe70498
Standardises cast syntax.
2020-03-06 21:55:00 -05:00
Thomas Harte
b971e2a42c
Adds get_is_resetting to the Z80, eliminating the CPC's custom version.
2020-02-29 19:58:25 -05:00
Thomas Harte
4aeb9a7c56
Genericises RegisterPair.
2019-03-09 21:16:11 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
364859467f
Corrects Rockwell and WDC references.
...
Also shuffles the NES CPU type up into the top position, so this is a strict progression in terms of functionality.
2018-09-27 22:36:45 -04:00
Thomas Harte
8787d85e64
Eliminates #undefs as being (i) unnecessary, now this is a source file; and (ii) incomplete in any case.
2018-08-17 22:24:42 -04:00
Thomas Harte
0e7f54f375
Implements STP and WAI, and ensures all unimplemented 65C02 instructions are NOP for all 65C02s.
2018-08-17 21:49:06 -04:00
Thomas Harte
b3bdfa9f46
Corrected: it's three-cycle 65C02 branches that ignore interrupts, not two.
2018-08-16 20:47:49 -04:00
Thomas Harte
592ec69d36
Causes the 65C02 not to accept interrupts immediately after untaken branches.
2018-08-15 22:42:04 -04:00
Thomas Harte
60e00ddd02
Correction: the test for not skipping an operand fetch requires a 65C02.
2018-08-15 22:07:17 -04:00
Thomas Harte
6806193dc2
Ensures that "Read/Modify/Write instructions absolute indexed in same page" take only six cycles on a 65C02.
2018-08-15 19:17:37 -04:00
Thomas Harte
c35dca783f
Ensures that page-crossing indexing no longer causes an extra read of an invalid address on the 65C02.
...
It rereads the last byte of the instruction stream instead.
2018-08-15 18:47:53 -04:00
Thomas Harte
901e0d65b9
Documents all 6502 micro-operations.
...
Also makes sure 1-cycle NOPs really, definitely are one cycle only on a 65C02 and eliminates OperationCopyOperandFromA as a redundant copy of OperationSTA.
2018-08-14 22:17:53 -04:00
Thomas Harte
ddf45a0010
Ensures NMI and RST reset D on 65C02s.
2018-08-14 19:49:14 -04:00
Thomas Harte
1eca4463b3
Ensures NMI can no longer usurp BRK on 65C02s.
2018-08-14 19:33:48 -04:00
Thomas Harte
be01203cc1
Starts to expand the range of supported 6502s.
...
This fully implements the NES 6502 because, well, it's virtually no extra work, and ensures that RDY takes effect on write cycles on 65C02s.
2018-08-13 22:17:22 -04:00
Thomas Harte
4b91910fab
Removes erroneous addition.
2018-08-10 23:27:09 -04:00
Thomas Harte
878c63dcd2
Ensures ADC and SBC decimal take an extra cycle on the 65C02.
2018-08-10 22:52:55 -04:00
Thomas Harte
261fb3d4f8
Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
...
This gets Klaus Dorman's test to pass.
2018-08-10 22:42:35 -04:00
Thomas Harte
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
Thomas Harte
8b50ab2593
Corrects (zero) behaviour.
2018-08-10 21:12:55 -04:00
Thomas Harte
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
Thomas Harte
6f838fe190
Implements INA and DEA.
2018-08-08 22:30:19 -04:00
Thomas Harte
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
Thomas Harte
e46bde35f5
Implements BBS and BBR.
2018-08-07 21:52:17 -04:00
Thomas Harte
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00
Thomas Harte
5c881bd19d
Implements PLX, PLY, PHX and PHY.
2018-08-06 22:00:23 -04:00
Thomas Harte
1a44ef0469
Introduces Klaus Dorman's 65C02 tests. All failing.
2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51
Fixes test target.
2018-08-06 21:15:13 -04:00
Thomas Harte
633af4d404
The operations table is now per-instance.
2018-08-06 20:47:14 -04:00
Thomas Harte
76a73c835c
Forces 6502 consumers to declare which model — the original, 65C02 or 65SC02.
...
All present machines use a regular 6502.
2018-08-06 20:06:07 -04:00
Thomas Harte
5d6b5d9f10
Eliminates all emdashes in cross-platform code.
2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
5aef81cf24
Commutes cross-platform #pragma marks to //MARK:s.
2017-11-12 15:59:11 -05:00
Thomas Harte
2e15fab651
Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
2017-11-11 15:28:40 -05:00
Thomas Harte
4cbc87a17d
Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502.
2017-11-10 22:20:44 -05:00
Thomas Harte
e983854e71
Converts all uint8_t and uint16_t casts to the functional style.
2017-10-21 21:50:53 -04:00
Thomas Harte
ab2bcb939f
Separates 6502Base into its constituent parts.
2017-09-04 11:08:33 -04:00
Thomas Harte
de218611e4
Corrects possible confusion as documentation recommends Cycles(0) as default, but then gives Cycles(1).
2017-09-01 20:49:24 -04:00
Thomas Harte
b306776ba9
Removes from 6502.hpp all remaining implementation details, making it purely an interface document.
...
Though those details remain visible to files including 6502.hpp through necessity.
2017-09-01 19:46:29 -04:00
Thomas Harte
4af333d5ec
Tidies the 6502 template and folder hierarchy.
...
Specifically: there's now just the one .h file at the top level, giving a clear indication of what a user should read. That separates implementation from interface. It also devolves a lot more to the base class because doing so makes debug builds less of a hassle. The all-RAM 6502 has been shuffled off into a subfolder, to indicate that it's not something you necessarily need know about. Also general documentation improvements have been applied: incorrect citing of the recurring-template pattern has been removed and the meaning of the two BusHandler methods has now accrued at the bus handler.
2017-08-31 22:10:27 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
42b5b66305
Remove the 6502's use of runtime polymorphism in favour of ordinary templating.
2017-08-16 11:56:52 -04:00
Thomas Harte
4abd62e62b
Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
8361756dc4
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
2017-07-27 07:40:02 -04:00
Thomas Harte
279c369a1f
Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
2017-07-25 22:21:09 -04:00
Thomas Harte
75d67ee770
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
2017-07-25 20:20:55 -04:00
Thomas Harte
a1e9a54765
Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
2017-07-25 20:09:13 -04:00
Thomas Harte
677ed463f0
Updated comment per new method name.
2017-07-24 21:19:49 -04:00
Thomas Harte
b82bef95f3
Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
2017-07-24 20:10:05 -04:00
Thomas Harte
2ff157cf7a
Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
2017-07-22 22:17:29 -04:00
Thomas Harte
83628b285b
Experimentally turned the 6502 into a clock receiver. No problem encountered.
2017-07-22 21:52:21 -04:00
Thomas Harte
1a811b1ab1
Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class.
2017-06-03 22:19:35 -04:00
Thomas Harte
c26349624c
This, of course, should be inline to gain any benefit from the slightly-tortured private implementation.
2017-06-03 22:00:57 -04:00
Thomas Harte
b642d9f712
Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
Thomas Harte
b304c3a4b9
Eliminated the 6502's reliance on the micro-op scheduler.
2017-06-03 20:30:07 -04:00
Thomas Harte
01f7394f7f
Corrected 6502 scheduling when flushing the pipeline.
2017-05-30 20:58:07 -04:00
Thomas Harte
5aa8b03349
Attempted to regularise the 6502 with the Z80 as to scheduling. I think that at least one bug remains.
2017-05-30 20:36:53 -04:00
Thomas Harte
a0189a6fe1
Switched to following the current program via address.
2017-05-30 18:49:40 -04:00
Thomas Harte
21d0602305
Restored the all RAM 6502's lack of power-on reset.
2017-05-17 21:43:40 -04:00
Thomas Harte
7190f927b7
Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
2017-05-16 21:28:17 -04:00
Thomas Harte
d559d8b901
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
2017-05-16 21:19:17 -04:00
Thomas Harte
eb8a2de5d6
Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
2017-05-15 07:38:59 -04:00
