Thomas Harte
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7b164de6fd
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Reenables interrupts.
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2021-03-06 18:53:39 -05:00 |
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Thomas Harte
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24e68166c6
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Minor clean-ups of my temporary cruft.
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2021-03-06 17:11:06 -05:00 |
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Thomas Harte
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b72474f418
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Reduces debugging shout outs a touch.
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2021-03-03 20:53:05 -05:00 |
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Thomas Harte
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38046d49aa
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Increases debugging noise.
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2021-03-03 20:52:14 -05:00 |
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Thomas Harte
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4601421aa6
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This conditional is gone.
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2021-03-03 20:52:01 -05:00 |
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Thomas Harte
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2f45e07d82
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Further consolidates region map, now that shadowing is orthogonal.
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2021-02-28 15:22:36 -05:00 |
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Thomas Harte
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496b6b5cfc
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Introduces a further 128 bits of storage to eliminate the conditional in IsShadowed.
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2021-02-28 15:14:32 -05:00 |
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Thomas Harte
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8604b1786e
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Simplifies banks $02+ to a single region.
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2021-02-27 23:34:51 -05:00 |
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Thomas Harte
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267e28e012
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Adds various bits of debugging detritus.
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2021-02-27 22:27:57 -05:00 |
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Thomas Harte
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631a8a7421
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Adds bitset header.
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2021-02-27 22:13:49 -05:00 |
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Thomas Harte
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7dcb0553e4
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Switches to a target-centric view of shadowing.
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2021-02-27 22:13:10 -05:00 |
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Thomas Harte
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55c9d152e9
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Slightly smarter: this does branchless shadowing without additional storage.
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2021-02-24 18:46:41 -05:00 |
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Thomas Harte
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6cf9099ce1
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Don't clear the mouse data full flag until both registers have been read.
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2021-02-23 21:57:02 -05:00 |
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Thomas Harte
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e6dc39f6f0
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Makes an attempt at mouse event transmission.
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2021-02-19 22:48:15 -05:00 |
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Thomas Harte
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28ce675c96
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Takes a further stab at ::CommandDataIsValid.
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2021-02-19 22:22:14 -05:00 |
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Thomas Harte
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3d91b0a31b
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Fixes keyboard data return.
Input sort of works now! Except that key repeat is way out of control.
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2021-02-19 21:55:06 -05:00 |
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Thomas Harte
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5d1970d201
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Adds a hacky different guess at how register access might work.
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2021-02-19 21:46:18 -05:00 |
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Thomas Harte
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72d7901c88
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Takes a shot at the keyboard data full flag.
Just a guess. But likely?
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2021-02-19 20:06:12 -05:00 |
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Thomas Harte
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60cfec6a65
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Amongst ever more cruft, adds a couple of extra asserts.
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2021-02-18 22:49:48 -05:00 |
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Thomas Harte
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2e9065b34c
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Increases number of fixed initial values.
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2021-02-18 22:48:53 -05:00 |
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Thomas Harte
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e42843cca0
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This may temporarily exhaust my wit for asserts.
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2021-02-16 22:47:46 -05:00 |
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Thomas Harte
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3336a123f8
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Asserts even more overtly.
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2021-02-16 22:33:28 -05:00 |
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Thomas Harte
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28bd620e7f
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Adds joystick support to the IIgs.
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2021-02-16 19:39:22 -05:00 |
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Thomas Harte
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fa8236741d
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Takes a shot at an ADB mouse.
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2021-02-15 20:49:16 -05:00 |
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Thomas Harte
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99c21925f4
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Makes attempt at keyboard mapping.
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2021-02-15 15:00:12 -05:00 |
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Thomas Harte
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eccf5ca043
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Makes first effort to wire up the ADB vertical blank input.
However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
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2021-02-14 22:20:58 -05:00 |
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Thomas Harte
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52cf15c3e6
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Attempts to route out modifier state.
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2021-02-14 21:15:31 -05:00 |
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Thomas Harte
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a791680e6f
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Implements set_status as per advice.
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2021-02-14 21:04:20 -05:00 |
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Thomas Harte
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17e9305282
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Starts adding a keyboard.
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2021-02-13 23:16:45 -05:00 |
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Thomas Harte
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2ab3bba695
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Attempts GLU register latching, restoring expected startup sequence.
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2021-02-13 17:38:42 -05:00 |
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Thomas Harte
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2c4dcf8843
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Edges towards implementing an ADB device.
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2021-02-12 21:50:24 -05:00 |
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Thomas Harte
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6ca8aa99fc
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Commit SDL and Qt project files; improve commenting.
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2021-02-10 21:28:32 -05:00 |
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Thomas Harte
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17bac4c8cf
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Starts to formalise the ADB bus.
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2021-02-10 21:24:31 -05:00 |
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Thomas Harte
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46bd20b5e0
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Attempts to simplify ADB bit parsing.
On-line output still looks reasonable, albeit that the microcontroller suddenly seems to be interested in devices F and 3 rather than 2 and 3.
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2021-02-08 22:08:49 -05:00 |
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Thomas Harte
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93a80a30d3
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With correct divider appears to get reset requests posted.
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2021-02-07 23:05:01 -05:00 |
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Thomas Harte
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77b1efd176
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Sets sensible 'reset' values.
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2021-02-07 21:53:57 -05:00 |
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Thomas Harte
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acfab1dfb3
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Starts to make some effort at timers.
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2021-02-06 21:02:44 -05:00 |
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Thomas Harte
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b8c6d4b153
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Rips out my high-level ADB microcontroller protocol implementation.
Adds just enough that the main computer validates the ADB controller as present and talking.
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2021-01-30 17:53:27 -05:00 |
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Thomas Harte
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f50e8b5106
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If I'm going to maintain the max_address approach, & is 'correct'.
% +1 would be 'more correct', but I think this approach is probably misguided.
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2021-01-27 18:31:11 -05:00 |
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Thomas Harte
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dcc2fe0990
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Improves M50470 entry-point detection, adds test output.
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2021-01-26 21:29:17 -05:00 |
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Thomas Harte
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56111c75ae
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Makes first efforts towards disassembly.
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2021-01-26 19:52:30 -05:00 |
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Thomas Harte
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fc4bda0047
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Experimentally flipping interpretation of the output bit gives something closer to coherent.
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2021-01-25 22:02:39 -05:00 |
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Thomas Harte
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c8beb59172
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Attempts properly to track ADB bus activity.
Output is not yet a valid ADB stream. Work to do.
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2021-01-25 17:43:22 -05:00 |
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Thomas Harte
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8789ffda15
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Corrects performer storage, RMW/W confusion, implicit casts, port readback.
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2021-01-24 22:30:42 -05:00 |
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Thomas Harte
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e8e604dc3c
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Attempts to wire up M50470 and GLU.
Resulting in an unexpected interest in R15. Bugs to find, I guess.
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2021-01-24 18:07:05 -05:00 |
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Thomas Harte
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57e0fdfadc
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Ensures ADB microcontroller is clocked.
And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).
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2021-01-23 22:55:12 -05:00 |
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Thomas Harte
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ec0018df79
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Routes in the ADB keyboard ROM. This should get as far as parsing.
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2021-01-18 16:59:49 -05:00 |
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Thomas Harte
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12784a71e2
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A stab in the dark: does the IOLC inhibit also affect vector fetches?
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2020-12-29 20:53:56 -05:00 |
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Thomas Harte
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114d48b076
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This register appears to be read/write.
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2020-12-11 21:43:34 -05:00 |
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Thomas Harte
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159924dcc0
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More clarity tweaks.
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2020-12-10 22:47:11 -05:00 |
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