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9,790 Commits 8 Branches 121 Tags 496 MiB
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1049 Commits

Author SHA1 Message Date
Thomas Harte
318cea4ccd Attempt a full bus-transaction comparison. 2022-08-06 10:06:49 -04:00
Thomas Harte
93d2a612ee Add an explicit flush-pipeline step; some tests now pass. 2022-07-29 16:33:46 -04:00
Thomas Harte
1ac0a4e924 Provide a loop count directly from the sequencer. 
This avoids the caller having to take a guess at iterations.
 2022-07-29 12:14:59 -04:00
Thomas Harte
d85d70a133 Add documentation, formal begin function. 2022-07-26 22:01:43 -04:00
Thomas Harte
76979c8059 Add missing tests. 2022-07-26 21:47:02 -04:00
Thomas Harte
86246e4f45 Introduce partial Blitter sequencer test. 2022-07-26 21:28:12 -04:00
Thomas Harte
4ddbf095f3 Fully banish flush from the processors. 2022-07-12 10:49:53 -04:00
Thomas Harte
f7e75da4bd Disable [temporarily?] outdated shadowing tests. 2022-06-29 15:14:51 -04:00
Thomas Harte
825136b168 Fix installation of LCW test value; thereby permit all tests. 2022-06-29 15:04:21 -04:00
Thomas Harte
5a9eb58d33 Fix test generator: IO state can be cleared. 2022-06-29 14:57:14 -04:00
Thomas Harte
beb4993548 Remove card pages from the equation. 2022-06-29 14:51:50 -04:00
Thomas Harte
48e8bfbb0e Introduce failing is-IO test. 2022-06-29 14:44:17 -04:00
Thomas Harte
5dfbc58959 Fix test generator's concept of hires2 shadowing. 2022-06-29 14:41:56 -04:00
Thomas Harte
924de35cf3 Go all in on support for physical shadowing. 2022-06-29 14:39:56 -04:00
Thomas Harte
60d3519993 Clarify, attempt to implement as internally documented. 2022-06-28 22:32:31 -04:00
Thomas Harte
c6b4570424 Fix Markdown code marking. 2022-06-28 17:12:38 -04:00
Thomas Harte
f5d56cc473 Add first pass at testing shadowing. 2022-06-28 17:12:25 -04:00
Thomas Harte
4e52572b03 Omit language card write tests. 2022-06-28 16:57:09 -04:00
Thomas Harte
6abc317986 Avoid permitting writes in the Cx00 region after uninhibiting the language card. 2022-06-28 16:35:47 -04:00
Thomas Harte
22c0b588c4 Tidy up slightly, without fixing failure. 2022-06-28 16:32:35 -04:00
Thomas Harte
6c9fc0ac75 Introduce [failing] write area tests. 2022-06-28 16:28:00 -04:00
Thomas Harte
ef322dc705 Reformulate to allow addition of write tests, momentarily. 2022-06-28 16:22:41 -04:00
Thomas Harte
823c7765f8 Avoid manual index counting. 2022-06-27 11:16:05 -04:00
Thomas Harte
5cb0aebdf4 For the sake of poor Xcode, stop after a single failure. 2022-06-27 11:10:51 -04:00
Thomas Harte
686dccb48d Correct comparison. 2022-06-26 21:49:58 -04:00
Thomas Harte
1f7700edac Ensure proper register hits. 2022-06-26 21:20:57 -04:00
Thomas Harte
5adc656066 Make some attempt to use the JSON tests. 2022-06-25 21:41:37 -04:00
Thomas Harte
9cf64ea643 Import generated tests. 2022-06-25 16:46:57 -04:00
Thomas Harte
f2c2027a8c Disable test generation for commit. 2022-06-24 16:50:23 -04:00
Thomas Harte
ef5ac1442f Don't invent an address for STP and WAI. 2022-06-24 13:05:32 -04:00
Thomas Harte
1c1ce625a7 Vector reads signal VDA. 2022-06-24 10:37:39 -04:00
Thomas Harte
a442077eac Allow repetition for MVN and MVP only. 2022-06-24 10:34:43 -04:00
Thomas Harte
6c638712f3 Attempt to capture MVP and MVN in their entirety. 2022-06-24 07:39:58 -04:00
Thomas Harte
2e7afb13c7 Exit gracefully upon a STP or WAI. 2022-06-23 21:03:40 -04:00
Thomas Harte
65140b341d Simplify slightly, per new S reporting rule. 2022-06-22 16:43:00 -04:00
Thomas Harte
2f684ee66d Use null for values that were never loaded. 2022-06-21 21:47:18 -04:00
Thomas Harte
ab0c290489 Use 'x' instead of 'i'. 2022-06-19 06:58:23 -04:00
Thomas Harte
15ac2c3e5a Output to files, at volume, with extended bus flags. 2022-06-18 22:00:50 -04:00
Thomas Harte
0c24a27ba6 Completely prints tests. 2022-06-18 21:32:50 -04:00
Thomas Harte
eb82e06fab Add randomised initial state, fix PC. 2022-06-18 19:21:56 -04:00
Thomas Harte
f8e6954739 Ensure complete runs of each tested opcode. 2022-06-18 16:26:40 -04:00
Thomas Harte
b62f484d93 Start scaffolding a 65816 test generator. 2022-06-18 13:28:15 -04:00
Thomas Harte
6cc41d6dda Restore 1000 test count. 2022-06-14 22:02:53 -04:00
Thomas Harte
d91f8a264e Flip presumption, reenabling most tests. 2022-06-14 21:57:14 -04:00
Thomas Harte
e066546c13 Resolve PEA timing errors. 2022-06-13 14:08:42 -04:00
Thomas Harte
7dc66128c2 Fix strobe output. 2022-06-13 10:49:47 -04:00
Thomas Harte
e484e4c9d7 Expand test to make sure that correct data strobes are active. 2022-06-13 10:39:06 -04:00
Thomas Harte
f316cbcf94 The old implementation was correct. 2022-06-11 21:15:08 -04:00
Thomas Harte
0a6b2b7d32 Verify newer CMPA.l, RTE, TRAP[V] and CHK. 2022-06-11 11:17:18 -04:00
Thomas Harte
c3345dd839 Fix MOVEM timing. 2022-06-10 21:52:07 -04:00
Thomas Harte
917b7fbf80 Notarise won't fix status of CLR, NEGX, NEG, NOT. 2022-06-10 16:50:38 -04:00
Thomas Harte
97715e7ccc Expand test set to include those with timing discrepancies. 2022-06-10 16:34:05 -04:00
Thomas Harte
43c0dea1bd With the difference in RESET times now factored out, test timing too. 2022-06-10 16:12:54 -04:00
Thomas Harte
2e4652209b Remove entire RESET sequence, move to testing PEA. 2022-06-10 15:57:54 -04:00
Thomas Harte
e2d811a7a0 Notarise digressions that appear to be correct, remove now-working RTE/RTR. 2022-06-09 21:48:15 -04:00
Thomas Harte
dd5c903fd6 DIVS also appears sometimes to differ. 2022-06-09 20:19:39 -04:00
Thomas Harte
2e1675066d Reinstate address error non-testing. 2022-06-09 16:59:06 -04:00
Thomas Harte
be84ce657b Add an optional testing whitelist. 2022-06-09 16:18:04 -04:00
Thomas Harte
64053d697f Take improved guess at address error stacking order. 2022-06-09 16:17:09 -04:00
Thomas Harte
a59ad06438 Print out summary of failure. 2022-06-09 13:13:33 -04:00
Thomas Harte
5af03d74ec Add note to self about first diagnosis. 2022-06-09 12:21:39 -04:00
Thomas Harte
ba2803c807 Include all bus activity after the split. 2022-06-09 11:30:22 -04:00
Thomas Harte
fdcbf617d8 Avoid STOP. 2022-06-09 08:42:31 -04:00
Thomas Harte
2e42bda0a3 Permit instructions that end in an address error to differ in transactions. 2022-06-08 16:15:33 -04:00
Thomas Harte
168dc12e27 Avoid spurious mismatches. 2022-06-08 16:03:02 -04:00
Thomas Harte
fd1955e15b Attempt to randomise and test register contents. 2022-06-08 15:12:47 -04:00
Thomas Harte
f4f93f4836 Test a single, whole instruction; record read/write. 2022-06-08 14:53:04 -04:00
Thomas Harte
dd0a7533ab Randomise all parts of memory other than the opcode. 2022-06-08 14:43:51 -04:00
Thomas Harte
50130b7004 Minor layout tweak. 2022-06-08 11:42:42 -04:00
Thomas Harte
ab52c5cef2 Pass first all-zeroes test, establishing that processors aren't being fully reset. 2022-06-08 10:56:54 -04:00
Thomas Harte
c7fa93a5bc Attempt human-legible explanation of differences encountered. 2022-06-08 10:51:05 -04:00
Thomas Harte
400b73b5a2 Allow capture to be limited; retain timestamps. 2022-06-08 09:49:27 -04:00
Thomas Harte
788b026cf5 Log and attempt to compare some activity. Sort of. 2022-06-07 16:56:05 -04:00
Thomas Harte
c4ae5d4c8d Establishes at least that both 68000s can run. 2022-06-06 21:47:10 -04:00
Thomas Harte
ca8dd61045 Start sketching out an old vs new 68000 test. 2022-06-06 21:19:57 -04:00
Thomas Harte
7b3cf6e747 Add missing instruction: RESET. 2022-06-03 11:15:39 -04:00
Thomas Harte
640b04e59e Test only well-defined flags. 
Albeit that timing is still off.
 2022-06-03 10:18:46 -04:00
Thomas Harte
10b9b13673 Disable divide-by-zero PC test in lieu of better documentation. 2022-06-03 08:27:20 -04:00
Thomas Harte
90d720ca28 Don't test undocumented flags. 2022-06-02 12:30:39 -04:00
Thomas Harte
6dd89eb0d7 Adjust my expectation as to length. 2022-06-02 12:11:54 -04:00
Thomas Harte
e1abf431cb Don't test undefined flags. 2022-05-30 16:23:51 -04:00
Thomas Harte
8e0fa3bb5f DIV # with a divide by zero should be 44 cycles. 2022-05-29 21:22:45 -04:00
Thomas Harte
9eea471e72 Resolve infinite recursion. 2022-05-29 20:39:22 -04:00
Thomas Harte
2a40e419fc Fix CHK tests: timing and expected flags. 2022-05-29 15:26:56 -04:00
Thomas Harte
5f030edea4 Simplify transaction. 2022-05-26 19:37:30 -04:00
Thomas Harte
88e33353a1 Fix instruction and time counting, and initial state. 2022-05-26 09:17:37 -04:00
Thomas Harte
f3c0c62c79 Switch register-setting interface. 2022-05-26 07:52:14 -04:00
Thomas Harte
866787c5d3 Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence. 2022-05-25 20:22:38 -04:00
Thomas Harte
64491525b4 Work further to guess at caller's intention for set_state. 
Probably I should just eliminate the initial reset, somehow.
 2022-05-25 17:01:18 -04:00
Thomas Harte
68b184885f Reapply only the status. 2022-05-25 16:54:25 -04:00
Thomas Harte
06f3c716f5 Make better effort to establish initial state. 2022-05-25 16:47:41 -04:00
Thomas Harte
22714b8c7f Capture state at instruction end, for potential inspection. 2022-05-25 16:32:26 -04:00
Thomas Harte
f9d1c554b7 Fix for the actual number of cycles in a standard reset. 2022-05-25 16:05:28 -04:00
Thomas Harte
f2a7660390 Merge branch 'master' into 68000Mk2 2022-05-25 15:40:10 -04:00
Thomas Harte
4961e39fb6 Mention DIVU/DIVS flags. 2022-05-25 15:39:00 -04:00
Thomas Harte
0bedf608c0 Add details on gaps in coverage. 2022-05-25 15:36:27 -04:00
Thomas Harte
1ab831f571 Add the option to log a list of all untested instructions. 2022-05-25 13:17:01 -04:00
Thomas Harte
2c6b9b4c9d Switch comparative trace tests to 68000 Mk2. 2022-05-25 11:32:00 -04:00
Thomas Harte
463fbb07f9 Adapt remaining 68000 tests to use Mk2. 2022-05-25 10:55:17 -04:00
Thomas Harte
4b07c41df9 Ensure alignment of storage. 2022-05-24 11:29:28 -04:00