 Thomas Harte
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39b8285ba5
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Trust the HRM on step bit, but catch rising edge.
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2021-10-11 07:42:42 -07:00 |
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Thomas Harte
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7733fef3bd
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DSKLEN has to be written twice.
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2021-10-11 06:16:01 -07:00 |
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Thomas Harte
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6acddfdb98
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Add the sync match interrupt.
Albeit that it doesn't yet unblock disk DMA.
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2021-10-11 03:37:56 -07:00 |
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Thomas Harte
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ec3d5c0b32
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Increase maximum number of activity LEDs to eight.
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2021-10-10 18:37:33 -07:00 |
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Thomas Harte
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99492c2ec2
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Further tweak logging.
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2021-10-10 18:19:50 -07:00 |
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Thomas Harte
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addf9f9af4
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Moves block byte writes into Storage::Encodings::MFM::Encoder.
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2021-10-10 16:06:51 -07:00 |
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Thomas Harte
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846b505d27
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Reduce logging; disk data probably isn't the immediate obstacle.
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2021-10-10 13:04:10 -07:00 |
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Thomas Harte
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c4cfcfab8e
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Checksums appear to be calculated as 32-bit quantities.
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2021-10-10 12:58:10 -07:00 |
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Thomas Harte
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5e083426c5
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Takes another run at checksums.
It turns out I'd read entirely the wrong section of the ADF FAQ. Am now trying to piece things together from various EAB threads.
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2021-10-10 11:47:48 -07:00 |
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Thomas Harte
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8d43b4a98d
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Expands Disk DMA access window.
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2021-10-10 11:47:02 -07:00 |
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Thomas Harte
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aeaea073c6
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Switch both: (i) which bits are odd/even; and (ii) nibble ordering.
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2021-10-09 13:45:19 -07:00 |
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Thomas Harte
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6b0dd19442
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Name file appropriately: the logo comes from Kickstart.
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2021-10-09 08:02:15 -07:00 |
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Thomas Harte
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9336ffe216
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Take a stab at index-hole sync.
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2021-10-09 08:01:02 -07:00 |
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Thomas Harte
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eb157f15f3
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Adds index hole interrupt.
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2021-10-09 04:08:59 -07:00 |
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Thomas Harte
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d6e2a3f425
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Make a first attempt to spool into RAM.
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2021-10-08 18:11:47 -07:00 |
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Thomas Harte
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b47ca13ed3
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Push disk data onwards.
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2021-10-08 17:18:11 -07:00 |
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Thomas Harte
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67546c4d6e
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Per the HRM, the index hole is connected to CIA B, potentially to raise an interrupt.
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2021-10-08 17:12:37 -07:00 |
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Thomas Harte
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f72deb0a5c
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Correct RDY position.
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2021-10-08 04:32:13 -07:00 |
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Thomas Harte
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616ccbb878
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Correct ID bit placement, multiplex with motor state.
The latter per my reading of http://www.primrosebank.net/computers/amiga/upgrades/amiga_upgrades_storage_fdis.htm
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2021-10-08 04:05:57 -07:00 |
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Thomas Harte
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5899af0038
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Starts accumulating disk data.
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2021-10-07 05:11:32 -07:00 |
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Thomas Harte
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ed303310bb
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Spell out slightly more; this makes debugging a touch easier.
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2021-10-06 13:40:48 -07:00 |
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Thomas Harte
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33ff4f3b5c
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Eliminate drive copies.
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2021-10-06 13:40:28 -07:00 |
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Thomas Harte
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20bad38d42
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Add drive activity lights.
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2021-10-06 04:54:40 -07:00 |
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Thomas Harte
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92a07398cd
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I think CHNG works the other way around.
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2021-10-06 04:47:52 -07:00 |
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Thomas Harte
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ce8f782577
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Corrects meaning of IBM-style RDY.
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2021-10-06 04:42:44 -07:00 |
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Thomas Harte
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e961d0b4a3
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Switch RDY type.
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2021-10-06 04:41:09 -07:00 |
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Thomas Harte
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2253ff656a
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Adds route for inserting disks.
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2021-10-05 16:12:30 -07:00 |
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Thomas Harte
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18631399ad
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Attempts to clock the disk controller.
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2021-10-05 15:38:56 -07:00 |
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Thomas Harte
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ad4afcdcd5
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Switch stepping direction.
Empirically, based on the actions of Kickstart, and assuming my confusion is because the relevant signal is active low.
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2021-10-05 15:23:48 -07:00 |
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Thomas Harte
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2cf5bcc5db
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Clarify logic somewhat.
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2021-10-05 15:20:05 -07:00 |
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Thomas Harte
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1180ad7662
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Disables a couple of now-trustworthy LOGs.
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2021-10-05 06:51:47 -07:00 |
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Thomas Harte
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5463cd1ae3
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Attempts to support stepping and head selection.
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2021-10-05 06:36:17 -07:00 |
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Thomas Harte
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647ec770ce
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Implements motor latching, drive ID shift registers.
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2021-10-05 05:12:01 -07:00 |
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Thomas Harte
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e47bec2e65
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Switch CIA B ports over.
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2021-10-05 03:38:11 -07:00 |
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Thomas Harte
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6566936be9
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Be overt about the intended interface.
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2021-10-04 16:45:33 -07:00 |
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Thomas Harte
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674941abdf
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Starts to add a disk controller.
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2021-10-04 16:45:05 -07:00 |
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Thomas Harte
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b3f0ca39ed
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Adds some unused drives.
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2021-10-04 08:12:13 -07:00 |
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Thomas Harte
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5ccb512883
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Moves the CIAs into the Chipset class.
This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.
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2021-10-04 06:44:54 -07:00 |
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Thomas Harte
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da286d5ae8
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Switch spaces to tabs.
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2021-10-04 05:27:25 -07:00 |
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Thomas Harte
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73e45511dc
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Add missing #include.
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2021-10-04 05:26:38 -07:00 |
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Thomas Harte
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a282a51673
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Remove last of the direct printf'ing.
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2021-09-30 02:42:59 -04:00 |
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Thomas Harte
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b7b13e20d1
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Single column blits should use both masks.
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2021-09-29 22:49:35 -04:00 |
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Thomas Harte
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ad90c6b6ce
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Now that this is getting close, don't stop at the first error.
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2021-09-29 22:19:34 -04:00 |
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Thomas Harte
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402fa41bc0
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Corrects initial error value.
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2021-09-29 22:19:17 -04:00 |
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Thomas Harte
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0b9ebafc0f
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Flip bit deserialisation order.
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2021-09-28 22:12:13 -04:00 |
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Thomas Harte
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140e24ef15
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Grab further copy flags.
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2021-09-28 22:11:58 -04:00 |
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Thomas Harte
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0c998d60cb
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Correct test logic for line draws that repeatedly write to the same address.
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2021-09-28 21:45:55 -04:00 |
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Thomas Harte
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ffcd2ea10c
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Attempts more properly to implement line mode.
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2021-09-28 21:39:09 -04:00 |
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Thomas Harte
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cb460de94d
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Makes bad first attempt at a Bresenham inner loop.
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2021-09-27 22:06:00 -04:00 |
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Thomas Harte
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f6624bf776
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Edges mildly closer to line output.
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2021-09-26 19:18:12 -04:00 |
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