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Author	SHA1	Message	Date
Thomas Harte	82b08d0e3a	Corrects addressing behaviour of nRd[+-].	2019-04-17 08:53:34 -04:00
Thomas Harte	8f77d1831b	Implements MULU and MULS.	2019-04-16 22:16:43 -04:00
Thomas Harte	be722143e1	Completes addressing modes for ADDI/etc/etc.	2019-04-16 21:34:16 -04:00
Thomas Harte	d8d974e2d7	Consolidates JSR and BSR preparation.	2019-04-16 21:29:37 -04:00
Thomas Harte	9b7ca6f271	Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. ... Also corrects the BSR return address.	2019-04-16 19:50:10 -04:00
Thomas Harte	8ce018dbab	Adds the necessary runtime support for AND, EOR and OR.	2019-04-16 15:17:40 -04:00
Thomas Harte	180062c58c	Finishes fleshing out [ADD/SUB]Q.	2019-04-16 14:28:31 -04:00
Thomas Harte	6076b8df69	Merge branch 'master' into 68000	2019-04-16 14:07:23 -04:00
Thomas Harte	5e65ee79b1	Merge pull request #617 from TomHarte/MSXDisk ... Removes hard-coded assumption about disk ROM list placement.	2019-04-16 11:22:52 -04:00
Thomas Harte	c0861c7362	Removes hard-coded assumption about disk ROM list placement.	2019-04-16 11:22:03 -04:00
Thomas Harte	37656f14d8	Adds basic addressing modes for [ADD/SUB]Q.	2019-04-16 11:19:45 -04:00
Thomas Harte	dec5535e54	Implements (arguably: fixes) BSR.	2019-04-15 23:20:36 -04:00
Thomas Harte	1f0e3b157a	Corrects a couple of JSR and JMP addressing modes.	2019-04-15 22:37:11 -04:00
Thomas Harte	d802e83f49	Fills in further MOVEs.	2019-04-15 22:25:22 -04:00
Thomas Harte	ebcae25762	Adjusts JSR behaviour and further extends MOVE.	2019-04-15 22:02:52 -04:00
Thomas Harte	5330267d16	Implements BCLR.	2019-04-15 18:11:02 -04:00
Thomas Harte	892476973b	Attempts RO{X}[L/R].	2019-04-15 17:31:58 -04:00
Thomas Harte	84f4a25bc9	Completes TST.	2019-04-15 16:28:20 -04:00
Thomas Harte	1460a88bb3	Takes a run at JSR and RTS.	2019-04-15 15:14:38 -04:00
Thomas Harte	62e4c23961	Corrects memory map, causing the RAM test no longer to fail.	2019-04-15 13:03:32 -04:00
Thomas Harte	d25ab35d58	Finally gets setw usage correct.	2019-04-15 12:41:56 -04:00
Thomas Harte	a223cd90a1	Adds predecrement TSTs, increases QL running time, reduces logging.	2019-04-15 12:36:08 -04:00
Thomas Harte	aef92ba29c	Corrects immediate shift count.	2019-04-15 12:25:45 -04:00
Thomas Harte	328d297490	Implements the first few addressing modes for TST.	2019-04-15 10:03:52 -04:00
Thomas Harte	3d240f3f18	Corrects decoding of DBcc.	2019-04-15 09:49:23 -04:00
Thomas Harte	45f35236a7	Corrects decoding of ADDA and SUBA.	2019-04-15 09:44:06 -04:00
Thomas Harte	fba210f7ce	Corrects MOVE.l Dn, (An)[+].	2019-04-15 09:30:49 -04:00
Thomas Harte	8a09e5fc16	Implements Scc.	2019-04-14 22:39:13 -04:00
Thomas Harte	52e33e861c	Starts to introduce the QL as a second source for 68000 testing. ... It's advantageous over the ST in that a commented disassembly of the ROM is available.	2019-04-14 22:15:09 -04:00
Thomas Harte	75d8824e6b	Eliminates implicit type conversion.	2019-04-14 21:02:28 -04:00
Thomas Harte	325af677d3	Implements MOVEM to M with an implicit type conversion.	2019-04-14 20:53:27 -04:00
Thomas Harte	1003e70b5e	Implements MOVEM to R.	2019-04-14 20:02:18 -04:00
Thomas Harte	d70229201d	Advances right up to the lack of MOVEM actions being the final piece.	2019-04-14 14:45:29 -04:00
Thomas Harte	823f91605b	Still slow pedalling slightly, adds further MOVEM storage.	2019-04-14 14:31:13 -04:00
Thomas Harte	53f75034fc	Commits at least to decoding MOVEM.	2019-04-14 14:09:28 -04:00
Thomas Harte	78649a5b54	Fleshes out MOVE, (XXX) a little further.	2019-04-12 17:16:03 -04:00
Thomas Harte	f48db625a0	Corrects write-back and zero flag for ADD/SUB.l.	2019-04-12 16:41:00 -04:00
Thomas Harte	2ba66c4457	Corrects MOVEA, adds extra test safeguards.	2019-04-12 16:10:17 -04:00
Thomas Harte	2c78ea1a4e	Completes conversion away from magic constants.	2019-04-12 15:48:29 -04:00
Thomas Harte	73f50ac44e	Commits further to elimination of magic constants.	2019-04-12 13:45:28 -04:00
Thomas Harte	9ce48953c1	Improves debugging printout.	2019-04-12 13:45:03 -04:00
Thomas Harte	1098cd0c6b	Begins rooting out magic constants.	2019-04-11 22:31:17 -04:00
Thomas Harte	652ebd143c	Corrects addressing mode support for LEA.	2019-04-11 11:58:34 -04:00
Thomas Harte	8e9d7c0f40	Corrects register-relative address calculation.	2019-04-10 23:09:03 -04:00
Thomas Harte	a64948a2ba	Permits zero-bus-op non-terminals.	2019-04-10 22:42:43 -04:00
Thomas Harte	43f619a081	Implements ASL, ASR, LSL and LSR.	2019-04-10 22:31:04 -04:00
Thomas Harte	a07de97df4	Implements the fixed part of register shifts.	2019-04-09 22:12:37 -04:00
Thomas Harte	85d25068a8	Attempts a full implementation of memory shifts.	2019-04-09 22:04:25 -04:00
Thomas Harte	7a0319cfe5	Kicks the work of dealing with ASL/etc into the runtime.	2019-04-09 21:48:08 -04:00
Thomas Harte	f750671f33	Stepping gingerly onwards, adds a double-decoding test. ... As a result of that, collapses BRA into Bcc. Which provisionally looks correct.	2019-04-09 16:54:41 -04:00