38 Commits

Author	SHA1	Message	Date
Thomas Harte	d3ed485e7a	Take another big swing at indentation, some consts.	2024-12-01 21:44:14 -05:00
Thomas Harte	bc5727af14	Switch to = default.	2024-02-16 21:50:15 -05:00
Thomas Harte	a6df20ff84	Eliminate printf.	2024-01-21 21:19:38 -05:00
Thomas Harte	a3d37640aa	Switch include guards to #pragma once.	2024-01-16 23:34:46 -05:00
Thomas Harte	a6b8285d9c	Factor out the blitter sequencer.	2022-08-19 16:38:15 -04:00
Thomas Harte	bb54ac14b8	Prove that new output errors are [probably] external to the Blitter.	2022-08-15 11:10:17 -04:00
Thomas Harte	d4b7d73fc4	Further reduces lines to one access per slot, max.	2022-08-07 19:19:00 -04:00
Thomas Harte	867769f6e7	Reduces line drawing to two accesses per slot. ... Still a fiction, but a better one.	2022-08-07 19:15:03 -04:00
Thomas Harte	3781b5eb0e	Provide further context.	2022-08-06 14:40:12 -04:00
Thomas Harte	318cea4ccd	Attempt a full bus-transaction comparison.	2022-08-06 10:06:49 -04:00
Thomas Harte	45892f3584	Add optional transaction records to the Blitter.	2022-08-06 09:51:20 -04:00
Thomas Harte	612413cb1c	Remove redundant state.	2022-08-04 10:06:14 -04:00
Thomas Harte	511ec5a736	Apply modulos at end of final line. ... Possibly I need to rethink the sequence logic?	2022-07-30 21:35:26 -04:00
Thomas Harte	94a90b7a89	Attempt a real slot-by-slot blit.	2022-07-30 20:34:37 -04:00
Thomas Harte	5d992758f8	Ensure blitter with all flags disabled terminates.	2022-07-30 20:13:37 -04:00
Thomas Harte	93d2a612ee	Add an explicit flush-pipeline step; some tests now pass.	2022-07-29 16:33:46 -04:00
Thomas Harte	03d4960a03	Begin a full-synchronous usage of the sequencer, at least exposing poor handling of the pipeline.	2022-07-29 16:15:18 -04:00
Thomas Harte	1ac0a4e924	Provide a loop count directly from the sequencer. ... This avoids the caller having to take a guess at iterations.	2022-07-29 12:14:59 -04:00
Thomas Harte	d85d70a133	Add documentation, formal begin function.	2022-07-26 22:01:43 -04:00
Thomas Harte	2c95dea4db	Introduce putative blitter sequencer.	2022-07-26 17:05:05 -04:00
Thomas Harte	012084b37b	Fix exclusive fill, sizing, eliminate ECS call-ins. ... The clock test now proceeds further, but still doesn't seem to pass.	2021-11-24 17:25:32 -05:00
Thomas Harte	47f36f08fb	Switches to a synchronous audio state machine; renames advance -> advance_dma. ... I can worry about how to just-in-time things once I better understand the hardware in general.	2021-11-13 15:53:41 -05:00
Thomas Harte	edb75e69cb	Implement bitplane modulos.	2021-10-29 11:29:22 -07:00
Thomas Harte	07facc0636	Takes a stab at BZERO.	2021-10-28 18:12:46 -07:00
Thomas Harte	b10f5ab110	Apply A mask when loading into barrel shifter.	2021-10-26 20:02:28 -07:00
Thomas Harte	140e24ef15	Grab further copy flags.	2021-09-28 22:11:58 -04:00
Thomas Harte	f6624bf776	Edges mildly closer to line output.	2021-09-26 19:18:12 -04:00
Thomas Harte	b4b6c4d86f	Attempts to support left and right masks.	2021-09-26 18:42:08 -04:00
Thomas Harte	42ef459e20	Resolve resting values.	2021-09-23 22:05:59 -04:00
Thomas Harte	137d1c61bd	Allow for channel enables and blitting direction.	2021-09-23 18:38:37 -04:00
Thomas Harte	adc071ed7a	Fix: modulos are 15-bit signed, the minterms are also in regular BLTCON0.	2021-09-23 18:30:35 -04:00
Thomas Harte	ab69fe56c9	Take a first shot at magical instant blitting.	2021-09-23 18:13:51 -04:00
Thomas Harte	7092429f7c	Added some notes to self on line mode.	2021-09-20 23:08:26 -04:00
Thomas Harte	add11db369	Factors out DMADevice, which is now a parent of Blitter.	2021-09-14 20:51:32 -04:00
Thomas Harte	fd70f7ad43	Attempts to make pixel content observeable.	2021-09-08 20:57:26 -04:00
Thomas Harte	e412927415	Logs a bit more from the Blitter, gives it access to slots.	2021-08-10 07:17:01 -04:00
Thomas Harte	2bc9af09e1	Factors out the chipset.	2021-07-22 21:16:23 -04:00
Thomas Harte	e85db40b0f	Sketches out a blitter class.	2021-07-22 18:43:07 -04:00