2007-12-29 20:36:04 +00:00
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//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
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2007-12-04 22:35:58 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-12-04 22:35:58 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Cell SPU implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SPURegisterNames.h"
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#include "SPUInstrInfo.h"
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2008-01-01 21:11:32 +00:00
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#include "SPUInstrBuilder.h"
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2007-12-04 22:35:58 +00:00
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#include "SPUTargetMachine.h"
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#include "SPUGenInstrInfo.inc"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2008-05-29 21:46:33 +00:00
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#include "llvm/Support/Streams.h"
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2009-01-02 20:52:08 +00:00
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#include "llvm/Support/Debug.h"
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2007-12-04 22:35:58 +00:00
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using namespace llvm;
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2008-12-10 00:15:19 +00:00
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namespace {
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//! Predicate for an unconditional branch instruction
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inline bool isUncondBranch(const MachineInstr *I) {
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unsigned opc = I->getOpcode();
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return (opc == SPU::BR
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2009-01-26 03:37:41 +00:00
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|| opc == SPU::BRA
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|| opc == SPU::BI);
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2008-12-10 00:15:19 +00:00
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}
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2009-01-03 00:27:53 +00:00
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//! Predicate for a conditional branch instruction
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2008-12-10 00:15:19 +00:00
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inline bool isCondBranch(const MachineInstr *I) {
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unsigned opc = I->getOpcode();
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2008-12-27 04:51:36 +00:00
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return (opc == SPU::BRNZr32
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|| opc == SPU::BRNZv4i32
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2009-01-26 03:37:41 +00:00
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|| opc == SPU::BRZr32
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|| opc == SPU::BRZv4i32
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|| opc == SPU::BRHNZr16
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|| opc == SPU::BRHNZv8i16
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|| opc == SPU::BRHZr16
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|| opc == SPU::BRHZv8i16);
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2008-12-10 00:15:19 +00:00
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}
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}
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2007-12-04 22:35:58 +00:00
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SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
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2008-01-01 01:03:04 +00:00
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: TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
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2007-12-04 22:35:58 +00:00
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TM(tm),
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RI(*TM.getSubtargetImpl(), *this)
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2009-01-03 00:27:53 +00:00
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{ /* NOP */ }
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2007-12-04 22:35:58 +00:00
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bool
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SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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2009-01-20 19:12:24 +00:00
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unsigned& destReg,
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unsigned& SrcSR, unsigned& DstSR) const {
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SrcSR = DstSR = 0; // No sub-registers.
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2007-12-04 22:35:58 +00:00
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switch (MI.getOpcode()) {
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default:
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break;
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case SPU::ORIv4i32:
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case SPU::ORIr32:
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case SPU::ORHIv8i16:
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case SPU::ORHIr16:
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2008-02-23 18:41:37 +00:00
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case SPU::ORHIi8i16:
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2007-12-04 22:35:58 +00:00
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case SPU::ORBIv16i8:
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2007-12-17 22:32:34 +00:00
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case SPU::ORBIr8:
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2008-02-23 18:41:37 +00:00
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case SPU::ORIi16i32:
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case SPU::ORIi8i32:
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2007-12-04 22:35:58 +00:00
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case SPU::AHIvec:
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case SPU::AHIr16:
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2008-12-30 23:28:25 +00:00
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case SPU::AIv4i32:
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2007-12-04 22:35:58 +00:00
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assert(MI.getNumOperands() == 3 &&
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2008-10-03 15:45:36 +00:00
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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MI.getOperand(2).isImm() &&
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2007-12-04 22:35:58 +00:00
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"invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
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2007-12-30 20:49:49 +00:00
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if (MI.getOperand(2).getImm() == 0) {
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2007-12-04 22:35:58 +00:00
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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2007-12-19 07:35:06 +00:00
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case SPU::AIr32:
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assert(MI.getNumOperands() == 3 &&
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"wrong number of operands to AIr32");
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2008-10-03 15:45:36 +00:00
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if (MI.getOperand(0).isReg() &&
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2008-12-30 23:28:25 +00:00
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MI.getOperand(1).isReg() &&
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2008-10-03 15:45:36 +00:00
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(MI.getOperand(2).isImm() &&
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2007-12-30 20:49:49 +00:00
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MI.getOperand(2).getImm() == 0)) {
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2007-12-19 07:35:06 +00:00
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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2008-12-27 04:51:36 +00:00
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case SPU::LRr8:
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case SPU::LRr16:
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case SPU::LRr32:
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case SPU::LRf32:
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case SPU::LRr64:
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case SPU::LRf64:
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case SPU::LRr128:
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case SPU::LRv16i8:
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case SPU::LRv8i16:
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case SPU::LRv4i32:
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case SPU::LRv4f32:
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case SPU::LRv2i64:
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case SPU::LRv2f64:
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2007-12-19 20:15:47 +00:00
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case SPU::ORv16i8_i8:
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2007-12-04 22:35:58 +00:00
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case SPU::ORv8i16_i16:
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case SPU::ORv4i32_i32:
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case SPU::ORv2i64_i64:
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case SPU::ORv4f32_f32:
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case SPU::ORv2f64_f64:
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2007-12-19 20:15:47 +00:00
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case SPU::ORi8_v16i8:
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2007-12-04 22:35:58 +00:00
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case SPU::ORi16_v8i16:
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case SPU::ORi32_v4i32:
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case SPU::ORi64_v2i64:
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case SPU::ORf32_v4f32:
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2009-01-06 03:36:14 +00:00
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case SPU::ORf64_v2f64:
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2009-01-21 04:58:48 +00:00
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/*
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2009-01-06 03:36:14 +00:00
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case SPU::ORi128_r64:
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case SPU::ORi128_f64:
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case SPU::ORi128_r32:
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case SPU::ORi128_f32:
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case SPU::ORi128_r16:
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case SPU::ORi128_r8:
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2009-03-16 18:47:25 +00:00
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*/
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2009-01-06 03:36:14 +00:00
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case SPU::ORi128_vec:
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2009-03-16 18:47:25 +00:00
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/*
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2009-01-06 03:36:14 +00:00
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case SPU::ORr64_i128:
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case SPU::ORf64_i128:
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case SPU::ORr32_i128:
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case SPU::ORf32_i128:
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case SPU::ORr16_i128:
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case SPU::ORr8_i128:
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2009-01-21 04:58:48 +00:00
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*/
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2009-03-16 18:47:25 +00:00
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case SPU::ORvec_i128:
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2009-01-21 04:58:48 +00:00
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/*
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2009-01-06 03:36:14 +00:00
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case SPU::ORr16_r32:
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case SPU::ORr8_r32:
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2009-03-16 18:47:25 +00:00
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case SPU::ORf32_r32:
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case SPU::ORr32_f32:
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2009-01-06 03:36:14 +00:00
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case SPU::ORr32_r16:
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case SPU::ORr32_r8:
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case SPU::ORr16_r64:
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case SPU::ORr8_r64:
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case SPU::ORr64_r16:
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case SPU::ORr64_r8:
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2009-01-21 04:58:48 +00:00
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*/
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2009-01-26 03:31:40 +00:00
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case SPU::ORr64_r32:
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case SPU::ORr32_r64:
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2009-01-21 04:58:48 +00:00
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case SPU::ORf32_r32:
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case SPU::ORr32_f32:
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case SPU::ORf64_r64:
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case SPU::ORr64_f64: {
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2008-12-27 04:51:36 +00:00
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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2009-01-03 00:27:53 +00:00
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"invalid SPU OR<type>_<vec> or LR instruction!");
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2008-12-27 04:51:36 +00:00
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if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
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2009-03-17 01:15:45 +00:00
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sourceReg = MI.getOperand(1).getReg();
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2008-12-27 04:51:36 +00:00
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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}
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2007-12-04 22:35:58 +00:00
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case SPU::ORv16i8:
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case SPU::ORv8i16:
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case SPU::ORv4i32:
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2009-01-03 00:27:53 +00:00
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case SPU::ORv2i64:
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case SPU::ORr8:
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case SPU::ORr16:
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2007-12-04 22:35:58 +00:00
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case SPU::ORr32:
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case SPU::ORr64:
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2009-03-16 18:47:25 +00:00
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case SPU::ORr128:
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2007-12-20 00:44:13 +00:00
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case SPU::ORf32:
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case SPU::ORf64:
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2007-12-04 22:35:58 +00:00
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assert(MI.getNumOperands() == 3 &&
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2008-10-03 15:45:36 +00:00
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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MI.getOperand(2).isReg() &&
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2007-12-04 22:35:58 +00:00
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"invalid SPU OR(vec|r32|r64|gprc) instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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}
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return false;
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}
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unsigned
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2008-11-18 19:49:32 +00:00
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SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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2007-12-04 22:35:58 +00:00
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switch (MI->getOpcode()) {
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default: break;
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case SPU::LQDv16i8:
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case SPU::LQDv8i16:
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case SPU::LQDv4i32:
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case SPU::LQDv4f32:
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case SPU::LQDv2f64:
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case SPU::LQDr128:
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case SPU::LQDr64:
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case SPU::LQDr32:
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2008-12-10 00:15:19 +00:00
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case SPU::LQDr16: {
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const MachineOperand MOp1 = MI->getOperand(1);
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const MachineOperand MOp2 = MI->getOperand(2);
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2009-01-03 00:27:53 +00:00
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if (MOp1.isImm() && MOp2.isFI()) {
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FrameIndex = MOp2.getIndex();
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2008-12-10 00:15:19 +00:00
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return MI->getOperand(0).getReg();
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}
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break;
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}
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2007-12-04 22:35:58 +00:00
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}
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return 0;
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}
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unsigned
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2008-11-18 19:49:32 +00:00
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SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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2007-12-04 22:35:58 +00:00
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switch (MI->getOpcode()) {
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default: break;
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case SPU::STQDv16i8:
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case SPU::STQDv8i16:
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case SPU::STQDv4i32:
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case SPU::STQDv4f32:
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case SPU::STQDv2f64:
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case SPU::STQDr128:
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case SPU::STQDr64:
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case SPU::STQDr32:
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case SPU::STQDr16:
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2008-12-10 00:15:19 +00:00
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case SPU::STQDr8: {
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const MachineOperand MOp1 = MI->getOperand(1);
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const MachineOperand MOp2 = MI->getOperand(2);
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2008-12-27 04:51:36 +00:00
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if (MOp1.isImm() && MOp2.isFI()) {
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FrameIndex = MOp2.getIndex();
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2008-12-10 00:15:19 +00:00
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return MI->getOperand(0).getReg();
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}
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break;
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}
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2007-12-04 22:35:58 +00:00
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}
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return 0;
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}
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2007-12-31 06:32:00 +00:00
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2008-08-26 18:03:31 +00:00
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bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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2007-12-31 06:32:00 +00:00
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const
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{
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2008-03-09 20:31:11 +00:00
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// We support cross register class moves for our aliases, such as R3 in any
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// reg class to any other reg class containing R3. This is required because
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// we instruction select bitconvert i64 -> f64 as a noop for example, so our
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// types have no specific meaning.
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2008-12-30 23:28:25 +00:00
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2009-02-12 00:02:55 +00:00
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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2007-12-31 06:32:00 +00:00
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if (DestRC == SPU::R8CRegisterClass) {
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2009-02-12 00:02:55 +00:00
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BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg);
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2007-12-31 06:32:00 +00:00
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} else if (DestRC == SPU::R16CRegisterClass) {
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2009-02-12 00:02:55 +00:00
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BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg);
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2007-12-31 06:32:00 +00:00
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} else if (DestRC == SPU::R32CRegisterClass) {
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2009-02-12 00:02:55 +00:00
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BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg);
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2007-12-31 06:32:00 +00:00
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} else if (DestRC == SPU::R32FPRegisterClass) {
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2009-02-12 00:02:55 +00:00
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BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg);
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2007-12-31 06:32:00 +00:00
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} else if (DestRC == SPU::R64CRegisterClass) {
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2009-02-12 00:02:55 +00:00
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BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg);
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2007-12-31 06:32:00 +00:00
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} else if (DestRC == SPU::R64FPRegisterClass) {
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2009-02-12 00:02:55 +00:00
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|
|
BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg);
|
2009-01-02 20:52:08 +00:00
|
|
|
} else if (DestRC == SPU::GPRCRegisterClass) {
|
2009-02-12 00:02:55 +00:00
|
|
|
BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg);
|
2009-01-02 20:52:08 +00:00
|
|
|
} else if (DestRC == SPU::VECREGRegisterClass) {
|
2009-02-12 00:02:55 +00:00
|
|
|
BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
|
2007-12-31 06:32:00 +00:00
|
|
|
} else {
|
2008-08-26 18:03:31 +00:00
|
|
|
// Attempt to copy unknown/unsupported register class!
|
|
|
|
return false;
|
2007-12-31 06:32:00 +00:00
|
|
|
}
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2008-08-26 18:03:31 +00:00
|
|
|
return true;
|
2007-12-31 06:32:00 +00:00
|
|
|
}
|
2008-01-01 21:11:32 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
|
|
|
const TargetRegisterClass *RC) const
|
|
|
|
{
|
2008-01-07 02:48:55 +00:00
|
|
|
unsigned opc;
|
2008-12-10 00:15:19 +00:00
|
|
|
bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
|
2008-01-01 21:11:32 +00:00
|
|
|
if (RC == SPU::GPRCRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R64CRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R64FPRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R32CRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R32FPRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R16CRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
|
|
|
|
} else if (RC == SPU::R8CRegisterClass) {
|
|
|
|
opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
|
2008-12-27 04:51:36 +00:00
|
|
|
} else if (RC == SPU::VECREGRegisterClass) {
|
|
|
|
opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
|
2008-01-01 21:11:32 +00:00
|
|
|
} else {
|
|
|
|
assert(0 && "Unknown regclass!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
2009-02-12 00:02:55 +00:00
|
|
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
|
|
|
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
|
|
|
addFrameReference(BuildMI(MBB, MI, DL, get(opc))
|
2009-05-13 21:33:08 +00:00
|
|
|
.addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
|
2008-01-01 21:11:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
2009-02-12 00:02:55 +00:00
|
|
|
bool isKill,
|
|
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
2008-01-01 21:11:32 +00:00
|
|
|
cerr << "storeRegToAddr() invoked!\n";
|
|
|
|
abort();
|
|
|
|
|
2008-10-03 15:45:36 +00:00
|
|
|
if (Addr[0].isFI()) {
|
2008-01-01 21:11:32 +00:00
|
|
|
/* do what storeRegToStackSlot does here */
|
|
|
|
} else {
|
|
|
|
unsigned Opc = 0;
|
|
|
|
if (RC == SPU::GPRCRegisterClass) {
|
|
|
|
/* Opc = PPC::STW; */
|
|
|
|
} else if (RC == SPU::R16CRegisterClass) {
|
|
|
|
/* Opc = PPC::STD; */
|
|
|
|
} else if (RC == SPU::R32CRegisterClass) {
|
|
|
|
/* Opc = PPC::STFD; */
|
|
|
|
} else if (RC == SPU::R32FPRegisterClass) {
|
|
|
|
/* Opc = PPC::STFD; */
|
|
|
|
} else if (RC == SPU::R64FPRegisterClass) {
|
|
|
|
/* Opc = PPC::STFS; */
|
|
|
|
} else if (RC == SPU::VECREGRegisterClass) {
|
|
|
|
/* Opc = PPC::STVX; */
|
|
|
|
} else {
|
|
|
|
assert(0 && "Unknown regclass!");
|
|
|
|
abort();
|
|
|
|
}
|
2009-02-12 23:08:38 +00:00
|
|
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
|
2009-05-13 21:33:08 +00:00
|
|
|
.addReg(SrcReg, getKillRegState(isKill));
|
2009-02-18 05:45:50 +00:00
|
|
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
|
|
MIB.addOperand(Addr[i]);
|
2008-01-01 21:11:32 +00:00
|
|
|
NewMIs.push_back(MIB);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
unsigned DestReg, int FrameIdx,
|
|
|
|
const TargetRegisterClass *RC) const
|
|
|
|
{
|
2008-01-07 02:48:55 +00:00
|
|
|
unsigned opc;
|
2008-12-10 00:15:19 +00:00
|
|
|
bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
|
2008-01-01 21:11:32 +00:00
|
|
|
if (RC == SPU::GPRCRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R64CRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R64FPRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R32CRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R32FPRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
|
2008-01-01 21:11:32 +00:00
|
|
|
} else if (RC == SPU::R16CRegisterClass) {
|
2008-12-10 00:15:19 +00:00
|
|
|
opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
|
|
|
|
} else if (RC == SPU::R8CRegisterClass) {
|
|
|
|
opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
|
2008-12-27 04:51:36 +00:00
|
|
|
} else if (RC == SPU::VECREGRegisterClass) {
|
|
|
|
opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
|
2008-01-01 21:11:32 +00:00
|
|
|
} else {
|
|
|
|
assert(0 && "Unknown regclass in loadRegFromStackSlot!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
2009-02-12 00:02:55 +00:00
|
|
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
|
|
|
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
|
|
|
addFrameReference(BuildMI(MBB, MI, DL, get(opc)).addReg(DestReg), FrameIdx);
|
2008-01-01 21:11:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*!
|
|
|
|
\note We are really pessimistic here about what kind of a load we're doing.
|
|
|
|
*/
|
|
|
|
void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
2008-12-10 00:15:19 +00:00
|
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs)
|
2008-01-01 21:11:32 +00:00
|
|
|
const {
|
|
|
|
cerr << "loadRegToAddr() invoked!\n";
|
|
|
|
abort();
|
|
|
|
|
2008-10-03 15:45:36 +00:00
|
|
|
if (Addr[0].isFI()) {
|
2008-01-01 21:11:32 +00:00
|
|
|
/* do what loadRegFromStackSlot does here... */
|
|
|
|
} else {
|
|
|
|
unsigned Opc = 0;
|
|
|
|
if (RC == SPU::R8CRegisterClass) {
|
|
|
|
/* do brilliance here */
|
|
|
|
} else if (RC == SPU::R16CRegisterClass) {
|
|
|
|
/* Opc = PPC::LWZ; */
|
|
|
|
} else if (RC == SPU::R32CRegisterClass) {
|
|
|
|
/* Opc = PPC::LD; */
|
|
|
|
} else if (RC == SPU::R32FPRegisterClass) {
|
|
|
|
/* Opc = PPC::LFD; */
|
|
|
|
} else if (RC == SPU::R64FPRegisterClass) {
|
|
|
|
/* Opc = PPC::LFS; */
|
|
|
|
} else if (RC == SPU::VECREGRegisterClass) {
|
|
|
|
/* Opc = PPC::LVX; */
|
|
|
|
} else if (RC == SPU::GPRCRegisterClass) {
|
|
|
|
/* Opc = something else! */
|
|
|
|
} else {
|
|
|
|
assert(0 && "Unknown regclass!");
|
|
|
|
abort();
|
|
|
|
}
|
2009-02-12 23:08:38 +00:00
|
|
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
|
2009-02-18 05:45:50 +00:00
|
|
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
|
|
MIB.addOperand(Addr[i]);
|
2008-01-01 21:11:32 +00:00
|
|
|
NewMIs.push_back(MIB);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-01-03 00:27:53 +00:00
|
|
|
//! Return true if the specified load or store can be folded
|
|
|
|
bool
|
|
|
|
SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
|
|
|
|
const SmallVectorImpl<unsigned> &Ops) const {
|
|
|
|
if (Ops.size() != 1) return false;
|
|
|
|
|
|
|
|
// Make sure this is a reg-reg copy.
|
|
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
|
|
|
|
switch (Opc) {
|
|
|
|
case SPU::ORv16i8:
|
|
|
|
case SPU::ORv8i16:
|
|
|
|
case SPU::ORv4i32:
|
|
|
|
case SPU::ORv2i64:
|
|
|
|
case SPU::ORr8:
|
|
|
|
case SPU::ORr16:
|
|
|
|
case SPU::ORr32:
|
|
|
|
case SPU::ORr64:
|
|
|
|
case SPU::ORf32:
|
|
|
|
case SPU::ORf64:
|
|
|
|
if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
|
|
|
|
return true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-01-07 01:35:02 +00:00
|
|
|
/// foldMemoryOperand - SPU, like PPC, can only fold spills into
|
|
|
|
/// copy instructions, turning them into load/store instructions.
|
|
|
|
MachineInstr *
|
2008-12-03 18:43:12 +00:00
|
|
|
SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
|
|
|
MachineInstr *MI,
|
|
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
|
|
int FrameIndex) const
|
2008-01-07 01:35:02 +00:00
|
|
|
{
|
2009-01-03 00:27:53 +00:00
|
|
|
if (Ops.size() != 1) return 0;
|
2008-01-07 01:35:02 +00:00
|
|
|
|
|
|
|
unsigned OpNum = Ops[0];
|
|
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
MachineInstr *NewMI = 0;
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2009-01-03 00:27:53 +00:00
|
|
|
switch (Opc) {
|
|
|
|
case SPU::ORv16i8:
|
|
|
|
case SPU::ORv8i16:
|
|
|
|
case SPU::ORv4i32:
|
|
|
|
case SPU::ORv2i64:
|
|
|
|
case SPU::ORr8:
|
|
|
|
case SPU::ORr16:
|
|
|
|
case SPU::ORr32:
|
|
|
|
case SPU::ORr64:
|
|
|
|
case SPU::ORf32:
|
|
|
|
case SPU::ORf64:
|
2008-01-07 01:35:02 +00:00
|
|
|
if (OpNum == 0) { // move -> store
|
|
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
2008-07-03 09:09:37 +00:00
|
|
|
bool isKill = MI->getOperand(1).isKill();
|
2008-01-07 01:35:02 +00:00
|
|
|
if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
|
2009-02-12 00:02:55 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
|
|
|
|
get(SPU::STQDr32));
|
2009-01-03 00:27:53 +00:00
|
|
|
|
2009-05-13 21:33:08 +00:00
|
|
|
MIB.addReg(InReg, getKillRegState(isKill));
|
2009-01-03 00:27:53 +00:00
|
|
|
NewMI = addFrameReference(MIB, FrameIndex);
|
2008-01-07 01:35:02 +00:00
|
|
|
}
|
|
|
|
} else { // move -> load
|
|
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
2008-07-03 09:09:37 +00:00
|
|
|
bool isDead = MI->getOperand(0).isDead();
|
2009-02-12 00:02:55 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
|
2009-01-03 00:27:53 +00:00
|
|
|
|
2009-05-13 21:33:08 +00:00
|
|
|
MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead));
|
2008-07-03 09:09:37 +00:00
|
|
|
Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
|
|
|
|
? SPU::STQDr32 : SPU::STQXr32;
|
2009-01-03 00:27:53 +00:00
|
|
|
NewMI = addFrameReference(MIB, FrameIndex);
|
|
|
|
break;
|
|
|
|
}
|
2008-01-07 01:35:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return NewMI;
|
|
|
|
}
|
|
|
|
|
2008-12-10 00:15:19 +00:00
|
|
|
//! Branch analysis
|
2009-01-02 20:52:08 +00:00
|
|
|
/*!
|
2008-12-10 00:15:19 +00:00
|
|
|
\note This code was kiped from PPC. There may be more branch analysis for
|
|
|
|
CellSPU than what's currently done here.
|
|
|
|
*/
|
|
|
|
bool
|
|
|
|
SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
2009-01-26 03:37:41 +00:00
|
|
|
MachineBasicBlock *&FBB,
|
2009-02-09 07:14:22 +00:00
|
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
|
|
bool AllowModify) const {
|
2008-12-10 00:15:19 +00:00
|
|
|
// If the block has no terminators, it just falls into the block after it.
|
|
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
|
|
if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Get the last instruction in the block.
|
|
|
|
MachineInstr *LastInst = I;
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2008-12-10 00:15:19 +00:00
|
|
|
// If there is only one terminator instruction, process it.
|
|
|
|
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
|
|
|
|
if (isUncondBranch(LastInst)) {
|
|
|
|
TBB = LastInst->getOperand(0).getMBB();
|
|
|
|
return false;
|
|
|
|
} else if (isCondBranch(LastInst)) {
|
|
|
|
// Block ends with fall-through condbranch.
|
|
|
|
TBB = LastInst->getOperand(1).getMBB();
|
2009-01-02 20:52:08 +00:00
|
|
|
DEBUG(cerr << "Pushing LastInst: ");
|
|
|
|
DEBUG(LastInst->dump());
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
|
2008-12-10 00:15:19 +00:00
|
|
|
Cond.push_back(LastInst->getOperand(0));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// Otherwise, don't know what this is.
|
|
|
|
return true;
|
|
|
|
}
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2008-12-10 00:15:19 +00:00
|
|
|
// Get the instruction before it if it's a terminator.
|
|
|
|
MachineInstr *SecondLastInst = I;
|
|
|
|
|
|
|
|
// If there are three terminators, we don't know what sort of block this is.
|
|
|
|
if (SecondLastInst && I != MBB.begin() &&
|
|
|
|
isUnpredicatedTerminator(--I))
|
|
|
|
return true;
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2008-12-10 00:15:19 +00:00
|
|
|
// If the block ends with a conditional and unconditional branch, handle it.
|
|
|
|
if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
|
|
|
|
TBB = SecondLastInst->getOperand(1).getMBB();
|
2009-01-02 20:52:08 +00:00
|
|
|
DEBUG(cerr << "Pushing SecondLastInst: ");
|
|
|
|
DEBUG(SecondLastInst->dump());
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
|
2008-12-10 00:15:19 +00:00
|
|
|
Cond.push_back(SecondLastInst->getOperand(0));
|
|
|
|
FBB = LastInst->getOperand(0).getMBB();
|
|
|
|
return false;
|
|
|
|
}
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2008-12-10 00:15:19 +00:00
|
|
|
// If the block ends with two unconditional branches, handle it. The second
|
|
|
|
// one is not executed, so remove it.
|
|
|
|
if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
|
|
|
|
TBB = SecondLastInst->getOperand(0).getMBB();
|
|
|
|
I = LastInst;
|
2009-02-09 07:14:22 +00:00
|
|
|
if (AllowModify)
|
|
|
|
I->eraseFromParent();
|
2008-12-10 00:15:19 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, can't handle this.
|
|
|
|
return true;
|
|
|
|
}
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2008-12-10 00:15:19 +00:00
|
|
|
unsigned
|
|
|
|
SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
|
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
|
|
if (I == MBB.begin())
|
|
|
|
return 0;
|
|
|
|
--I;
|
|
|
|
if (!isCondBranch(I) && !isUncondBranch(I))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
// Remove the first branch.
|
2009-01-02 20:52:08 +00:00
|
|
|
DEBUG(cerr << "Removing branch: ");
|
|
|
|
DEBUG(I->dump());
|
2008-12-10 00:15:19 +00:00
|
|
|
I->eraseFromParent();
|
|
|
|
I = MBB.end();
|
|
|
|
if (I == MBB.begin())
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
--I;
|
2009-01-02 20:52:08 +00:00
|
|
|
if (!(isCondBranch(I) || isUncondBranch(I)))
|
2008-12-10 00:15:19 +00:00
|
|
|
return 1;
|
|
|
|
|
|
|
|
// Remove the second branch.
|
2009-01-02 20:52:08 +00:00
|
|
|
DEBUG(cerr << "Removing second branch: ");
|
|
|
|
DEBUG(I->dump());
|
2008-12-10 00:15:19 +00:00
|
|
|
I->eraseFromParent();
|
|
|
|
return 2;
|
|
|
|
}
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2008-12-10 00:15:19 +00:00
|
|
|
unsigned
|
|
|
|
SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
2009-01-26 03:37:41 +00:00
|
|
|
MachineBasicBlock *FBB,
|
|
|
|
const SmallVectorImpl<MachineOperand> &Cond) const {
|
2009-02-13 02:30:42 +00:00
|
|
|
// FIXME this should probably have a DebugLoc argument
|
|
|
|
DebugLoc dl = DebugLoc::getUnknownLoc();
|
2008-12-10 00:15:19 +00:00
|
|
|
// Shouldn't be a fall through.
|
|
|
|
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
2008-12-30 23:28:25 +00:00
|
|
|
assert((Cond.size() == 2 || Cond.size() == 0) &&
|
2008-12-10 00:15:19 +00:00
|
|
|
"SPU branch conditions have two components!");
|
2008-12-30 23:28:25 +00:00
|
|
|
|
2008-12-10 00:15:19 +00:00
|
|
|
// One-way branch.
|
|
|
|
if (FBB == 0) {
|
2009-01-02 20:52:08 +00:00
|
|
|
if (Cond.empty()) {
|
|
|
|
// Unconditional branch
|
2009-02-13 02:30:42 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR));
|
2009-01-02 20:52:08 +00:00
|
|
|
MIB.addMBB(TBB);
|
|
|
|
|
|
|
|
DEBUG(cerr << "Inserted one-way uncond branch: ");
|
|
|
|
DEBUG((*MIB).dump());
|
|
|
|
} else {
|
|
|
|
// Conditional branch
|
2009-02-13 02:30:42 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
|
2009-01-02 20:52:08 +00:00
|
|
|
MIB.addReg(Cond[1].getReg()).addMBB(TBB);
|
|
|
|
|
|
|
|
DEBUG(cerr << "Inserted one-way cond branch: ");
|
|
|
|
DEBUG((*MIB).dump());
|
2008-12-10 00:15:19 +00:00
|
|
|
}
|
|
|
|
return 1;
|
2009-01-02 20:52:08 +00:00
|
|
|
} else {
|
2009-02-13 02:30:42 +00:00
|
|
|
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
|
|
|
|
MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR));
|
2009-01-02 20:52:08 +00:00
|
|
|
|
|
|
|
// Two-way Conditional Branch.
|
|
|
|
MIB.addReg(Cond[1].getReg()).addMBB(TBB);
|
|
|
|
MIB2.addMBB(FBB);
|
|
|
|
|
|
|
|
DEBUG(cerr << "Inserted conditional branch: ");
|
|
|
|
DEBUG((*MIB).dump());
|
|
|
|
DEBUG(cerr << "part 2: ");
|
|
|
|
DEBUG((*MIB2).dump());
|
|
|
|
return 2;
|
2008-12-10 00:15:19 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-01-03 00:27:53 +00:00
|
|
|
bool
|
|
|
|
SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
|
|
|
|
return (!MBB.empty() && isUncondBranch(&MBB.back()));
|
|
|
|
}
|
|
|
|
//! Reverses a branch's condition, returning false on success.
|
|
|
|
bool
|
|
|
|
SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
|
|
|
|
const {
|
|
|
|
// Pretty brainless way of inverting the condition, but it works, considering
|
|
|
|
// there are only two conditions...
|
|
|
|
static struct {
|
|
|
|
unsigned Opc; //! The incoming opcode
|
|
|
|
unsigned RevCondOpc; //! The reversed condition opcode
|
|
|
|
} revconds[] = {
|
|
|
|
{ SPU::BRNZr32, SPU::BRZr32 },
|
|
|
|
{ SPU::BRNZv4i32, SPU::BRZv4i32 },
|
|
|
|
{ SPU::BRZr32, SPU::BRNZr32 },
|
|
|
|
{ SPU::BRZv4i32, SPU::BRNZv4i32 },
|
|
|
|
{ SPU::BRHNZr16, SPU::BRHZr16 },
|
|
|
|
{ SPU::BRHNZv8i16, SPU::BRHZv8i16 },
|
|
|
|
{ SPU::BRHZr16, SPU::BRHNZr16 },
|
|
|
|
{ SPU::BRHZv8i16, SPU::BRHNZv8i16 }
|
|
|
|
};
|
|
|
|
|
|
|
|
unsigned Opc = unsigned(Cond[0].getImm());
|
|
|
|
// Pretty dull mapping between the two conditions that SPU can generate:
|
2009-01-07 23:07:29 +00:00
|
|
|
for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
|
2009-01-03 00:27:53 +00:00
|
|
|
if (revconds[i].Opc == Opc) {
|
|
|
|
Cond[0].setImm(revconds[i].RevCondOpc);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2008-12-10 00:15:19 +00:00
|
|
|
|
2009-01-03 00:27:53 +00:00
|
|
|
return true;
|
|
|
|
}
|