2005-10-16 05:39:50 +00:00
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//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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2005-04-21 23:30:14 +00:00
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//
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2004-06-21 16:55:25 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-06-21 16:55:25 +00:00
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//===----------------------------------------------------------------------===//
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2005-04-21 23:30:14 +00:00
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//
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2005-08-15 23:47:04 +00:00
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// Top-level implementation for the PowerPC target.
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2004-06-21 16:55:25 +00:00
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//
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//===----------------------------------------------------------------------===//
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2005-10-14 23:51:18 +00:00
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#include "PPC.h"
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2009-08-22 20:48:53 +00:00
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#include "PPCMCAsmInfo.h"
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2005-10-14 23:59:06 +00:00
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#include "PPCTargetMachine.h"
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2004-06-21 16:55:25 +00:00
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#include "llvm/PassManager.h"
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2010-11-15 08:49:58 +00:00
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#include "llvm/MC/MCStreamer.h"
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2008-07-31 18:13:12 +00:00
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#include "llvm/Target/TargetOptions.h"
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2009-07-25 06:49:55 +00:00
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#include "llvm/Target/TargetRegistry.h"
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2009-07-14 20:18:05 +00:00
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#include "llvm/Support/FormattedStream.h"
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2004-06-21 16:55:25 +00:00
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using namespace llvm;
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2010-03-20 22:36:22 +00:00
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static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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2009-08-12 07:22:17 +00:00
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Triple TheTriple(TT);
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2009-08-13 17:03:38 +00:00
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bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
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2009-08-12 07:22:17 +00:00
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if (TheTriple.getOS() == Triple::Darwin)
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2009-08-22 21:03:30 +00:00
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return new PPCMCAsmInfoDarwin(isPPC64);
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2009-08-22 20:48:53 +00:00
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return new PPCLinuxMCAsmInfo(isPPC64);
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2009-08-12 07:22:17 +00:00
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}
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2010-11-15 08:49:58 +00:00
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// This is duplicated code. Refactor this.
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static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
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MCContext &Ctx, TargetAsmBackend &TAB,
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raw_ostream &OS,
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MCCodeEmitter *Emitter,
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bool RelaxAll) {
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switch (Triple(TT).getOS()) {
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case Triple::Darwin:
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return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
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default:
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return NULL;
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}
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}
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2009-07-25 06:49:55 +00:00
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
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RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
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2009-08-12 07:22:17 +00:00
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2009-08-22 20:48:53 +00:00
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RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo);
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RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo);
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Implement a basic MCCodeEmitter for PPC. This doesn't handle
fixups yet, and doesn't handle actually encoding operand values,
but this is enough for llc -show-mc-encoding to show the base
instruction encoding information, e.g.:
mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6]
stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00]
stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00]
Ltmp0:
lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00]
cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00]
beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 04:16:32 +00:00
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// Register the MC Code Emitter
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TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
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TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
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2010-11-15 08:49:58 +00:00
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// Register the asm backend.
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TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
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TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
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// Register the object streamer.
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TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
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TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
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2009-07-25 06:49:55 +00:00
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}
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2009-06-16 20:12:29 +00:00
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2006-09-07 23:39:26 +00:00
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2009-08-11 20:42:37 +00:00
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PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
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2009-07-15 20:24:03 +00:00
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const std::string &FS, bool is64Bit)
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2009-08-11 20:42:37 +00:00
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: LLVMTargetMachine(T, TT),
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2009-08-02 23:37:13 +00:00
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Subtarget(TT, FS, is64Bit),
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2006-06-17 00:01:04 +00:00
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DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
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2010-11-15 00:06:54 +00:00
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FrameInfo(Subtarget), JITInfo(*this, is64Bit),
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2010-05-11 17:31:57 +00:00
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TLInfo(*this), TSInfo(*this),
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2010-02-02 19:23:55 +00:00
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InstrItins(Subtarget.getInstrItineraryData()) {
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2006-06-16 01:37:27 +00:00
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2008-02-20 11:22:39 +00:00
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if (getRelocationModel() == Reloc::Default) {
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2006-02-22 20:19:42 +00:00
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if (Subtarget.isDarwin())
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setRelocationModel(Reloc::DynamicNoPIC);
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else
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2006-12-21 20:26:09 +00:00
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setRelocationModel(Reloc::Static);
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2008-02-20 11:22:39 +00:00
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}
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2005-10-16 05:39:50 +00:00
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}
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2007-05-22 17:14:46 +00:00
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/// Override this for PowerPC. Tail merging happily breaks up instruction issue
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/// groups, which typically degrades performance.
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2007-11-19 20:46:23 +00:00
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bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
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2007-05-22 17:14:46 +00:00
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2009-08-02 23:37:13 +00:00
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PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
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2009-07-15 20:24:03 +00:00
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const std::string &FS)
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2009-08-02 23:37:13 +00:00
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: PPCTargetMachine(T, TT, FS, false) {
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2006-06-16 01:37:27 +00:00
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}
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2009-08-02 23:37:13 +00:00
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PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
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2009-07-15 20:24:03 +00:00
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const std::string &FS)
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2009-08-02 23:37:13 +00:00
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: PPCTargetMachine(T, TT, FS, true) {
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2006-06-16 01:37:27 +00:00
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}
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2004-08-11 07:40:04 +00:00
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2006-09-04 04:14:57 +00:00
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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2004-08-11 07:40:04 +00:00
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2009-04-29 23:29:43 +00:00
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bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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2005-08-17 19:33:30 +00:00
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// Install an instruction selector.
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2006-01-12 01:46:07 +00:00
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PM.add(createPPCISelDag(*this));
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2006-09-04 04:14:57 +00:00
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return false;
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}
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2004-08-11 07:40:04 +00:00
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2009-04-29 23:29:43 +00:00
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bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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2006-09-04 04:14:57 +00:00
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// Must run branch selection immediately preceding the asm printer.
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2004-08-11 07:40:04 +00:00
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PM.add(createPPCBranchSelectionPass());
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return false;
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}
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2009-05-30 20:51:52 +00:00
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bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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2009-07-15 22:33:19 +00:00
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JITCodeEmitter &JCE) {
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2009-05-30 20:51:52 +00:00
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// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
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// FIXME: This should be moved to TargetJITInfo!!
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if (Subtarget.isPPC64()) {
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// We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
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// instructions to materialize arbitrary global variable + function +
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// constant pool addresses.
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setRelocationModel(Reloc::PIC_);
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// Temporary workaround for the inability of PPC64 JIT to handle jump
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// tables.
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DisableJumpTables = true;
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} else {
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setRelocationModel(Reloc::Static);
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}
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// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
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// writing?
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Subtarget.SetJITMode();
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCJITCodeEmitterPass(*this, JCE));
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return false;
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}
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