2005-10-16 05:39:50 +00:00
|
|
|
//===- PPCRegisterInfo.h - PowerPC Register Information Impl -----*- C++ -*-==//
|
2005-04-21 23:30:14 +00:00
|
|
|
//
|
2004-08-17 04:55:41 +00:00
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-04-21 23:30:14 +00:00
|
|
|
//
|
2004-08-17 04:55:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
2008-02-10 18:45:23 +00:00
|
|
|
// This file contains the PowerPC implementation of the TargetRegisterInfo
|
|
|
|
// class.
|
2004-08-17 04:55:41 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef POWERPC32_REGISTERINFO_H
|
|
|
|
#define POWERPC32_REGISTERINFO_H
|
|
|
|
|
2005-10-14 23:51:18 +00:00
|
|
|
#include "PPC.h"
|
2005-10-14 23:37:35 +00:00
|
|
|
#include "PPCGenRegisterInfo.h.inc"
|
2004-08-17 04:55:41 +00:00
|
|
|
#include <map>
|
|
|
|
|
|
|
|
namespace llvm {
|
2006-07-11 00:48:23 +00:00
|
|
|
class PPCSubtarget;
|
2006-11-27 23:37:22 +00:00
|
|
|
class TargetInstrInfo;
|
2004-08-17 04:55:41 +00:00
|
|
|
class Type;
|
|
|
|
|
2005-10-16 05:39:50 +00:00
|
|
|
class PPCRegisterInfo : public PPCGenRegisterInfo {
|
2004-08-17 04:55:41 +00:00
|
|
|
std::map<unsigned, unsigned> ImmToIdxMap;
|
2006-07-11 00:48:23 +00:00
|
|
|
const PPCSubtarget &Subtarget;
|
2006-11-13 23:36:35 +00:00
|
|
|
const TargetInstrInfo &TII;
|
2004-08-17 04:55:41 +00:00
|
|
|
public:
|
2006-11-13 23:36:35 +00:00
|
|
|
PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
|
2006-04-17 21:07:20 +00:00
|
|
|
|
|
|
|
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
|
|
|
/// PPC::F14, return the number that it corresponds to (e.g. 14).
|
|
|
|
static unsigned getRegisterNumbering(unsigned RegEnum);
|
2004-08-17 04:55:41 +00:00
|
|
|
|
2009-02-06 17:43:24 +00:00
|
|
|
/// getPointerRegClass - Return the register class to use to hold pointers.
|
|
|
|
/// This is used for addressing modes.
|
|
|
|
virtual const TargetRegisterClass *getPointerRegClass() const;
|
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
/// Code Generation virtual methods...
|
2007-07-14 14:06:15 +00:00
|
|
|
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
|
2006-05-18 00:12:58 +00:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
const TargetRegisterClass* const*
|
|
|
|
getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
|
2006-05-18 00:12:58 +00:00
|
|
|
|
2007-02-19 21:49:54 +00:00
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const;
|
|
|
|
|
2007-01-25 22:25:04 +00:00
|
|
|
/// targetHandlesStackFrameRounding - Returns true if the target is
|
|
|
|
/// responsible for rounding up the stack frame (probably at emitPrologue
|
|
|
|
/// time).
|
|
|
|
bool targetHandlesStackFrameRounding() const { return true; }
|
|
|
|
|
2008-03-03 22:19:16 +00:00
|
|
|
/// requiresRegisterScavenging - We require a register scavenger.
|
|
|
|
/// FIXME (64-bit): Should be inlined.
|
|
|
|
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
|
|
|
|
2007-01-23 00:57:47 +00:00
|
|
|
bool hasFP(const MachineFunction &MF) const;
|
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
|
|
MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
|
2008-03-03 22:19:16 +00:00
|
|
|
void lowerDynamicAlloc(MachineBasicBlock::iterator II,
|
|
|
|
int SPAdj, RegScavenger *RS) const;
|
|
|
|
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex,
|
|
|
|
int SPAdj, RegScavenger *RS) const;
|
2007-02-28 00:21:17 +00:00
|
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
2007-05-01 09:13:03 +00:00
|
|
|
int SPAdj, RegScavenger *RS = NULL) const;
|
2004-08-17 04:55:41 +00:00
|
|
|
|
2006-11-16 22:43:37 +00:00
|
|
|
/// determineFrameLayout - Determine the size of the frame and maximum call
|
|
|
|
/// frame size.
|
|
|
|
void determineFrameLayout(MachineFunction &MF) const;
|
|
|
|
|
2007-03-06 10:05:14 +00:00
|
|
|
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
|
|
RegScavenger *RS = NULL) const;
|
2004-08-17 04:55:41 +00:00
|
|
|
void emitPrologue(MachineFunction &MF) const;
|
|
|
|
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
2006-03-23 18:12:57 +00:00
|
|
|
|
2006-03-28 13:48:33 +00:00
|
|
|
// Debug information queries.
|
2006-04-07 16:34:46 +00:00
|
|
|
unsigned getRARegister() const;
|
2006-03-28 13:48:33 +00:00
|
|
|
unsigned getFrameRegister(MachineFunction &MF) const;
|
2007-01-24 18:45:13 +00:00
|
|
|
void getInitialFrameState(std::vector<MachineMove> &Moves) const;
|
2007-02-21 22:54:50 +00:00
|
|
|
|
|
|
|
// Exception handling queries.
|
|
|
|
unsigned getEHExceptionRegister() const;
|
|
|
|
unsigned getEHHandlerRegister() const;
|
2007-11-11 19:50:10 +00:00
|
|
|
|
2007-11-13 19:13:01 +00:00
|
|
|
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
|
2004-08-17 04:55:41 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end namespace llvm
|
|
|
|
|
|
|
|
#endif
|