2009-08-05 23:12:45 +00:00
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//===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "neon-prealloc"
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#include "ARM.h"
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#include "ARMInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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namespace {
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2009-10-25 06:33:48 +00:00
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class NEONPreAllocPass : public MachineFunctionPass {
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2009-08-05 23:12:45 +00:00
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const TargetInstrInfo *TII;
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public:
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static char ID;
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NEONPreAllocPass() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "NEON register pre-allocation pass";
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}
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private:
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bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
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};
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char NEONPreAllocPass::ID = 0;
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}
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2009-10-07 17:24:55 +00:00
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static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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unsigned &Offset, unsigned &Stride) {
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// Default to unit stride with no offset.
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Stride = 1;
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Offset = 0;
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2009-08-05 23:12:45 +00:00
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switch (Opcode) {
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default:
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break;
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case ARM::VLD2d8:
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case ARM::VLD2d16:
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case ARM::VLD2d32:
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2009-10-07 22:57:01 +00:00
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case ARM::VLD2d64:
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2009-09-01 04:26:28 +00:00
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case ARM::VLD2LNd8:
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case ARM::VLD2LNd16:
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case ARM::VLD2LNd32:
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2009-08-05 23:12:45 +00:00
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FirstOpnd = 0;
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NumRegs = 2;
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return true;
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2009-10-08 18:56:10 +00:00
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2009-10-08 22:27:33 +00:00
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case ARM::VLD2q8:
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case ARM::VLD2q16:
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case ARM::VLD2q32:
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FirstOpnd = 0;
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NumRegs = 4;
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return true;
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2009-10-08 18:56:10 +00:00
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case ARM::VLD2LNq16a:
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case ARM::VLD2LNq32a:
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FirstOpnd = 0;
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NumRegs = 2;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD2LNq16b:
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case ARM::VLD2LNq32b:
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FirstOpnd = 0;
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NumRegs = 2;
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Offset = 1;
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Stride = 2;
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return true;
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2009-08-05 23:12:45 +00:00
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case ARM::VLD3d8:
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case ARM::VLD3d16:
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case ARM::VLD3d32:
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2009-10-07 23:39:57 +00:00
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case ARM::VLD3d64:
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2009-09-01 04:26:28 +00:00
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case ARM::VLD3LNd8:
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case ARM::VLD3LNd16:
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case ARM::VLD3LNd32:
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2009-08-05 23:12:45 +00:00
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FirstOpnd = 0;
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NumRegs = 3;
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return true;
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2009-10-07 17:24:55 +00:00
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case ARM::VLD3q8a:
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case ARM::VLD3q16a:
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case ARM::VLD3q32a:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD3q8b:
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case ARM::VLD3q16b:
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case ARM::VLD3q32b:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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2009-10-08 22:27:33 +00:00
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case ARM::VLD3LNq16a:
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case ARM::VLD3LNq32a:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD3LNq16b:
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case ARM::VLD3LNq32b:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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2009-08-05 23:12:45 +00:00
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case ARM::VLD4d8:
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case ARM::VLD4d16:
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case ARM::VLD4d32:
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2009-10-07 23:54:04 +00:00
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case ARM::VLD4d64:
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2009-09-01 04:26:28 +00:00
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case ARM::VLD4LNd8:
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case ARM::VLD4LNd16:
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case ARM::VLD4LNd32:
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2009-08-05 23:12:45 +00:00
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FirstOpnd = 0;
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NumRegs = 4;
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return true;
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2009-08-06 18:47:44 +00:00
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2009-10-07 18:09:32 +00:00
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case ARM::VLD4q8a:
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case ARM::VLD4q16a:
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case ARM::VLD4q32a:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD4q8b:
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case ARM::VLD4q16b:
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case ARM::VLD4q32b:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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2009-10-08 22:53:57 +00:00
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case ARM::VLD4LNq16a:
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case ARM::VLD4LNq32a:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD4LNq16b:
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case ARM::VLD4LNq32b:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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2009-08-06 18:47:44 +00:00
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case ARM::VST2d8:
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case ARM::VST2d16:
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case ARM::VST2d32:
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2009-10-08 00:21:01 +00:00
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case ARM::VST2d64:
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2009-09-01 18:51:56 +00:00
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case ARM::VST2LNd8:
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case ARM::VST2LNd16:
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case ARM::VST2LNd32:
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2009-08-06 18:47:44 +00:00
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FirstOpnd = 3;
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NumRegs = 2;
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return true;
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2009-10-07 18:47:39 +00:00
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case ARM::VST2q8:
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case ARM::VST2q16:
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case ARM::VST2q32:
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FirstOpnd = 3;
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NumRegs = 4;
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return true;
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2009-10-08 23:38:24 +00:00
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case ARM::VST2LNq16a:
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case ARM::VST2LNq32a:
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FirstOpnd = 3;
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NumRegs = 2;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST2LNq16b:
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case ARM::VST2LNq32b:
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FirstOpnd = 3;
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NumRegs = 2;
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Offset = 1;
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Stride = 2;
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return true;
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2009-08-06 18:47:44 +00:00
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case ARM::VST3d8:
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case ARM::VST3d16:
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case ARM::VST3d32:
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2009-10-08 00:28:28 +00:00
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case ARM::VST3d64:
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2009-09-01 18:51:56 +00:00
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case ARM::VST3LNd8:
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case ARM::VST3LNd16:
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case ARM::VST3LNd32:
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2009-08-06 18:47:44 +00:00
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FirstOpnd = 3;
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NumRegs = 3;
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return true;
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2009-10-07 20:30:08 +00:00
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case ARM::VST3q8a:
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case ARM::VST3q16a:
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case ARM::VST3q32a:
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FirstOpnd = 4;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST3q8b:
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case ARM::VST3q16b:
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case ARM::VST3q32b:
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FirstOpnd = 4;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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2009-10-08 23:51:31 +00:00
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case ARM::VST3LNq16a:
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case ARM::VST3LNq32a:
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FirstOpnd = 3;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST3LNq16b:
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case ARM::VST3LNq32b:
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FirstOpnd = 3;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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2009-08-06 18:47:44 +00:00
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case ARM::VST4d8:
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case ARM::VST4d16:
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case ARM::VST4d32:
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2009-10-08 05:18:18 +00:00
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case ARM::VST4d64:
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2009-09-01 18:51:56 +00:00
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case ARM::VST4LNd8:
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case ARM::VST4LNd16:
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case ARM::VST4LNd32:
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2009-08-06 18:47:44 +00:00
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FirstOpnd = 3;
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NumRegs = 4;
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return true;
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2009-08-12 20:51:55 +00:00
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2009-10-07 20:49:18 +00:00
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case ARM::VST4q8a:
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case ARM::VST4q16a:
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case ARM::VST4q32a:
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FirstOpnd = 4;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST4q8b:
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case ARM::VST4q16b:
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case ARM::VST4q32b:
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FirstOpnd = 4;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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2009-10-09 00:01:36 +00:00
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case ARM::VST4LNq16a:
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case ARM::VST4LNq32a:
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FirstOpnd = 3;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST4LNq16b:
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case ARM::VST4LNq32b:
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FirstOpnd = 3;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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2009-08-12 20:51:55 +00:00
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case ARM::VTBL2:
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FirstOpnd = 1;
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NumRegs = 2;
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return true;
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case ARM::VTBL3:
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FirstOpnd = 1;
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NumRegs = 3;
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return true;
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case ARM::VTBL4:
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FirstOpnd = 1;
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NumRegs = 4;
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return true;
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case ARM::VTBX2:
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FirstOpnd = 2;
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NumRegs = 2;
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return true;
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case ARM::VTBX3:
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FirstOpnd = 2;
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NumRegs = 3;
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return true;
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case ARM::VTBX4:
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FirstOpnd = 2;
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NumRegs = 4;
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return true;
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2009-08-05 23:12:45 +00:00
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}
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return false;
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}
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bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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for (; MBBI != E; ++MBBI) {
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MachineInstr *MI = &*MBBI;
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2009-10-07 17:24:55 +00:00
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unsigned FirstOpnd, NumRegs, Offset, Stride;
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if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
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2009-08-05 23:12:45 +00:00
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continue;
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MachineBasicBlock::iterator NextI = next(MBBI);
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for (unsigned R = 0; R < NumRegs; ++R) {
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MachineOperand &MO = MI->getOperand(FirstOpnd + R);
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assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
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unsigned VirtReg = MO.getReg();
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"expected a virtual register");
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// For now, just assign a fixed set of adjacent registers.
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// This leaves plenty of room for future improvements.
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static const unsigned NEONDRegs[] = {
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2009-10-07 17:24:55 +00:00
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7
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2009-08-05 23:12:45 +00:00
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};
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2009-10-07 17:24:55 +00:00
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MO.setReg(NEONDRegs[Offset + R * Stride]);
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2009-08-05 23:12:45 +00:00
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if (MO.isUse()) {
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// Insert a copy from VirtReg.
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2009-10-06 22:01:15 +00:00
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TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg,
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ARM::DPRRegisterClass, ARM::DPRRegisterClass);
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2009-08-05 23:12:45 +00:00
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if (MO.isKill()) {
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MachineInstr *CopyMI = prior(MBBI);
|
|
|
|
CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
|
|
|
|
}
|
|
|
|
MO.setIsKill();
|
|
|
|
} else if (MO.isDef() && !MO.isDead()) {
|
|
|
|
// Add a copy to VirtReg.
|
2009-10-06 22:01:15 +00:00
|
|
|
TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(),
|
|
|
|
ARM::DPRRegisterClass, ARM::DPRRegisterClass);
|
2009-08-05 23:12:45 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return Modified;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
TII = MF.getTarget().getInstrInfo();
|
|
|
|
|
|
|
|
bool Modified = false;
|
|
|
|
for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
|
|
|
|
++MFI) {
|
|
|
|
MachineBasicBlock &MBB = *MFI;
|
|
|
|
Modified |= PreAllocNEONRegisters(MBB);
|
|
|
|
}
|
|
|
|
|
|
|
|
return Modified;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// createNEONPreAllocPass - returns an instance of the NEON register
|
|
|
|
/// pre-allocation pass.
|
|
|
|
FunctionPass *llvm::createNEONPreAllocPass() {
|
|
|
|
return new NEONPreAllocPass();
|
|
|
|
}
|