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01c99892ca
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889 Commits

Author SHA1 Message Date
Craig Topper
01c99892ca [X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225099 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-03 00:00:20 +00:00
Craig Topper
71fc42dbf6 [X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates. 
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.

Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225075 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-02 07:02:25 +00:00
Craig Topper
c602b726a8 [X86] Update disassembler tests for absolute move instructions to check the encodings. This provides testing for r225036. 64-bit mode is still broken. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225037 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-31 07:24:23 +00:00
Colin LeMahieu
96c631b191 [Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225024 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-31 00:08:34 +00:00
Colin LeMahieu
cb5c5f5934 [Hexagon] Adding double-logic on predicate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225018 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 23:22:39 +00:00
Colin LeMahieu
6026119d9f [Hexagon] Adding newvalue compare and jumps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225015 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 23:04:21 +00:00
Colin LeMahieu
a7940ef0e4 [Hexagon] Adding postincrement register newvalue stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225010 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 22:34:08 +00:00
Colin LeMahieu
df2531486d [Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225009 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 22:28:31 +00:00
Colin LeMahieu
ab63a4c95e [Hexagon] Adding indexed store new-value variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225007 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 22:00:26 +00:00
Colin LeMahieu
3fa758981d [Hexagon] Adding indexed store of immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225006 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 21:01:38 +00:00
Colin LeMahieu
65971bbfd7 [Hexagon] Adding indexed stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225005 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 20:42:23 +00:00
Colin LeMahieu
88e5659aaf [Hexagon] Adding reg-reg indexed load forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224997 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 18:58:47 +00:00
Colin LeMahieu
066f43435a [Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224991 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 17:39:24 +00:00
Colin LeMahieu
af9e1c79a5 [Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224989 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 15:44:17 +00:00
Craig Topper
f8207ac705 Testcases for r224939. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224976 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-30 02:35:56 +00:00
Colin LeMahieu
7c58cad0ca [Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224957 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-29 21:33:45 +00:00
Colin LeMahieu
0bd2ffae08 [Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-29 20:44:51 +00:00
Colin LeMahieu
3dc54ee5a4 [Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-29 20:00:43 +00:00
Colin LeMahieu
d25cfdb649 [Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224949 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-29 19:42:14 +00:00
Colin LeMahieu
17946361cc [Hexagon] Adding auto-incrementing loads with and without byte reversal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224871 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 21:09:25 +00:00
Colin LeMahieu
de2cee5556 [Hexagon] Adding locked loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224870 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 20:42:27 +00:00
Colin LeMahieu
6ff5e4862d [Hexagon] Adding deallocframe and circular addressing loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224869 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 20:30:58 +00:00
Colin LeMahieu
ffba450190 [Hexagon] Adding remaining post-increment instruction variants. Removing unused classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 19:31:46 +00:00
Colin LeMahieu
a46bee194d [Hexagon] Adding post-increment unsigned byte loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224867 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 19:12:11 +00:00
Colin LeMahieu
3c52b7b9f2 [Hexagon] Adding post-increment signed byte loads with tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224866 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 18:57:13 +00:00
Craig Topper
a996db696b [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224862 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 18:20:05 +00:00
Craig Topper
6eb3e3ce10 [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224861 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 18:19:44 +00:00
Craig Topper
654a66dbd3 Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224846 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-26 06:36:28 +00:00
Colin LeMahieu
5dbd280542 [Hexagon] Adding doubleword load. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224787 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 20:44:59 +00:00
Colin LeMahieu
3c3fc28384 [Hexagon] Reapplying 224775 load words. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224786 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 20:02:16 +00:00
Jozef Kolek
c623d0af3d [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions 
Differential Revision: http://reviews.llvm.org/D5204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224785 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 19:55:34 +00:00
Colin LeMahieu
6a9ef539c6 Reverting 224775 until mayLoad flag is addressed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224783 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 19:22:59 +00:00
Colin LeMahieu
5b7d5db23b [Hexagon] Adding word loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224775 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 18:06:56 +00:00
Colin LeMahieu
c9092d2829 [Hexagon] Adding signed halfword loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224774 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 17:25:57 +00:00
Jozef Kolek
e5fa612e9e [mips][microMIPS] Implement LWSP and SWSP instructions 
Differential Revision: http://reviews.llvm.org/D6416


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224771 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 16:16:33 +00:00
Colin LeMahieu
9c0a115fbe [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224735 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-22 21:40:43 +00:00
Colin LeMahieu
76be167773 [Hexagon] Adding classes and load unsigned byte instruction, updating usages. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224730 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-22 21:20:03 +00:00
Colin LeMahieu
bdfe60c796 [Hexagon] Removing old variants of instructions and updating references. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224612 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-19 20:29:29 +00:00
Colin LeMahieu
579ff45d4d [Hexagon] Adding bit extraction and table indexing instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224610 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-19 20:01:08 +00:00
Colin LeMahieu
0d6fdaeaad [Hexagon] Adding bit insertion instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224609 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-19 19:54:38 +00:00
Colin LeMahieu
84b8baf924 [Hexagon] Adding more xtype shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224608 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-19 19:51:35 +00:00
Colin LeMahieu
424493a8fc [Hexagon] Adding xtype shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224604 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-19 19:34:50 +00:00
Colin LeMahieu
e403ffc801 [Hexagon] Adding transfers to and from control registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224599 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-19 19:06:32 +00:00
Colin LeMahieu
128eb8312a [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224556 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-19 00:06:53 +00:00
Colin LeMahieu
a9dd3713d0 Reverting 224550, was not ready for commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224552 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-18 23:36:15 +00:00
Colin LeMahieu
7e9a77a2aa [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224550 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-18 23:27:51 +00:00
Colin LeMahieu
526a14a344 [Hexagon] Updating doubleword shift usages to new versions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224391 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 23:36:15 +00:00
Colin LeMahieu
504c77f9c8 [Hexagon] Adding tstbit/bitclr/bitset instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 21:28:58 +00:00
Colin LeMahieu
18f28b2de6 [Hexagon] Adding bit count and twiddling instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224367 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 20:57:56 +00:00
Colin LeMahieu
50b3134fb4 [Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224365 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 20:40:23 +00:00