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Author SHA1 Message Date
Craig Topper
e6a3a2990e Add FMA4 instructions to disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 05:20:36 +00:00
Craig Topper
5d1a38cbfa Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 04:48:54 +00:00
Craig Topper
4d5c4423b9 Combine FMA4 SS/SD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:33:59 +00:00
Craig Topper
ca28590d8b Combine FMA4 PS/PD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:17:15 +00:00
Craig Topper
2e9ed29449 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 02:18:36 +00:00
Craig Topper
57d4b3315f Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 01:49:53 +00:00
Hal Finkel
2e95afa04c Cleanup stack/frame register define/kill states. This fixes two bugs: 
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).

2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 00:34:00 +00:00
Craig Topper
1604ccfc01 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:43:40 +00:00
Craig Topper
19f18be449 Expose FMA3 instructions to the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:03:14 +00:00
Craig Topper
c38fff4277 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 19:46:19 +00:00
Craig Topper
5ebee4494b Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 19:25:56 +00:00
Craig Topper
8493e39014 Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:47:31 +00:00
Craig Topper
b75f5f7d5d Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:08:36 +00:00
Craig Topper
78be212d1b Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:00:08 +00:00
Craig Topper
d65c7da5b0 Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 17:41:56 +00:00
Craig Topper
d4d3513d37 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 15:51:45 +00:00
Craig Topper
19ec2a9db1 Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:34:54 +00:00
Craig Topper
d62c16e535 Remove some elses after returns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:20:51 +00:00
Craig Topper
3224e6b60a Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147335 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:09:33 +00:00
Eli Friedman
da813f4209 Fix type-checking for load transformation which is not legal on floating-point types. PR11674. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 21:24:44 +00:00
Elena Demikhovsky
021c0a2ee7 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. 
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 08:14:01 +00:00
Benjamin Kramer
27baab62e7 Clean up some Release build warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 11:41:05 +00:00
Craig Topper
3738ccd7eb Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 06:27:23 +00:00
Venkatraman Govindaraju
55caf9c60a Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-25 18:50:24 +00:00
Rafael Espindola
ce618af3e8 Section relative fixups are a coff concept, not a x86 one. Replace the 
x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 14:47:52 +00:00
Chandler Carruth
7782102c70 Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the 
LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type

We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 12:12:34 +00:00
Chandler Carruth
3d636ea8ed Add systematic testing for cttz as well, and fix the bug I spotted by 
inspection earlier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 11:46:10 +00:00
Benjamin Kramer
32d720bb2f Chandler fixed this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 11:23:32 +00:00
Chandler Carruth
d873a4b89b Expand more when we have a nice 'tzcnt' instruction, to avoid generating 
'bsf' instructions here.

This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 11:11:38 +00:00
Chandler Carruth
acc068e873 Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the 
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:

  (sizeof(x)*8 - 1) ^ __builtin_clz(x)

Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.

The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.

Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.

These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 10:55:54 +00:00
Jakob Stoklund Olesen
43ea32ca04 Fix Comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 04:17:01 +00:00
Akira Hatanaka
fd1d9250b2 Add MachineMemOperands to instructions generated in storeRegToStackSlot or 
loadRegFromStackSlot. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 03:11:18 +00:00
Akira Hatanaka
9dfd4399a9 Detect unaligned loads/stores that have been added for Mips64 support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 03:07:37 +00:00
Akira Hatanaka
9dbeb0284d If target ABI is N64, LEA should be daddiu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147232 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 02:59:27 +00:00
Rafael Espindola
df09270ae8 Move x86 specific bits of the COFF writer to lib/Target/X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147231 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-24 02:14:02 +00:00
Jakob Stoklund Olesen
f06f6f50e9 Experimental support for aligned NEON spills. 
ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.

Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.

This feature is off by default, controlled by an -align-neon-spills
command line option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-23 00:36:18 +00:00
Bob Wilson
f4aea8f349 Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138> 
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used.  This
caused massive failures on the testsuite when compiling for Thumb1.  While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 23:39:48 +00:00
Chad Rosier
30450e89d9 Fix 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:35:21 +00:00
Jim Grosbach
4050bc4cab ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:19:05 +00:00
Bob Wilson
d2355e72c5 Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp. 
Noticed by inspection; I don't have a testcase for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147188 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:12:44 +00:00
Jim Grosbach
21bcca81f4 Tidy up. Use predicate function a bit more liberally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:02:35 +00:00
Rafael Espindola
b975c27adc Fix incorrect relocation generation. Patch by Kristof Beyls. 
Fixes PR11214.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 21:36:43 +00:00
Jim Grosbach
c7448f8d47 ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns. 
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:55:21 +00:00
Jim Grosbach
8c748113eb Remove some bogus comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:45:01 +00:00
Jim Grosbach
1aa149f5ac ARM pre-UAL aliases. fcmp[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:20:45 +00:00
Rafael Espindola
f51e95a9f2 Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting 
it. It does need some some tests...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 18:38:06 +00:00
Jim Grosbach
8d9550bde9 ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 18:04:04 +00:00
Jim Grosbach
de626ad872 ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:37:00 +00:00
Jim Grosbach
18c8d12dea Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:17:10 +00:00
Jim Grosbach
f1a88fc474 Nuke invalid comment from copy/paste. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:04:50 +00:00
Rafael Espindola
090445967f Move the Mips only bits of the ELF writer to lib/Target/Mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 03:03:17 +00:00
Rafael Espindola
6db2d92603 Make the virtual methods in ARMELFObjectWriter public. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147132 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 02:58:12 +00:00
Rafael Espindola
4982159b88 Move the MBlaze ELF writer bits to lib/Target/MBlaze. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 02:28:24 +00:00
Rafael Espindola
dcc557f146 Fix cmake. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 02:06:17 +00:00
Rafael Espindola
f3a86fb03d Move PPC bits to lib/Target/PowerPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:57:09 +00:00
Rafael Espindola
81fafde8a6 Hopefully fix the cmake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:11:01 +00:00
Rafael Espindola
7609785d2b Fix name in comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:06:53 +00:00
Akira Hatanaka
bc24985c5f Local dynamic TLS model for direct object output. Create the correct TLS MIPS 
ELF relocations.

Patch by Jack Carter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:05:17 +00:00
Richard Smith
74cab51aa5 Unbreak cmake build after r147115. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:03:35 +00:00
Rafael Espindola
69bbda0391 Move the ARM specific parts of the ELF writer to Target/ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 00:37:50 +00:00
Jim Grosbach
f7c66fa0de ARM NEON mnemonic aliase for vrecpeq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:52:37 +00:00
Jim Grosbach
af33a0cfe0 ARM VFP optional data type on VMOV GPR<-->SPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:24:15 +00:00
Jim Grosbach
5f669fa8ba ARM NEON optional data type on VSWP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:09:28 +00:00
Jim Grosbach
4553fa3128 ARM NEON mnemonic aliases for vzipq and vswpq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:04:33 +00:00
Jim Grosbach
de4d83943a ARM asm parser should be more lenient w/ .thumb_func directive. 
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 22:30:16 +00:00
Jim Grosbach
520dc78d92 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 21:04:19 +00:00
Chad Rosier
5c0d761d63 Fix 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:59:09 +00:00
Jim Grosbach
2cc5cda464 Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:54:00 +00:00
Jakob Stoklund Olesen
a2a98fd0dd Move common code into an MRI function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:50:05 +00:00
Jim Grosbach
e6949b1399 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:40:55 +00:00
Chad Rosier
649326ab15 No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't 
necessary.  Please chime in if I'm mistaken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:14:52 +00:00
Chad Rosier
8d0447c506 Fix a couple of copy-n-paste bugs. Noticed by George Russell! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 18:56:22 +00:00
Rafael Espindola
edae8e1e4d Move the X86 specific bits of the ELF writer to the Target/X86 directory. 
Other targets will follow shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:30:17 +00:00
Rafael Espindola
dc9a8a378d Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:00:36 +00:00
Craig Topper
224c1b275d Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 08:06:52 +00:00
Craig Topper
e1a18a66df Fix typo in a couple comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 06:30:53 +00:00
Evan Cheng
1e33e8b715 Fix a couple of copy-n-paste bugs. Noticed by George Russell. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 03:04:10 +00:00
Jim Grosbach
c931325d99 ARM assembly parsing allows constant expressions for lane indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 01:19:23 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:38:54 +00:00
Akira Hatanaka
c7541c49a9 Fix bug in zero-store peephole pattern reported in pr11615. 
The patch and test case were originally written by Mans Rullgard.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:31:10 +00:00
Akira Hatanaka
c79507a4dd Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:20:27 +00:00
Akira Hatanaka
7f162743fc Expand 64-bit CTPOP and CTTZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:14:05 +00:00
Akira Hatanaka
9aed504c82 Expand 64-bit atomic load and store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:02:58 +00:00
Akira Hatanaka
c0ea04389c Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.



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 2011-12-20 23:56:43 +00:00
Akira Hatanaka
4d2b0f3ce7 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:47:44 +00:00
Akira Hatanaka
e1bcd6b5c6 64-bit uint-fp conversion nodes are expanded. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:40:56 +00:00
Akira Hatanaka
9388383b34 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:35:46 +00:00
Akira Hatanaka
056a1bc40f Set the correct stack pointer register that should be saved or restored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:28:36 +00:00
Jim Grosbach
aee718beac ARM .req register name aliases are case insensitive, just like regnames. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:11:00 +00:00
Akira Hatanaka
2fd0475cdb Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:10:57 +00:00
Akira Hatanaka
49d534bb3d Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:58:01 +00:00
Akira Hatanaka
8dc684d2a2 64-bit data directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:52:19 +00:00
Akira Hatanaka
ef43c2de86 32-to-64-bit sext_inreg pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:40:40 +00:00
Akira Hatanaka
acb5a06f7a Add 64-bit extload patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:36:08 +00:00
Akira Hatanaka
ab05b6c227 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:33:53 +00:00
Jim Grosbach
3cbe43fe69 Move comment to appropriate place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:26:38 +00:00
Akira Hatanaka
990d639f55 Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
52346e964f Heed spill slot alignment on ARM. 
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:15:04 +00:00
Akira Hatanaka
05c585319b Revert part of r146995 that was accidentally commmitted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:09:36 +00:00
Akira Hatanaka
403992dc58 32-to-64-bit sign extension pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:06:20 +00:00
Akira Hatanaka
caace8abdf Add a pattern for matching zero-store with 64-bit address. The pattern is enabled 
only when the target ABI is N64. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146992 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 21:50:49 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:46:29 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 19:21:26 +00:00
Evan Cheng
afff941211 ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 18:26:50 +00:00
Jason W Kim
d7c9e08b6b First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 17:38:12 +00:00
Elena Demikhovsky
ba4f83b4e9 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 13:34:28 +00:00
Chandler Carruth
f2d7693fbb Begin teaching the X86 target how to efficiently codegen patterns that 
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 11:19:37 +00:00
Chandler Carruth
cfb75fba73 Fix up the CMake build for the new files added in r146960, they're 
likely to stay either way that discussion ends up resolving itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 08:42:11 +00:00
David Blaikie
2d24e2a396 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 02:50:00 +00:00
Bob Wilson
c0b0e57a87 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. 
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers.  But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore.  Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early.  This also more accurately reflects
when the registers are clobbered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 01:29:27 +00:00
Jim Grosbach
04b5d93250 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 00:59:38 +00:00
Dan Gohman
e3376ecd50 Add basic generic CodeGen support for half. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 00:02:33 +00:00
Jim Grosbach
9b0878512f ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:51:07 +00:00
Jim Grosbach
2f196747f1 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:06:24 +00:00
Akira Hatanaka
f06cb2b207 Add patterns for matching immediates whose lower 16-bit is cleared. These 
patterns emit a single LUi instruction instead of a pair of LUi and ORi.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 20:21:18 +00:00
Akira Hatanaka
8209968306 Tidy up. Simplify logic. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:52:25 +00:00
Jim Grosbach
d22170e16a ARM NEON two-operand aliases for VPADD. 
rdar://10602276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:51:03 +00:00
Akira Hatanaka
ee973147ac Remove definitions of double word shift plus 32 instructions. Assembler or 
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:44:09 +00:00
Jim Grosbach
6849019079 ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:43:50 +00:00
Akira Hatanaka
ed538b5271 Remove unused predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:32:20 +00:00
Akira Hatanaka
89dc8d790d Remove the restriction on the first operand of the add node in SelectAddr. 
This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:28:37 +00:00
Jim Grosbach
9c39789c36 ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:02:41 +00:00
Jim Grosbach
61b74b4247 ARM NEON implied destination aliases for VMAX/VMIN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636 ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:31:43 +00:00
Jim Grosbach
3346dcef02 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:11:17 +00:00
Jakob Stoklund Olesen
9897c622e0 Remove a register class that can just as well be synthesized. 
Add the new TableGen register class synthesizer feature to the release
notes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 16:53:40 +00:00
Jakob Stoklund Olesen
570f9a972e Emit a getMatchingSuperRegClass() implementation for every target. 
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 16:53:34 +00:00
Benjamin Kramer
0581ed792b Another variadics tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-18 20:51:31 +00:00
Benjamin Kramer
2ea4cdb81f Use the fancy new VariadicFunction template instead of a plain variadic function. 
Some compilers were complaining about passing StringRef to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-18 19:59:20 +00:00
Benjamin Kramer
4c1ea552c5 Hexagon: Remove unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-18 12:00:09 +00:00
Craig Topper
ab44d3cf49 Remove an unused X86ISD node type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 19:16:44 +00:00
Benjamin Kramer
e6cddb77dc X86: Factor the bswap asm matching to be slightly less horrible to read. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146831 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 14:36:05 +00:00
Evan Cheng
b16db81719 Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:25:34 +00:00
Rafael Espindola
8f7d12ccfd Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:14:52 +00:00
Lang Hames
8b99c1e42c Make sure that the lower bits on the VSELECT condition are properly set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 01:08:46 +00:00
Jakob Stoklund Olesen
2027379985 Preserve more memory operands in ARMExpandPseudo. 
I don't think this affects anything but verbose assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-17 00:07:02 +00:00
Jakob Stoklund Olesen
b076fb7762 Fix off-by-one error in bucket sort. 
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 23:00:05 +00:00
Jakob Stoklund Olesen
f9aabb8f32 Don't adjust for alignment padding in OffsetIsInRange. 
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.

When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 19:10:00 +00:00
Benjamin Kramer
903456245b Hexagon: Fix a nasty order-of-initialization bug. 
Reenable the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 19:08:59 +00:00
Jakob Stoklund Olesen
f5bb45f895 Note ARM constant island alignment in the release notes. 
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 16:07:41 +00:00
Craig Topper
94438ba538 Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 08:06:31 +00:00
NAKAMURA Takumi
46209476e7 Target/Hexagon: Fix CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 06:21:02 +00:00
Jim Grosbach
ddecfe54a3 ARM NEON aliases for vmovq.f* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 00:12:22 +00:00
Jim Grosbach
b6744db06f Thumb2 ADR assembly parsing w/o the .w suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 23:52:17 +00:00
Eli Friedman
7e840efc23 Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 23:46:18 +00:00
Nick Lewycky
028700f544 Move parts of lib/Target that use CodeGen into lib/CodeGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:58:58 +00:00
Eli Friedman
2f21e8c5ba Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146700 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:56:53 +00:00
Jim Grosbach
a738da7bd3 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:56:33 +00:00
Tony Linthicum
d239ff67f2 Add MCTargetDesc library to Hexagon target 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146692 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:29:08 +00:00
Jim Grosbach
60d99a5278 ARM NEON VTBL/VTBX assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:27:11 +00:00