Jim Grosbach
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7ec7a0e96b
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switch the flag for using NEON for SP floating point to a subtarget 'feature'.
Re-commit. This time complete with testsuite updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
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2010-03-25 23:47:34 +00:00 |
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Jim Grosbach
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78e496e165
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need to fix 'make check' tests first. revert for a moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
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2010-03-25 23:34:05 +00:00 |
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Jim Grosbach
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bd17bc96bf
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switch the flag for using NEON for SP floating point to a subtarget 'feature'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8
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2010-03-25 23:32:19 +00:00 |
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Jim Grosbach
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6b2e8dc9a0
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switch the use-vml[as] instructions flag to a subtarget 'feature'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
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2010-03-25 23:11:16 +00:00 |
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Anton Korobeynikov
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631379e79c
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Add substarget feature for FP16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
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2010-03-14 18:42:38 +00:00 |
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David Goodwin
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ebb5cb9216
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Add ARMv6 itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89218 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-11-18 18:39:57 +00:00 |
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Anton Korobeynikov
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f95215f551
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Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-11-02 00:10:38 +00:00 |
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David Goodwin
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9843a93e83
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Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-10-01 22:19:57 +00:00 |
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David Goodwin
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471850ab84
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Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-10-01 21:46:35 +00:00 |
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David Goodwin
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0dad89fa94
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Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-09-30 00:10:16 +00:00 |
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David Goodwin
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127221fbdc
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Checkpoint NEON scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-09-23 21:38:08 +00:00 |
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David Goodwin
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546952fd60
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Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-11 22:38:43 +00:00 |
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David Goodwin
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767a952a6f
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Make NEON single-precision FP support the default for cortex-a8 (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-07 23:32:33 +00:00 |
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David Goodwin
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ce3c1f2a0e
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Disable NEON single-precision FP support for Cortex-A8, for now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78209 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-05 16:40:57 +00:00 |
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David Goodwin
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1f0e404c87
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By default, for cortex-a8 use NEON for single-precision FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-05 16:01:19 +00:00 |
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David Goodwin
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42a83f2d15
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Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-04 17:53:06 +00:00 |
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Evan Cheng
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6762d91c05
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Add fake v7 itineraries for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76612 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-21 18:54:14 +00:00 |
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Evan Cheng
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34a0fa362d
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Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74988 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-08 01:46:35 +00:00 |
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Evan Cheng
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8557c2bcb8
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Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-06-19 01:51:50 +00:00 |
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Anton Korobeynikov
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fbbf1eeccf
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Separate V6 from V6T2 since the latter has some extra nice instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73085 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-06-08 21:20:36 +00:00 |
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Anton Korobeynikov
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d4022c3fbb
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Add placeholder for thumb2 stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-05-29 23:41:08 +00:00 |
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Anton Korobeynikov
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6d7d2aa38a
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Add ARMv7 architecture, Cortex processors and different FPU modes handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-05-23 19:51:43 +00:00 |
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Bob Wilson
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1f595bb429
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Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-04-17 19:07:39 +00:00 |
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Evan Cheng
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027fdbe3ba
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Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-24 07:34:46 +00:00 |
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Evan Cheng
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d87293ce78
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Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-06 08:47:38 +00:00 |
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Evan Cheng
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edda31c412
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Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-05 18:35:52 +00:00 |
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Chris Lattner
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4ee451de36
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Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-12-29 20:36:04 +00:00 |
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Evan Cheng
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0ff94f7fcc
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Initial JIT support for ARM by Raul Fernandes Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-08-07 01:37:15 +00:00 |
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Lauro Ramos Venancio
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a8e9562906
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Add a processor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36765 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-05-04 22:16:30 +00:00 |
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Evan Cheng
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a8e2989ece
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ARM backend contribution from Apple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-01-19 07:51:42 +00:00 |
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Evan Cheng
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0f3ac8d8d4
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getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
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2006-05-18 00:12:58 +00:00 |
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Evan Cheng
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c01d497255
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Remove PointerType from class Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
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2006-05-17 21:20:27 +00:00 |
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Rafael Espindola
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7bc59bc395
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added a skeleton of the ARM backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
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2006-05-14 22:18:28 +00:00 |
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