Jim Grosbach
19cb7f491f
MCTargetAsmParser target match predicate support.
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Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 23:03:29 +00:00
Owen Anderson
c537f3be0c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:51:32 +00:00
Owen Anderson
92be8ab6a4
Remove dead classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137643 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:11:11 +00:00
Owen Anderson
5df7ef6cdb
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:08:25 +00:00
Owen Anderson
305e046e53
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 19:00:06 +00:00
Owen Anderson
7a2e1770ea
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 18:44:44 +00:00
Jim Grosbach
8757a4c6ab
Update comment to reflect MC target machine refactor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137615 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 16:52:24 +00:00
Bob Wilson
7dcd04abe0
Expand VMOVQQQQ pseudo instructions.
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Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-13 05:14:55 +00:00
Jim Grosbach
10342123ad
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
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Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 22:20:41 +00:00
Jim Grosbach
4dfe220ad5
ARM expansion of pre-indexed store pseudos should maintain memoperands.
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Partial fix for rdar://9945172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137513 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 21:02:34 +00:00
Owen Anderson
0d09499cf3
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:36:11 +00:00
Owen Anderson
79628e92e1
Fix decoding of ARM-mode STRH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:02:50 +00:00
Owen Anderson
6368119c25
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 19:41:29 +00:00
Owen Anderson
7cdbf086e4
Fix decoding of pre-indexed stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 18:12:39 +00:00
Owen Anderson
3f3570a38b
Separate decoding for STREXD and LDREXD to make each work better.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 17:58:32 +00:00
Duncan Sands
1f6a329f79
Silence a bunch (but not all) "variable written but not read" warnings
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when building with assertions disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137460 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 14:54:45 +00:00
Jim Grosbach
857e1a7b3f
ARM vector compare to zero instruction assembly parsing support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 23:51:13 +00:00
Jim Grosbach
d30970fb6c
Remove no-longer-true comments. These are for the assembler, also.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:30:30 +00:00
Jim Grosbach
342ebd5f38
ARM STRT assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:18:00 +00:00
Owen Anderson
41ff834e91
Make the USAT16 operand decoder auto-generate-able.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:10:11 +00:00
Owen Anderson
adf2b094cb
Add another accidentally omitted predicate operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:08:38 +00:00
Owen Anderson
1fb6673bc2
Add missing predicate operand on SMLA and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:05:38 +00:00
Jim Grosbach
dd32ba337a
ARM load shifted register pre-index fix shift value asm parser encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:05:09 +00:00
Owen Anderson
796d6b7602
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137364 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:52:38 +00:00
Owen Anderson
05b0c9f41e
Making SEL decodings auto-generate-able.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:50:56 +00:00
Jim Grosbach
89958d50c3
Tidy up comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137359 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:41:59 +00:00
Owen Anderson
cbfc044acd
Fix decoding support for STREXD and LDREXD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:34:58 +00:00
Jim Grosbach
7b8f46cf9e
ARM STRH assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:17:22 +00:00
Owen Anderson
508e1d3db5
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:47:56 +00:00
Jim Grosbach
45251b3707
Tidy up. Remove unused template parameter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:41:13 +00:00
Owen Anderson
9fe72bcd37
Improve operand validation for Thumb2 addressing modes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:40:40 +00:00
Jim Grosbach
14605d1a67
ARM STRD assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:28:23 +00:00
Owen Anderson
26d2f0ac91
Continue to tighten decoding by performing more operand validation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:21:46 +00:00
Jim Grosbach
ade7d00f5a
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:13:35 +00:00
Jim Grosbach
10348e70d5
ARM STRBT assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:04:56 +00:00
Jim Grosbach
548340c4bf
ARM STR(immediate) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:22:40 +00:00
Owen Anderson
71156a6e00
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:00:18 +00:00
Owen Anderson
2b7b238e84
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:55:42 +00:00
Owen Anderson
3dac0bec7e
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:41:59 +00:00
Owen Anderson
ae0bc5deaa
Improve error checking in the new ARM disassembler. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:24:51 +00:00
Jim Grosbach
f6713916fb
ARM push of a single register encodes as pre-indexed STR.
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Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:07:11 +00:00
Jim Grosbach
f8fce711e8
ARM pop of a single register encodes as post-indexed LDR.
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Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 17:35:48 +00:00
Jim Grosbach
59999264e6
ARM LDRT assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 23:43:54 +00:00
Jim Grosbach
e15defc56c
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 23:23:47 +00:00
Jim Grosbach
623a454b0f
ARM LDRH(immediate) assembly parsing and encoding support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 22:42:16 +00:00
Jim Grosbach
251bf25e7e
ARM LDRD(register) assembly parsing and encoding.
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Add support for literal encoding of #-0 along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 21:56:18 +00:00
Jim Grosbach
53642c5335
Fix typo. Not quite sure how that slipped in there.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 20:49:18 +00:00
Jim Grosbach
2fd2b87ded
ARM LDRD(immediate) assembly parsing and encoding support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 20:29:19 +00:00
Owen Anderson
8533ebad6f
Add initial support for decoding NEON instructions in Thumb2 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 19:01:10 +00:00
Owen Anderson
fd9085dca3
Tabs --> spaces.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:38:05 +00:00