Commit Graph

6176 Commits

Author SHA1 Message Date
Justin Holewinski
d2ea0e10cb Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25 16:35:28 +00:00
Craig Topper
51f50c1106 Make some opcode tables static and const. Allows code to avoid making copies to pass the tables around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24 05:17:00 +00:00
Craig Topper
032f441afc Mark a static array as const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157368 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24 04:11:15 +00:00
Craig Topper
cd2859eef8 Mark a static table as const. Shrink opcode size in static tables to uint16_t. Simplify loop iterating over one of those tables. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24 03:59:11 +00:00
Chad Rosier
1c8fccbc12 [arm-fast-isel] Add support for non-global callee.
Patch by Jush Lu <jush.msn@gmail.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23 18:38:57 +00:00
NAKAMURA Takumi
dd051a0414 ARMDisassembler.cpp: Fix utf8 char in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-22 21:47:02 +00:00
Jim Grosbach
b3a119a257 ARM: .end_data_region mismatch in Thumb2.
32-bit offset jump tables just use real branch instructions and so aren't
marked as data regions. We were still emitting the .end_data_region
marker though, which assert()ed.

rdar://11499158

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-21 23:34:42 +00:00
Jim Grosbach
b551f0cc78 Thumb2: RSB source register should be rGRP not GPRnopc.
t2RSB defined the operand correctly, but tRSBS didn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157200 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-21 17:57:17 +00:00
Jakob Stoklund Olesen
027c32a14e Use the right register class for LDRrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-20 06:38:47 +00:00
Jakob Stoklund Olesen
6e6269a976 Transfer memory operands to the right instruction.
They need to go on the PICLDR as the verifier points out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-20 06:38:42 +00:00
Jim Grosbach
3e96531186 Refactor data-in-code annotations.
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18 19:12:01 +00:00
Kevin Enderby
0fd4f3c8de Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits.  Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use.  Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions.  Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 22:18:01 +00:00
Tim Northover
44600d7081 Remove incorrect pattern for ARM SMML instruction.
Patch by Meador Inge.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 13:12:13 +00:00
Jim Grosbach
918f55fe23 Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15 17:35:52 +00:00
David Blaikie
9cc178726f Fix use of uninitialized variable.
Found by GCC's maybe-uninitialized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14 21:48:19 +00:00
Chad Rosier
226ddf5278 [fast-isel] Add support for selecting @llvm.trap().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 21:33:49 +00:00
Chad Rosier
2b3b335f2d [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:40:25 +00:00
Chad Rosier
2a2e9d54e9 [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 18:51:55 +00:00
Chad Rosier
2f6ae41f14 [fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 17:41:06 +00:00
Chad Rosier
f4bd21c256 The return type is an unsigned, not a bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 16:41:38 +00:00
Manman Ren
4949e98ccc Add space before an open parenthesis in control flow statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 15:36:46 +00:00
Silviu Baranga
169e9ba2b2 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 09:28:27 +00:00
Silviu Baranga
ca3cd419a5 Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 09:10:54 +00:00
Manman Ren
247c5ab07c ARM: peephole optimization to remove cmp instruction
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 01:30:47 +00:00
Manman Ren
fe65d98dad Revert: 156550 "ARM: peephole optimization to remove cmp instruction"
This commit broke an external linux bot and gave a compile-time warning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 18:49:43 +00:00
Manman Ren
8ae4f062e4 ARM: peephole optimization to remove cmp instruction
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 16:48:21 +00:00
Jakob Stoklund Olesen
397fc4874e Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 22:10:26 +00:00
Jim Grosbach
e5f31ad55e Nuke a few dead remnants of the CBE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 17:45:12 +00:00
Benjamin Kramer
aaf723dd2b Add a new target hook "predictableSelectIsExpensive".
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.

Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.

I'm not entirely happy with the name of this flag, suggestions welcome ;)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 12:49:14 +00:00
Kevin Enderby
3610a15c35 Tweak to the fix in r156212, as with the change in removing the shift the
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:09:52 +00:00
Kevin Enderby
ce734d5ffe Fix a bug in the ARM disassembler for wide branch conditional instructions
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 22:02:27 +00:00
Sebastian Pop
2c7e5c714c Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 19:53:56 +00:00
Matt Beaumont-Gay
39af9449a2 Pacify GCC's -Wreturn-type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 18:34:27 +00:00
Hans Wennborg
fd5abd546e Make ARM and Mips use TargetMachine::getTLSModel()
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 09:40:39 +00:00
Jakob Stoklund Olesen
338607ae0d Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 03:30:34 +00:00
Kevin Enderby
2d524b0765 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:41:56 +00:00
Silviu Baranga
b422d0b65e Fixed disassembler for vstm/vldm ARM VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 16:38:40 +00:00
Jim Grosbach
2727930ab4 ARM: Add missing two-operand VBIC aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 21:11:56 +00:00
Richard Barton
0a552d611e Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 09:43:18 +00:00
Jim Grosbach
54319e2a8c ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
        adds.w r2, #-16
        adds.w r2, r2, #-16
        addw r2, #-16
        addw r2, #-16
        addw r2, r2, #-16

rdar://11330769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 21:17:34 +00:00
Jim Grosbach
94b590f8fa ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.

rdar://10550147

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 20:43:21 +00:00
Bill Wendling
7c4ce30ea6 Change the PassManager from a reference to a pointer.
The TargetPassManager's default constructor wants to initialize the PassManager
to 'null'. But it's illegal to bind a null reference to a null l-value. Make the
ivar a pointer instead.
PR12468


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 08:27:43 +00:00
Jim Grosbach
7a3afa91ad ARM: Diagnostics for out of range fixups.
Replace some assert() calls w/ actual diagnostics. In a perfect world,
there'd be range checks on these values long before things ever reached
this code. For now, though, issuing a better-late-than-never diagnostic
is still a big improvement over assert().

rdar://11347287

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 22:30:43 +00:00
Jakob Stoklund Olesen
887d095fb6 Fix address calculation error from r155744.
This was exposed by SingleSource/UnitTests/Vector/constpool.c.

The computed size of a basic block isn't always a multiple of its known
alignment, and that can introduce extra alignment padding after the
block.

<rdar://problem/11347135>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 20:19:00 +00:00
Bob Wilson
ff73d8fef9 Don't introduce illegal types when creating vmull operations. <rdar://11324364>
ARM BUILD_VECTORs created after type legalization cannot use i8 or i16
operands, since those types are not legal.  Instead use i32 operands, which
will be implicitly truncated by the BUILD_VECTOR to match the element type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 16:53:34 +00:00
Jakob Stoklund Olesen
9b10dae0bf Fix a problem with blocks that need to be split twice.
The code could search past the end of the basic block when there was
already a constant pool entry after the block.

Test case with giant basic block in SingleSource/UnitTests/Vector/constpool.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-28 06:21:38 +00:00
Jim Grosbach
a9cc08f24f ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:51:36 +00:00
Jim Grosbach
bb32f1d545 ARM: Tweak tADDrSP definition for consistent operand order.
Make the operand order of the instruction match that of the asm syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:51:33 +00:00
Jakob Stoklund Olesen
456ff46e66 Track worst case alignment padding more accurately.
Previously, ARMConstantIslandPass would conservatively compute the
address of an aligned basic block as:

  RoundUpToAlignment(Offset + UnknownPadding)

This worked fine for the layout algorithm itself, but it could fool the
verify() function because it accounts for alignment padding twice: Once
when adding the worst case UnknownPadding, and again by rounding up the
fictional block offset. This meant that when optimizeThumb2Instructions
would shrink an instruction, the conservative distance estimate could
grow. That shouldn't be possible since the woorst case alignment padding
wss already included.

This patch drops the use of RoundUpToAlignment, and depends only on
worst case padding to compute conservative block offsets. This has the
weird effect that the computed offset for an aligned block may not be
aligned.

The important difference is that shrinking an instruction can never
cause the estimated distance between two instructions to grow. The
estimated distance is always larger than the real distance that only the
assembler knows.

<rdar://problem/11339352>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 22:58:38 +00:00
Lang Hames
7787800481 Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,
<rdar://problem/11325085>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 18:51:24 +00:00