Commit Graph

81320 Commits

Author SHA1 Message Date
Alex Lorenz
ad6702ec23 MIR Serialization: Serialize the virtual register definitions.
The virtual registers are serialized using a YAML sequence of YAML inline
mappings. Each mapping has the id of the virtual register and the register
class.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:23:13 +00:00
Adam Nemet
81e7e2dfab [LAA] Fix grammar in debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241867 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:17:41 +00:00
Adam Nemet
1c25d370c1 [LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFC
Currently canCheckPtrAtRT returns two flags NeedRTCheck and CanDoRT.
NeedRTCheck says whether we need checks and CanDoRT whether we can
generate the checks.  The idea is to encode three states with these:

     Need/Can:
(1) false/dont-care: no checks are needed
(2) true/false: we need checks but can't generate them
(3) true/true: we need checks and we can generate them

This is pretty unnecessary since the caller (analyzeLoop) is only
interested in whether we can generate the checks if we actually need
them (i.e. 1 or 3).

So this change cleans up to return just that (CanDoRTIfNeeded) and pulls
all the underlying logic into canCheckPtrAtRT.

By doing all this, we simplify analyzeLoop which is the complex function
in LAA.

There is further room for improvement here by using RtCheck.Need
directly rather than a new local variable NeedRTCheck but that's for a
later patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241866 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:17:38 +00:00
Reid Kleckner
5cf6c0b070 [WinEH] Give up on using CSRs across 32-bit invokes for now
The runtime does not restore CSRs when transferring control back to the
function handling the exception. According to the experts on IRC, LLVM's
register allocator has no way to model register clobbers that only
happen on one edge of the CFG. For now, don't worry about trying to use
the meager three CSRs available on 32-bit X86 and just say that such
invokes preserve nothing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241865 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:09:41 +00:00
Reid Kleckner
827f211e95 Expose sjlj preparation through opt for my own debugging purposes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241864 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:48:40 +00:00
Alex Lorenz
ccba68af82 MIR Parser: Report an error when parsing machine function with an empty body.
This commit adds a new error which is reported when the MIR Parser encounters
a machine function without any machine basic blocks. The machine verifier
expects that the machine functions have at least one MBB, and this error will
prevent machine functions without MBBs from reaching the machine verifier and
crashing with an assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241862 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:21:33 +00:00
Tom Stellard
847c023a2e AMDGPU: Add helper function for implicit parameter offsets.
Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241861 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:20:37 +00:00
JF Bastien
b5ebaf3ae5 Unbreak WebAssembly build
Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed.

Reviewers: sunfish, joker.eph, echristo

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241859 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:00:09 +00:00
Sanjoy Das
efec6ccae3 [ImplicitNullChecks] Fix a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241851 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:13:31 +00:00
Sanjoy Das
a5a3e2d58a [ImplicitNullChecks] Be smarter in picking the memory op.
Summary:
Before this change ImplicitNullChecks would only pick loads of the form:

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   movl 32(Reg), Reg2
```

but not (say)

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   inc Reg3
   movl 32(Reg), Reg2
```

This change teaches ImplicitNullChecks to look through "unrelated"
instructions like `inc Reg3` when searching for a load instruction
to convert to a trapping load.

Reviewers: atrick, JosephTremoulet, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:13:25 +00:00
Alex Lorenz
7c6ad33126 MIR Serialization: Serialize the simple MachineFrameInfo attributes.
This commit serializes the 13 scalar boolean and integer attributes from the
MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap,
HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack,
HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and
HasMustTailInVarArgFunc. These attributes are serialized as part
of the frameInfo YAML mapping, which itself is a part of the machine function's
YAML mapping.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241844 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 19:55:27 +00:00
Rafael Espindola
7255090cd3 llvm-ar: Pad the symbol table to 4 bytes.
It looks like ld64 requires it. With this we seem to be able to bootstrap using
llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 19:48:06 +00:00
Matt Arsenault
0685a5c5ed AMDGPU/R600: Return correct chain when lowering loads
The other LowerLOAD should be returning the correct chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:47:03 +00:00
Sanjoy Das
4db527032a [IndVars] Try to use existing values in RewriteLoopExitValues.
Summary:
In RewriteLoopExitValues, before expanding out an SCEV expression using
SCEVExpander, try to see if an existing LLVM IR expression already
computes the value we're interested in.  If so use that existing
expression.

Apart from reducing IndVars' reliance on the rest of the compilation
pipeline, this also prevents IndVars from concluding some expressions as
"high cost" when they're not.  For instance,
`InductiveRangeCheckElimination` often emits code of the following form:

```
len = umin(len_A, len_B)

loop:
  ...
  if (i++ < len)
    goto loop

outside_loop:
    use(i)
```

`SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`,
since it thinks the value of `i` on loop exit, `len`, is a high cost
expansion since it contains an `umax` in it.  With this change,
`IndVars` can see that it can re-use `len` instead of creating a new
expression to compute `umin(len_A, len_B)`.

I considered putting this cleverness in `SCEVExpander`, but I was
worried that it may then have a deterimental effect on other passes
that use it.  So I decided it was better to just do this in the one
place where it seems like an obviously good idea, with the intent of
generalizing later if needed.

Reviewers: atrick, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10782

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241838 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:46:12 +00:00
Reid Kleckner
5574399e37 Remove dead code from old 64-bit SEH lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:46:39 +00:00
Pat Gavlin
db5a82b861 Allow {e,r}bp as the target of {read,write}_register.
This patch allows the read_register and write_register intrinsics to
read/write the RBP/EBP registers on X86 iff the targeted register is
the frame pointer for the containing function.

Differential Revision: http://reviews.llvm.org/D10977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241827 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:40:29 +00:00
Sanjay Patel
dc219dddde fix an invisible bug when combining repeated FP divisors
This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG:
r237046 ( http://reviews.llvm.org/rL237046 ):

1. When replacing a division node, it's not enough to RAUW.
   We should call CombineTo() to delete dead nodes and combine again.
2. Because we are changing the DAG, we can't return an empty SDValue
   after the transform. As the code comments say:

    Visitation implementation - Implement dag node combining for different node types.
    The semantics are as follows: Return Value:
      SDValue.getNode() == 0 - No change was made
      SDValue.getNode() == N - N was replaced, is dead and has been handled.
      otherwise - N should be replaced by the returned Operand.

The new test case shows no difference with or without this patch, but it will crash if
we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt.

Differential Revision: http://reviews.llvm.org/D9893



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241826 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:28:37 +00:00
Juergen Ributzka
c014920a89 [StackMap] Use lambdas to specify the sort and erase conditions. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241823 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:15 +00:00
Juergen Ributzka
fd5ef9d20c [StackMap] Rename variables to be more consistent. NFC.
Rename a few variables and use auto for long iterator names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241822 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:11 +00:00
Juergen Ributzka
9ba87b84ab [StackMaps] Use emplace_back when possible. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241821 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 17:11:08 +00:00
Tom Stellard
2b2d86178c AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use
This is convered by existing testcases and will be exposed by a future
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:36 +00:00
Tom Stellard
e05910e677 AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()
No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:27 +00:00
Rafael Espindola
a55816b3fc Basic support for BSD symbol tables in archives.
This could be optimized and for now we only produce __.SYMDEF
and not "__.SYMDEF SORTED".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241814 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:56:23 +00:00
Krzysztof Parzyszek
8e78dfcf23 [Hexagon] Add missing preamble to a source file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:40:25 +00:00
Rafael Espindola
f336caf392 Remove redundant variable. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241810 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:24:39 +00:00
Silviu Baranga
f283cd9acf Don't rely on the DepCands iteration order when constructing checking pointer groups
Summary:
The checking pointer group construction algorithm relied on the iteration on DepCands.
We would need the same leaders across runs and the same iteration order over the underlying std::set for determinism.

This changes the algorithm to process the pointers in the order in which they were added to the runtime check, which is deterministic.
We need to update the tests, since the order in which pointers appear has changed.

No new tests were added, since it is impossible to test for non-determinism.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11064

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241809 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:18:25 +00:00
Rafael Espindola
3696927846 Add a helper to printing BE of LE depending on the format.
The gnu ar format uses BE numbers. The BSD one uses LE. Add a helper for one or the
other. NFC for now, just removes some noise from the following patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241808 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:13:41 +00:00
Mehdi Amini
cdc323b2b7 Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT user
A documentation for this function would be nice by the way.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241807 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:12:23 +00:00
Pawel Bylica
dbbfabaf01 Reapply fixed r241790: Fix shift legalization and lowering for big constants.
Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.

Reviewers: nadav, majnemer, sanjoy, RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241806 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:58:04 +00:00
Rafael Espindola
56240eaf73 Extract printBSDMemberHeader.
It will get another use in the following patch. Also rename the other helper to
printGNUSmallMemberHeader for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241805 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:54:12 +00:00
Krzysztof Parzyszek
b13f72aa2d [Hexagon] Add support for atomic RMW operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241804 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:51:21 +00:00
Arnaud A. de Grandmaison
86d3dfce62 [AArch64] Select SBFIZ or UBFIZ instead of left + right shifts
And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241803 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:33:38 +00:00
Scott Douglass
0e714c7efa [ARM] Thumb1 3 to 2 operand convertion for commutative operations
Differential Revision: http://reviews.llvm.org/D11057

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241802 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:55 +00:00
Scott Douglass
7b8defda79 [ARM] Don't be overzealous converting Thumb1 3 to 2 operands
Differential Revision: http://reviews.llvm.org/D11056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241801 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:48 +00:00
Scott Douglass
3ca1884ba8 [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2
Differential Revision: http://reviews.llvm.org/D11055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241800 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:41 +00:00
Scott Douglass
ab17c04abe [ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc)
Also adds some test cases.

Differential Revision: http://reviews.llvm.org/D11054

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241799 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:13:34 +00:00
Renato Golin
86b4ed2fc4 Add support for nest attribute to AArch64 backend
The nest attribute is currently supported on the x86 (32-bit) and x86-64
backends, but not on ARM (32-bit) or AArch64. This patch adds support for
nest to the AArch64 backend.

Register x18 is used by GCC for this purpose and hence is used here.
As discussed on the GCC mailing list the register choice is an ABI issue
and so choosing the same register as GCC means __builtin_call_with_static_chain
is compatible.

Patch by Stephen Cross.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 10:18:02 +00:00
Tamas Berghammer
6055ca7bf4 Add getSizeInBits function to the APFloat class
The newly added function returns the size of the specified floating
point semantics in bits.

Differential revision: http://reviews.llvm.org/D8413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241793 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 10:13:39 +00:00
Pawel Bylica
b0205f5937 Revert r241790: Fix shift legalization and lowering for big constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241792 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 09:50:54 +00:00
Pawel Bylica
71386b0e04 Fix shift legalization and lowering for big constants.
Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.

Reviewers: nadav, majnemer, sanjoy, RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241790 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 08:01:36 +00:00
Elena Demikhovsky
43afab3bdb Extended syntax of vector version of getelementptr instruction.
The justification of this change is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/082989.html

According to the current GEP syntax, vector GEP requires that each index must be a vector with the same number of elements.

%A = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets

In this implementation I let each index be or vector or scalar. All vector indices must have the same number of elements. The scalar value will mean the splat vector value.

(1) %A = getelementptr i8, i8* %ptr, <4 x i64> %offsets
or
(2) %A = getelementptr i8, <4 x i8*> %ptrs, i64 %offset

In all cases the %A type is <4 x i8*>

In the case (2) we add the same offset to all pointers.

The case (1) covers C[B[i]] case, when we have the same base C and different offsets B[i].

The documentation is updated.

http://reviews.llvm.org/D10496




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241788 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 07:42:48 +00:00
Adam Nemet
f959df643a [LAA] Fix line break in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241785 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 06:47:21 +00:00
Adam Nemet
ecb6a37111 [LAA] Rename IsRTNeeded to IsRTCheckAnalysisNeeded
The original name was too close to NeedRTCheck which is what the actual
memcheck analysis returns.  This flag, as the new name suggests, is only
used to whether to initiate that analysis.

Also a comment is added to answer one question I had about this code for
a long time.  Namely, how does this flag differ from
isDependencyCheckNeeded since they are seemingly set at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241784 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 06:47:18 +00:00
Mehdi Amini
dc4dccabf3 Remove getDataLayout() from TargetSelectionDAGInfo (had no users)
Summary:
Remove empty subclass in the process.

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren, ted

Differential Revision: http://reviews.llvm.org/D11045

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241780 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:10:08 +00:00
Mehdi Amini
691b2ff11e Remove getDataLayout() from TargetLowering
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11042

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241779 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:52 +00:00
Mehdi Amini
0e496c884c Make isLegalAddressingMode() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11040

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:40 +00:00
Mehdi Amini
027a9f4561 Make getByValTypeAlignment() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11038

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241777 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:28 +00:00
Mehdi Amini
29a2d864d4 Make TargetLowering::getShiftAmountTy() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11037

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241776 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:20 +00:00
Mehdi Amini
f29cc18dcb Make TargetLowering::getPointerTy() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11028

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241775 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:04 +00:00
Mehdi Amini
966e6ca1ac Make TargetTransformInfo keeping a reference to the Module DataLayout
DataLayout is no longer optional. It was initialized with or without
a DataLayout, and the DataLayout when supplied could have been the
one from the TargetMachine.

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11021

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241774 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:08:42 +00:00
Mehdi Amini
103bdfccee Redirect DataLayout from TargetMachine to Module in ComputeValueVTs()
Summary:
Avoid using the TargetMachine owned DataLayout and use the Module owned
one instead. This requires passing the DataLayout up the stack to
ComputeValueVTs().

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11019

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241773 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 01:57:34 +00:00
David Majnemer
b1d6ad18ba [CodeView] Add support for emitting column information
Column information is present in CodeView when the line table subsection
has bit 0 set to 1 in it's flags field.  The column information is
represented as a pair of 16-bit quantities: a starting and ending
column.  This information is present at the end of the chunk, after all
the line-PC pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241764 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 00:19:51 +00:00
Adam Nemet
f7f4697e3c [LAA] Fix misleading use of word 'consecutive'
Fix some places where the word consecutive is used but the code really
means constant-stride (i.e. not just unit stride).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241763 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 00:03:22 +00:00
Alex Lorenz
5faf25b798 MIR Serialization: Serialize the 'undef' register machine operand flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241762 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 23:58:31 +00:00
Sanjay Patel
c1c43c15cc [SLPVectorizer] Try different vectorization factors for store chains
...and set max vector register size based on target 

This patch is based on discussion on the llvmdev mailing list:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-July/087405.html

and also solves:
https://llvm.org/bugs/show_bug.cgi?id=17170

Several FIXME/TODO items are noted in comments as potential improvements.

Differential Revision: http://reviews.llvm.org/D10950



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241760 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 23:40:55 +00:00
Matthias Braun
6e999b0a30 RegisterPressure: Add PressureDiff::dump()
Also display the pressure diff in the case of a
getMaxUpwardPressureDelta() verify failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241759 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 23:40:27 +00:00
Adam Nemet
7a6f54545f [LAA] Revert a small part of r239295
This commit ([LAA] Fix estimation of number of memchecks) regressed the
logic a bit.  We shouldn't quit the analysis if we encounter a pointer
without known bounds *unless* we actually need to emit a memcheck for
it.

The original code was using NumComparisons which is now computed
differently.  Instead I compute NeedRTCheck from NumReadPtrChecks and
NumWritePtrChecks.

As side note, I find the separation of NeedRTCheck and CanDoRT
confusing, so I will try to merge them in a follow-up patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241756 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:58:48 +00:00
Juergen Ributzka
9a39681fd9 Run clang-format before making changes to StackMaps. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241754 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:42:09 +00:00
Sanjay Patel
f769239c19 [x86] enable machine combiner reassociations for scalar single-precision multiplies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241752 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:35:20 +00:00
Rafael Espindola
a04933edc1 Don't reject an archive with just a symbol table.
It is pretty unambiguous how to interpret it and gnu ar accepts it too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241750 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:27:54 +00:00
Rafael Espindola
bf4296f2c0 Disallow Archive::child_iterator that don't point to an archive.
NFC, just less error prone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241747 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 22:15:07 +00:00
Michael Zolotukhin
5ebb47fa90 [LoopVectorizer] Rename BypassBlock to VectorPH, and CheckBlock to NewVectorPH. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241742 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:48:03 +00:00
Michael Zolotukhin
c196e8f18b [LoopVectorizer] Restructurize code for emitting RT checks. NFCI.
Place all code corresponding to a run-time check in one place.
Previously we generated some code, then proceeded to a next check, then
finished the code for the first check (like splitting blocks and
generating branches). Now the code for generating a check is
self-contained.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241741 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:47:59 +00:00
Michael Zolotukhin
f26da26d05 [LoopVectorizer] Remove redundant variables PastOverflowCheck and OverflowCheckAnchor. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241740 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:47:56 +00:00
Michael Zolotukhin
ca6e363f1d [LoopVectorizer] Move some code around to ease further refactoring. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241739 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:47:53 +00:00
Michael Zolotukhin
a8e8640a65 [LoopVectorizer] Remove redundant variable LastBypassBlock. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241738 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:47:47 +00:00
Alex Lorenz
f67f2c25fe MIR Parser: Remove redundant TODO comment. NFC.
This TODO comment has been redundant since r240474.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241737 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:30:21 +00:00
Alex Lorenz
03dcd3c6ef MIR Serialization: Serialize the 'killed' register machine operand flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241734 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:23:34 +00:00
Diego Novillo
afab5f8c17 Add missing dependency to Hexagon target.
A recent patch added calls to isInstructionTriviallyDead without the
corresponding dependency on TransformUtils.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241731 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:13:37 +00:00
Rafael Espindola
576604b51b Use a raw_svector_ostream and simplify a loop. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241727 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:07:18 +00:00
Reid Kleckner
f8d3677531 [Win64] Only treat some functions as having the Win64 convention
All the usual X86 target-specific conventions are collapsed to the
normal Win64 convention, but the custom conventions like GHC and webkit
should not be.

Previously we would assume that the caller allocated 32 bytes of shadow
space for us, which is not how webkit_jscc or other custom conventions
are supposed to work.

Based on a patch by peavo@outlook.com.

Fixes PR24051.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241725 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 21:03:47 +00:00
Rafael Espindola
b13e877e27 Start adding support for writing archives in BSD format.
No support for the symbol table yet (but will hopefully add it today).
We always use the long filename format so that we can align the member,
which is an advantage of the BSD format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241721 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 20:47:32 +00:00
Alex Lorenz
31512fe6ce MIR Parser: Use source locations for MBB naming errors.
This commit changes the type of the field 'Name' in the struct
'yaml::MachineBasicBlock' from 'std::string' to 'yaml::StringValue'. This change
allows the MIR parser to report errors related to the MBB name with the proper
source locations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241718 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 20:22:20 +00:00
Sanjay Patel
ea64a51108 early exits -> less indenting; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241716 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 19:32:39 +00:00
Krzysztof Parzyszek
a307401165 [Hexagon] Implement commoning of GetElementPtr instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241714 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 19:22:28 +00:00
Peter Collingbourne
c783eb28f7 LibDriver: Fix output path inference.
The inferred output file name is based on the first input file, not the
first one with extension .obj. The output file was also being written to
the wrong directory; it needs to be written to whichever directory on the
libpath it was found in. This change fixes both issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241710 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 19:00:46 +00:00
Adam Nemet
b089d62c9a [LAA] Add missing debug output after r239285
r239285 ([LoopAccessAnalysis] Teach LAA to check the memory dependence
between strided accesses.) introduced a new case under
MemoryDepChecker::isDependent.  We normally have debug output for each
case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241707 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 18:47:38 +00:00
Reid Kleckner
f0999f3b02 [SEH] Ensure that empty __except blocks have their own BB
The 32-bit lowering assumed that WinEHPrepare had this invariant.
WinEHPrepare did it for C++, but not SEH. The result was that we would
insert calls to llvm.x86.seh.restoreframe in normal basic blocks, which
corrupted the frame pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241699 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 18:08:52 +00:00
Duncan P. N. Exon Smith
dfcac4b07a MC: Constify MCSubtargetInfo in getDeprecationInfo(), NFC
There's no reason to be able to mutate `MCSubtargetInfo` in
`getDeprecationInfo()`.  Constify the reference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241693 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 17:30:55 +00:00
Rafael Espindola
4ea795b15a Inline function into only use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241692 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 17:26:24 +00:00
Rafael Espindola
9ff2cd5417 Add a helper function to reduce a bit of code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241691 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 17:08:26 +00:00
Eli Bendersky
e933e5bd08 Cosmetic cleanups - NFC
Remove commented lines, trailing whitespace, etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241687 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 16:33:21 +00:00
James Y Knight
8eb1aaac9c [SPARC] Cleanup handling of the Y/ASR registers.
- Implement copying ASR to/from GPR regs.
- Mark ASRs as non-allocatable, so it won't try to arbitrarily use
  them inappropriately.
- Instead of inserting explicit WRASR/RDASR nodes in the MUL/DIV
  routines, just do normal register copies.
- Also...mark div as using Y, not just writing it.

Added a test case with some code which previously died with an
assertion failure (with -O0), or produced wrong code (otherwise).

(Third time's the charm?)

Differential Revision: http://reviews.llvm.org/D10401

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241686 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 16:25:12 +00:00
Rafael Espindola
cf8f6a296f Use a range loop. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241685 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 16:16:15 +00:00
Krzysztof Parzyszek
e7f45f66a7 [Hexagon] Generate "insert" instructions more aggressively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:47:34 +00:00
Krzysztof Parzyszek
5d447e9c2a Revert 241681: causes Windows builds to fail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241682 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:34:13 +00:00
Krzysztof Parzyszek
ea2273d00c [Hexagon] Generate "insert" instructions more aggressively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241681 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:22:27 +00:00
Silviu Baranga
8bde857088 [LAA] Merge memchecks for accesses separated by a constant offset
Summary:
Often filter-like loops will do memory accesses that are
separated by constant offsets. In these cases it is
common that we will exceed the threshold for the
allowable number of checks.

However, it should be possible to merge such checks,
sice a check of any interval againt two other intervals separated
by a constant offset (a,b), (a+c, b+c) will be equivalent with
a check againt (a, b+c), as long as (a,b) and (a+c, b+c) overlap.
Assuming the loop will be executed for a sufficient number of
iterations, this will be true. If not true, checking against
(a, b+c) is still safe (although not equivalent).

As long as there are no dependencies between two accesses,
we can merge their checks into a single one. We use this
technique to construct groups of accesses, and then check
the intervals associated with the groups instead of
checking the accesses directly.

Reviewers: anemet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10386

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241673 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 09:16:33 +00:00
Simon Pilgrim
796a06d4eb [X86][SSE] Added (V)ROUNDSD + (V)ROUNDSS stack folding support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241671 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 08:07:57 +00:00
Karthik Bhat
d9dffa6b3c Allow constfolding of llvm.sin.* and llvm.cos.* intrinsics
This patch const folds llvm.sin.* and llvm.cos.* intrinsics whenever feasible.

Differential Revision: http://reviews.llvm.org/D10836



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241665 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 03:55:47 +00:00
Mehdi Amini
7bcdaa6978 Remove IsLittleEndian from TargetLowering and redirect to DataLayout
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11017

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241655 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 01:00:38 +00:00
Mehdi Amini
564bfad782 Redirect DataLayout from TargetMachine to Module in SjLjEHPrepare
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11009

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241654 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 01:00:31 +00:00
Reid Kleckner
39ee70ca76 [WinEH] Make llvm.x86.seh.restoreframe work for stack realignment prologues
The incoming EBP value points to the end of a local stack allocation, so
we can use that to restore ESI, the base pointer. Once we do that, we
can use local stack allocations. If we know we need stack realignment,
spill the original frame pointer in the prologue and reload it after
restoring ESI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241648 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:45:58 +00:00
Mehdi Amini
c845b4d7be Redirect DataLayout from TargetMachine to Module in StackProtector
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11010

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241646 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:38:49 +00:00
Alex Lorenz
aa0d6db1e7 MIR Printer: Use a module slot tracker to print global address operands. NFC.
This commit adopts the 'ModuleSlotTracker' class, which was surfaced in r240842,
to print the global address operands. This change ensures that the slot tracker
won't have to be recreated every time a global address operand is printed,
making the MIR printing more efficient.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241645 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:27:53 +00:00
Reid Kleckner
4fe74caa61 [WinEH] Add localaddress intrinsic instead of using frameaddress
Clang uses this for SEH finally. The new intrinsic will produce the
right value when stack realignment is required.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241643 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:23:03 +00:00
Arnold Schwaighofer
39fe55270a Add more nvcasts
Tim Northover has told me that they can occur when the compiler cleverly
constructs constants - as demonstrated in the test case.

rdar://21703486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241641 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 23:13:18 +00:00
Dan Gohman
8ef6f1e24b [WebAssembly] Set the scheduling preference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 22:38:06 +00:00
Reid Kleckner
8f32e5f0d6 Rename llvm.frameescape and llvm.framerecover to localescape and localrecover
Summary:
Initially, these intrinsics seemed like part of a family of "frame"
related intrinsics, but now I think that's more confusing than helpful.
Initially, the LangRef specified that this would create a new kind of
allocation that would be allocated at a fixed offset from the frame
pointer (EBP/RBP). We ended up dropping that design, and leaving the
stack frame layout alone.

These intrinsics are really about sharing local stack allocations, not
frame pointers. I intend to go further and add an `llvm.localaddress()`
intrinsic that returns whatever register (EBP, ESI, ESP, RBX) is being
used to address locals, which should not be confused with the frame
pointer.

Naming suggestions at this point are welcome, I'm happy to re-run sed.

Reviewers: majnemer, nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11011

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241633 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 22:25:32 +00:00
Sanjay Patel
dd5fd545b1 fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241629 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 21:31:54 +00:00
Alex Lorenz
78bc2545c9 MIR Serialization: Serialize the 'dead' register machine operand flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241624 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 20:34:53 +00:00
Mehdi Amini
298a718c94 Redirect DataLayout from TargetMachine to Module in SelectionDAG
Summary:
SelectionDAG itself is not invoking directly the DataLayout in the
TargetMachine, but the "TargetLowering" class is still using it. I'll
address it in a following commit.

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11000

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241618 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 19:07:19 +00:00
David Majnemer
0148a4c854 Revert "Revert r241570, it caused PR24053"
This reverts commit r241602.  We had a latent bug in SCCP where we would
make a basic block empty and then proceed to ask questions about it's
terminator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241616 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:49:41 +00:00
Mehdi Amini
a77796487b Redirect DataLayout from TargetMachine to Module in GlobalMerge
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10987

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241615 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:49:25 +00:00
Mehdi Amini
d888ac430d Redirect DataLayout from TargetMachine to Module in CodeGen Prepare
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10986

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241614 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:45:17 +00:00
Mehdi Amini
26a2a4b4ed Redirect DataLayout from TargetMachine to Module in FastISel
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10985

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241613 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:39:02 +00:00
Arnold Schwaighofer
f869ca86f1 Add a pattern for a nvcast from v2f64 -> v4f32
Since the NvCast is generated by the selection process the concerns about
endianess and bit reversal don't apply.

rdar://21703486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:31:55 +00:00
Mehdi Amini
33c4d685e3 Redirect DataLayout from TargetMachine to Module in MachineFunction
Summary:
This change is part of a series of commits dedicated to have a
single DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10984

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241610 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:20:57 +00:00
Reid Kleckner
d0c71cfdf6 Use default member initializers to deduplicate code in X86MachineFunctionInfo, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241609 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 18:12:06 +00:00
Rafael Espindola
51652580f4 Fix the -DBUILD_SHARED_LIBS=ON build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241608 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 17:48:00 +00:00
Alex Lorenz
ddc6f0a433 MIR Parser: wrap 'MBBSlots' from the MI parsing functions in a struct. NFC.
This commit modifies the interface for the machine instruction parsing
functions by wrapping the parameter 'MBBSlots' in a new structure called
'PerFunctionMIParsingState'. This change is useful as in the future I will be
able to pass new parameters to the machine instruction parser just by modifying
the 'PerFunctionMIParsingState' structure instead of adding a new parameter to
each function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241607 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 17:46:43 +00:00
Rafael Espindola
7b7c81cd35 Delete UnknownAddress. It is a perfectly valid symbol value.
getSymbolValue now returns a value that in convenient for most callers:
* 0 for undefined
* symbol size for common symbols
* offset/address for symbols the rest

Code that needs something more specific can check getSymbolFlags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241605 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 17:12:59 +00:00
Rafael Espindola
9327084f92 Simplify by passing in the section of the symbol. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241603 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 16:45:55 +00:00
Nico Weber
1a2abd4a90 Revert r241570, it caused PR24053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241602 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 16:42:50 +00:00
Krzysztof Parzyszek
70bb40bd17 [Hexagon] Fix unused variable warnings in NDEBUG build caused by r241595
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241600 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 16:02:11 +00:00
Reid Kleckner
db38d7657a [WinEH] Add a report_fatal_error for 32-bit stack realignment
This type of prologue isn't supported yet. Implementing it should be a
matter of copying the adjusted incoming EBP into ESI (the base pointer)
instead of EBP.  The original EBP can be saved and restored from other
memory afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241597 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 15:47:29 +00:00
Krzysztof Parzyszek
41e59a6d7b [Hexagon] Implement bit-tracking facility with specifics for Hexagon
This includes code that is intended to be target-independent as well
as the Hexagon-specific details. This is just the framework without
any users.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241595 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 15:16:42 +00:00
Rafael Espindola
9ca3a03969 Common symbols don't have a value.
At least not in the interface exposed by ObjectFile. This matches what ELF and
COFF implement.

Adjust existing code that was expecting them to have values. No overall
functionality change intended.

Another option would be to change the interface and the ELF and COFF
implementations to say that the value of a common symbol is its size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241593 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 15:05:09 +00:00
Sanjay Patel
08c4cbeeae use range-based for loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241592 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 15:03:53 +00:00
Rafael Espindola
8b3aaabd30 Common symbols are not undefined, at least for ObjectFile.
They are implemented like that in some object formats, but for the interface
provided by lib/Object, SF_Undefined and SF_Common are different things.

This matches the ELF and COFF implementation and fixes llvm-nm for MachO.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241587 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 14:26:39 +00:00
Rafael Espindola
6b24d0a9a7 Simplify, NFC.
In these two contexts we really just want the raw n_value. No need to use
getSymbolValue which checks for special cases where, semantically, the symbol
has no value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241584 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 13:58:32 +00:00
David Majnemer
2822246ece [IR] Make getFirstNonPHI return null if the BB is empty
getFirstNonPHI's documentation states that it returns null if there is
no non-PHI instruction.  However, it instead returns a pointer to the
end iterator.  The implementation of getFirstNonPHI claims that
dereferencing the iterator will result in an assertion failure but this
doesn't occur.  Instead, machinery like getFirstInsertionPt will attempt
to isa<> this invalid memory which results in unpredictable behavior.
Instead, make getFirst* return null if no such instruction exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241570 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 09:15:29 +00:00
Denis Protivensky
2b4a535b70 Fix gcc warnings of different enum and non-enum types in ternaries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241567 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 07:48:48 +00:00
Akira Hatanaka
a744879a65 [ARM] Define a subtarget feature and use it to decide whether long calls should
be emitted.

This is needed to enable ARM long calls for LTO and enable and disable it on a
per-function basis.

Out-of-tree projects currently using EnableARMLongCalls to emit long calls
should start passing "+long-calls" to the feature string (see the changes made
to clang in r241565).

rdar://problem/21529937

Differential Revision: http://reviews.llvm.org/D9364


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2015-07-07 06:54:42 +00:00
Alex Lorenz
d0ef9f3115 MIR Parser: Verify the implicit machine register operands.
This commit verifies that the parsed machine instructions contain the implicit
register operands as specified by the MCInstrDesc. Variadic and call
instructions aren't verified.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10781


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241537 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 02:08:46 +00:00
Juergen Ributzka
b062a9b411 [StackMap Liveness] Calling the base class' getAnalysisUsage method. NFCI.
Calling into the base class' getAnalysisUsage method after we did our pass
specific modifications. This shouldn't really matter since this is the last
pass in the pipeline anyways.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241536 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 02:05:18 +00:00
Juergen Ributzka
083b791eaf [StackMap Liveness] No need to cache the MachineFunction. NFC.
Don't cache the MachineFunction in the pass and range'ify some loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241535 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 02:05:15 +00:00
Benjamin Kramer
32f3dc455b [Triple] Add a helper to switch between big/little endian variants
This will be used from clang's driver.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241527 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 23:58:14 +00:00
Sanjoy Das
0b1bc70dbf [FaultMaps] Add statistic to count the # of implicit null checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241521 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 23:32:10 +00:00
Alex Lorenz
4ec0f60807 MIR Serialization: Serialize the implicit register flag.
This commit serializes the implicit flag for the register machine operands. It
introduces two new keywords into the machine instruction syntax: 'implicit' and
'implicit-def'. The 'implicit' keyword is used for the implicit register
operands, and the 'implicit-def' keyword is used for the register operands that
have both the implicit and the define flags set.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10709


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241519 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 23:07:26 +00:00
Eric Christopher
ddf4c989ee Remove JumpInstrTableInfo.h as it is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241517 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 22:55:20 +00:00
Simon Pilgrim
315fd86400 [X86][AVX] Add support for shuffle decoding of vperm2f128/vperm2i128 with zero'd lanes
The vperm2f128/vperm2i128 shuffle mask decoding was not attempting to deal with shuffles that give zero lanes. This patch fixes this so that the assembly printer can provide shuffle comments.

As this decoder is also used in X86ISelLowering for shuffle combining, I've added an early-out to match existing behaviour. The hope is that we can add zero support in the future, this would allow other ops' decodes (e.g. insertps) to be combined as well.

Differential Revision: http://reviews.llvm.org/D10593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241516 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 22:46:46 +00:00
Sanjay Patel
75a2ce3271 [x86] extend machine combiner reassociation optimization to SSE scalar adds
Extend the reassociation optimization of http://reviews.llvm.org/rL240361 (D10460)
to SSE scalar FP SP adds in addition to AVX scalar FP SP adds.

With the 'switch' in place, we can trivially add other opcodes and test cases in
future patches.

Differential Revision: http://reviews.llvm.org/D10975



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241515 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 22:35:29 +00:00
Simon Pilgrim
6970be03d1 [X86][SSE] Vectorized i64 uniform constant SRA shifts
This patch adds vectorization support for uniform constant i64 arithmetic shift right operators.

Differential Revision: http://reviews.llvm.org/D9645

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241514 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 22:35:19 +00:00
JF Bastien
610992baca WebAssembly: add some TODO
Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D10971

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241513 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 21:41:59 +00:00
Reid Kleckner
e23370402c [WinEH] Insert the EH code load before the block terminator
The previous code put the load after the terminator, leading to invalid
IR and downstream crashes. This caused http://crbug.com/506446.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241509 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 21:13:43 +00:00
Simon Pilgrim
3ecdd44e5d [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructions
This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it.

As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions.

From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level.

Differential Revision: http://reviews.llvm.org/D10146

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241508 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 20:46:41 +00:00
Simon Pilgrim
ecb00f403c [X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN opcodes and remove the X86 implementation
With the completion of D9746 there is now a common implementation of integer signed/unsigned min/max nodes, removing the need for the equivalent X86 specific implementations.

This patch removes the old X86ISD nodes, legalizes the relevant SSE2/SSE41/AVX2/AVX512 instructions for the ISD versions and converts the small amount of existing X86 code.

Differential Revision: http://reviews.llvm.org/D10947

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241506 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 20:30:47 +00:00
Quentin Colombet
4bde0fa367 [TwoAddressInstructionPass] Rename a variable to match the coding style.
Spot by Bruno.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241505 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 20:12:54 +00:00
Reid Kleckner
f0101b2d60 [llvm-extract] Drop comdats from declarations
The verifier rejects comdats on declarations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241483 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 18:48:02 +00:00
Alex Lorenz
edfa571cbd llc: Add a 'run-pass' option.
This commit adds a 'run-pass' option to llc, which instructs the compiler to run
one specific code generation pass only.

Llc already has the 'start-after' and the 'stop-after' options, and this new
option complements the other two by making it easier to write tests that want
to invoke a single pass only.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10776


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241476 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 17:44:26 +00:00
Matt Arsenault
b560f9ca2f AMDGPU: Run SIInsertWaits as pre-emit pass
Running this after the scheduler enables scheduling
waits later so other ALU instructions can run while
this would be waiting.

When combined with enabling the post-RA scheduler, this
gives about a ~20% improvement on sgemm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241473 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 17:02:20 +00:00
Daniel Sanders
96fe9196e9 Change the last few internal StringRef triples into Triple objects.
Summary:
This concludes the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

At this point, the StringRef-form of GNU Triples should only be used in the
public API (including IR serialization) and a couple objects that directly
interact with the API (most notably the Module class). The next step is to
replace these Triple objects with the TargetTuple object that will represent
our authoratative/unambiguous internal equivalent to GNU Triples.

Reviewers: rengolin

Subscribers: llvm-commits, jholewinski, ted, rengolin

Differential Revision: http://reviews.llvm.org/D10962

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241472 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:56:07 +00:00
Adrian Prantl
9d4ce7c110 DIBuilder: Don't rauw null pointers with empty arrays in finalize().
This makes the IR a little easier to read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241470 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:36:02 +00:00
Daniel Sanders
24a1fec2a7 Where Triple has a suitable predicate, use it rather than the enum values. NFC.
Reviewers: mcrosier

Subscribers: llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10960

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241469 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:33:18 +00:00
Sanjay Patel
a71390ff3b use range-based for loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241468 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:27:35 +00:00
Teresa Johnson
3d41fcb3da Resubmit "Add new EliminateAvailableExternally module pass" (r239480)
This change includes a fix for https://code.google.com/p/chromium/issues/detail?id=499508#c3,
which required updating the visibility for symbols with eliminated definitions.

--Original Commit Message--

Add new EliminateAvailableExternally module pass, which is performed in
O2 compiles just before GlobalDCE, unless we are preparing for LTO.

This pass eliminates available externally globals (turning them into
declarations), regardless of whether they are dead/unreferenced, since
we are guaranteed to have a copy available elsewhere at link time.
This enables additional opportunities for GlobalDCE.

If we are preparing for LTO (e.g. a -flto -c compile), the pass is not
included as we want to preserve available externally functions for possible
link time inlining. The FE indicates whether we are doing an -flto compile
via the new PrepareForLTO flag on the PassManagerBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241466 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:22:42 +00:00
Adrian Prantl
e91246ae8c Use an early exit in DIBuilder::finalize() to improve readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241465 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:22:12 +00:00
Sanjay Patel
98d447c206 use range-based for loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241463 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:19:14 +00:00
Matt Arsenault
6fe7acaaf8 AMDGPU/SI: Add debugging subtarget feature for DS offsets
We don't have a good way to detect most situations where
DS offsets are usable on SI, so add an option to force using
them even if unsafe for debugging performance problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241462 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:01:58 +00:00