Commit Graph

18004 Commits

Author SHA1 Message Date
Eric Christopher
29aeed1bf8 Fix the bfi handling for or (and a mask) (and b mask). We need the two
masks to match inversely for the code as is to work. For the example given
we actually want:

bfi r0, r2, #1, #1

not #0, however, given the way the pattern is written it's not possible
at the moment.

Fixes rdar://9177502


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26 01:21:03 +00:00
Johnny Chen
a2755b9829 Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
Also add some test cases.

rdar://problem/9189829


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 22:19:07 +00:00
Johnny Chen
abeea57639 DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
rdar://problem/9182892


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 19:35:37 +00:00
Johnny Chen
ceceabd4b1 Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
t2LDREX/t2STREX instructions.  Add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 18:29:49 +00:00
Benjamin Kramer
ef7b8d9e5a Add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:32:40 +00:00
Johnny Chen
6c3891067b Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
rdar://problem/9184053


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:31:16 +00:00
Johnny Chen
f14d5cf33a Also need to handle invalid imod values for CPS2p.
rdar://problem/9186136


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:03:12 +00:00
Jakob Stoklund Olesen
eb5067e0d9 Ignore special ARM allocation hints for unexpected register classes.
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 01:48:18 +00:00
Johnny Chen
a7078c4f27 Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 01:09:48 +00:00
Matt Beaumont-Gay
1866af4a98 Suppress an unused variable warning in -asserts builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:05:48 +00:00
Johnny Chen
c39b6271be Handle the added VBICiv*i* NEON instructions, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:04:39 +00:00
Johnny Chen
8cb988686d Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128241 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:42:55 +00:00
Johnny Chen
9091bf25d9 T2 Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:36:56 +00:00
Benjamin Kramer
83ccbff84f Plug a leak in the arm disassembler and put the tests back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
505f3cd296 Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:04:58 +00:00
Johnny Chen
e6d69e7dbe ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 20:42:48 +00:00
Jim Grosbach
d31d304f83 Clean up assembly statement separator support.
The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:46:34 +00:00
Johnny Chen
b4ac342ea0 The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:40:38 +00:00
Johnny Chen
ce1868b21c Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 17:04:22 +00:00
NAKAMURA Takumi
a2e0762fae Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
FIXME: Some cleanups would be needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 07:07:00 +00:00
Evan Cheng
d700617193 Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.

rdar://9125354


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 06:20:03 +00:00
Johnny Chen
e4000595fb CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.
Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)

Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

Before:
	cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!

After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 02:24:36 +00:00
Johnny Chen
3d793962be Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 01:40:42 +00:00
Johnny Chen
571f290376 STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
We now tag them as IndexModePost.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 01:07:26 +00:00
Johnny Chen
2abc9d2444 The r128103 fix to cope with the removal of addressing modes from the MC instructions
were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 00:28:38 +00:00
Devang Patel
36dca60f5c Enable GlobalMerge on darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 23:34:19 +00:00
Andrew Trick
f6c39412dd Revert r128175.
I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 23:11:02 +00:00
Evan Cheng
2c33915628 Cmp peephole optimization isn't always safe for signed arithmetics.
int tries = INT_MAX;    
while (tries > 0) {
      tries--;
}

The check should be:
        subs    r4, #1
        cmp     r4, #0
        bgt     LBB0_1

The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.

rdar://9172742


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:52:04 +00:00
Andrew Trick
d8fa01fbd7 Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.
(target-specific branchless method for double-width relational comparisons on x86)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:16:02 +00:00
Owen Anderson
741ad15e26 The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.
This fixes 464.h264ref with the integrated assembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:03:44 +00:00
Justin Holewinski
d662576671 PTX: Improve support for 64-bit addressing
- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 16:58:51 +00:00
Johnny Chen
c59c87c322 For ARM Disassembler, start a newline to dump the opcode and friends for an instruction.
Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 23:49:46 +00:00
Johnny Chen
27c6baeca2 LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
We now tag them as IndexModePost.

This fixed http://llvm.org/bugs/show_bug.cgi?id=9530.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 22:28:49 +00:00
Eli Friedman
97ab5803df A bit more analysis of a memset-related README entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:49:53 +00:00
Johnny Chen
758df29741 A8.6.399 VSTM:
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions.  Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.

Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:00:10 +00:00
Eric Christopher
7244d7cbce Migrate the fix in r128041 to ARM's fastisel support as well.
Fixes rdar://9169640 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 19:39:17 +00:00
Bruno Cardoso Lopes
026a42b170 Change MRC and MRC2 instructions to model the output register properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 15:06:24 +00:00
Che-Liang Chiou
5e0872e099 ptx: add analyze/insert/remove branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 14:12:00 +00:00
Matt Beaumont-Gay
ddb657c63d Avoid -Wunused-variable in -asserts builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 00:37:28 +00:00
Dan Gohman
b55d6b6a7e Fix fast-isel address mode folding to avoid folding instructions
outside of the current basic block. This fixes PR9500, rdar://9156159.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 00:04:35 +00:00
Bill Wendling
a5c177e70a We need to pass the TargetMachine object to the InstPrinter if we are printing
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.

This is part of a work-in-progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 04:13:46 +00:00
Eli Friedman
ddfa02ba24 This README entry was fixed recently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 01:33:03 +00:00
Evan Cheng
485fafc840 Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 01:19:09 +00:00
Daniel Dunbar
7a90e04fc7 Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
to canonicalize IR", it broke a lot of things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 21:47:14 +00:00
Evan Cheng
ae16d6b972 SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
  switch(x) {
  case 1: return f1();
  case 2: return f2();
  case 3: return f3();
  case 4: return f4();
  case 5: return f5();
  case 6: return f6();
  }
}

=>
LBB0_2:                                 ## %sw.bb
  callq   _f1
  popq    %rbp
  ret
LBB0_3:                                 ## %sw.bb1
  callq   _f2
  popq    %rbp
  ret
LBB0_4:                                 ## %sw.bb3
  callq   _f3
  popq    %rbp
  ret

This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:

sw.bb7:                                           ; preds = %entry
  %call8 = tail call i32 @f5() nounwind
  br label %return
sw.bb9:                                           ; preds = %entry
  %call10 = tail call i32 @f6() nounwind
  br label %return
return:
  %retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
  ret i32 %retval.0

This allows codegen to generate better code like this:

LBB0_2:                                 ## %sw.bb
        jmp     _f1                     ## TAILCALL
LBB0_3:                                 ## %sw.bb1
        jmp     _f2                     ## TAILCALL
LBB0_4:                                 ## %sw.bb3
        jmp     _f3                     ## TAILCALL

rdar://9147433


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 17:17:39 +00:00
Nadav Rotem
06cc324b9d Add support for legalizing UINT_TO_FP of vectors on platforms which do
not have native support for this operation (such as X86).
The legalized code uses two vector INT_TO_FP operations and is faster
than scalarizing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 13:09:10 +00:00
Johnny Chen
94dad03a96 Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand.  Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 01:16:20 +00:00
Owen Anderson
0082830cb2 Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 22:50:18 +00:00
Evan Cheng
3f30af3f45 Match a few more obvious patterns to revsh. rdar://9147637.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127913 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 21:52:42 +00:00
Eli Friedman
b6192d2a9f Revert r127852; it's apparently causing an ICE on mingw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 21:12:29 +00:00