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16287 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
635127a8c6 Constrain the offset register to a *_NOSP register class when inserting LEA 
instructions.

This unbreaks the machine code verifier and fixes PR8317.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:07:26 +00:00
Chris Lattner
78266110bf add the pattern operator to match to X86TypeInfo, use this to 
convert AND64ri32 to use BinOpRI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8f42a19fb0 Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass. 
This function looks like it is about ready to be generated by TebleGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 23:56:46 +00:00
Jim Grosbach
fa7fb64fad remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:46:47 +00:00
Jason W Kim
def9ac48b7 First in a sequence of ARM/MC/*ELF* specific work. 
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:36:46 +00:00
Jim Grosbach
3c38f96af2 Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:01:26 +00:00
Jim Grosbach
1d6111c5ac Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:36:43 +00:00
Jim Grosbach
35636281c7 Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed 
"lane" operand modifier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:22:32 +00:00
Jim Grosbach
65dc30340c Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be 
pseudo instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:16:16 +00:00
Jim Grosbach
7cd2729d2a Add a 'pattern' arg to the ARM PseudoNeonI class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 20:36:55 +00:00
Jim Grosbach
4dea941c8d target operand flag values aren't a bitmask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 16:51:55 +00:00
Evan Cheng
a0792de66c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 06:27:31 +00:00
Chris Lattner
b2fc409827 enhance X86TypeInfo to include information about the encoding and 
operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115752 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:55:42 +00:00
Chris Lattner
3ab0b59aad add a class for _REV nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115748 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:35:22 +00:00
Chris Lattner
08808f9733 sink more intelligence into the ITy base class. Now it knows 
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:28:38 +00:00
Chris Lattner
44402c0701 refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:20:57 +00:00
Chris Lattner
da4b361726 with tblgen suitably extended, we can now get the load node from typeinfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 04:58:43 +00:00
Chris Lattner
417b54354b lets go all meta and define new X86 type wrappers that declare the associated 
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115727 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:45:24 +00:00
Chris Lattner
ff27af206e introduce a new BinOpRM class and use it to factor AND*rm. This points out 
that I need a heavier handed approach to get ultimate factorization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:30:49 +00:00
Chris Lattner
c7252ce743 remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places 
where !cast is just as short.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115722 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:19:21 +00:00
Chris Lattner
78caacc226 replace stuff like: 
let AsmString = !strconcat(
                     !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
                     !strconcat("\t", asm));

with:

  let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);

:)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115720 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:05:18 +00:00
Chris Lattner
8d978a75b4 allow !strconcat to take more than two operands to eliminate 
!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115719 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:58:18 +00:00
Eric Christopher
e540a6f94a Comment out fastisel debugging message. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115717 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:50:58 +00:00
Chris Lattner
20b2499a7c associate the instruction suffix letter with the integer gpr 
register class, and use this to simplify use of BinOpRR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115716 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:43:04 +00:00
Chris Lattner
e00047c906 introduce a new BinOpRR class, and convert 4 and instructions to use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115715 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:32:05 +00:00
Eric Christopher
022b7fb045 Random cleanup and make the intermediate register in fptosi a 
32-bit fp reg, not 64-bit.

Fixes SingleSource.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115711 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:13:24 +00:00
Chris Lattner
6dbbff9172 Move cmov pseudo instructions to InstrCompiler, 
convert all the rest of the cmovs to the multiclass,
with good results:

 X86InstrCMovSetCC.td |  598 +--------------------------------------------------
 X86InstrCompiler.td  |   61 +++++
 2 files changed, 77 insertions(+), 582 deletions(-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:09:10 +00:00
Chris Lattner
25cbf504fe Use #NAME# to have the CMOV multiclass define things with the same names as before 
(e.g. CMOVBE16rr instead of CMOVBErr16).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:00:14 +00:00
Chris Lattner
df72eaef3d enhance tblgen to support anonymous defm's, use this to 
simplify the X86 CMOVmr's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:51:56 +00:00
Chris Lattner
286997c745 convert cmov mr patterns to use a multipattern. Death to redundancy 
and verbosity


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115701 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:42:54 +00:00
Chris Lattner
d350e4757e switch CMOVBE to the multipattern: 
21 insertions(+), 53 deletions(-)

Moar change coming before I switch the rest.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:23:58 +00:00
Chris Lattner
e583c892d8 fix a bug I introduced in r115669, which ended up with MOV64mr_TC 
not getting marked as mayStore.  This fixes llvm-gcc bootstrap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:16:48 +00:00
Chris Lattner
b484213d1b add a multiclass for cmov's, but don't start using it yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:01:02 +00:00
Chris Lattner
d244699067 use a multipattern to define setcc instructions: 
X86InstrCMovSetCC.td |  200 ++++++---------------------------------------------
 1 file changed, 27 insertions(+), 173 deletions(-)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115689 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:34:29 +00:00
Chris Lattner
2c383d8c4d move SETB pseudos into the same place in InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:18:04 +00:00
Chris Lattner
508fc4708b Replace a gross hack (the MOV64ri_alt instruction) with a slightly less 
gross hack (having the asmmatcher handle the alias).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115685 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:09:45 +00:00
Chris Lattner
748a2fe917 distribute the rest of the contents of X86Instr64bit.td out to 
the right places.  X86Instr64bit.td now dies, long live x86-64!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115669 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:49:15 +00:00
Chris Lattner
10701928ff move the rest of the simple 64-bit arithmetic into InstrArithmetic.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115663 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:35:37 +00:00
Chris Lattner
5bbbcdb1d8 continue moving 64-bit stuff into X86InstrArithmetic.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:23:31 +00:00
Jim Grosbach
d86609fca4 Increase the number of bits used internally by the ARM target to represent the 
addressing mode from four to five.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115645 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 18:14:55 +00:00
Chris Lattner
64227940e7 move 64-bit add and adc to InstrArithmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115632 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:59:08 +00:00
Chris Lattner
c7d4655b57 rewrote two addr constraints so that they are only set, not set and then nestedly cleared. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115631 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:52:25 +00:00
Chris Lattner
6367cfc470 split the 32-bit integer arithmetic instructions out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115627 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:39:12 +00:00
Chris Lattner
5249ff34fb integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 07:13:35 +00:00
Chris Lattner
5f58e84af8 move 32-bit shift and rotates out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115607 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 07:00:12 +00:00
Chris Lattner
2c065e1c86 add new file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115606 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:52:35 +00:00
Chris Lattner
8917cd3d67 move sign and zero extensions out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115605 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:52:26 +00:00
Chris Lattner
d8cc2722a4 move some instructions from Instr64Bit -> InstrInfo. 
bswap32 doesn't read eflags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:47:35 +00:00
Chris Lattner
5673e1d314 move CMOV_FR32 and friends to InstrCompiler, since they are 
pseudo instructions.

Move POPCNT to InstrSSE since they are SSE4 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:41:40 +00:00
Chris Lattner
41efbfaa66 move various pattern matching support goop out of X86Instr64Bit, to live 
with the 32-bit stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:37:31 +00:00
Chris Lattner
35649fc3dd split conditional moves and setcc's out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:33:16 +00:00
Chris Lattner
d3f033d969 move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:27:48 +00:00
Chris Lattner
010496c6a7 move the atomic pseudo instructions out to X86InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115599 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:22:35 +00:00
Chris Lattner
8af88ef157 move more pseudo instructions out to X86InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:10:16 +00:00
Chris Lattner
d071b83b5d move VMX instructions out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115597 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:06:53 +00:00
Chris Lattner
87be16a9e1 continue moving stuff out to X86InstrSystem.td. Move 
control flow stuff out to X86InstrControl.td.  Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:04:14 +00:00
Michael J. Spencer
f000a7a212 fix MSVC 2010 build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:00:43 +00:00
Michael J. Spencer
2bbb769091 Cleanup Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115593 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:00:33 +00:00
Chris Lattner
434c7cb8a1 refactor .td files a bit, moving system instructions out to X86InstrSystem.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115591 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 05:32:15 +00:00
Jim Grosbach
33caa07cc5 Re-apply r115363 and r115366 now that r115525 has removed the un-needed header 
that caused the circular dependencies on Linux.

Built OK for me on OSX and Linux (Ubuntu) with configure/make and CMake. Will
keep an eye on the bots....

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 00:34:11 +00:00
Bill Wendling
6cf6c79e82 The pshufw instruction came about in MMX2 when SSE was introduced. Don't place 
it in with the SSSE3 instructions.

Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115552 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-04 20:24:01 +00:00
Jim Grosbach
c5ccf73dee Remove unneeded header 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115525 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-04 17:53:40 +00:00
Jan Wen Voung
083cf1574f Add hook in MCSection to decide when to use "optimized nops", for each 
section kind. Previously, optimized nops were only used for MachO.
Also added tests for ELF and COFF.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115523 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-04 17:32:41 +00:00
Anton Korobeynikov
e7beda183d va_args support for Win64. 
Patch by Cameron!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 22:52:07 +00:00
Anton Korobeynikov
6af61ca789 Properly emit stack probe on win64 (for non-mingw targets). 
Based on the patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115479 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 22:02:38 +00:00
Eli Friedman
d32d85e5ba Add 3DNowA instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115477 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 20:23:13 +00:00
Chris Lattner
591d76ea5a the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 19:09:13 +00:00
Rafael Espindola
0febc4657b Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do 
so and also change X86 for consistency.

Investigating if this can be improved a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 18:59:45 +00:00
Chris Lattner
cc07d7116a add support for the prefetch/prefetchw instructions, move femms into 
the right file.  The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115468 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 18:42:30 +00:00
Chris Lattner
f132fa0e74 what the heck, add support for the rest of the 3dNow! binary operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 18:24:18 +00:00
Chris Lattner
548abfcbd6 Implement support for the bizarre 3DNow! encoding (which is unlike anything 
else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 18:08:05 +00:00
Evan Cheng
ec45f60cab Major changes to Cortex-A9 itinerary. 
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
   dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 02:03:59 +00:00
Chris Lattner
7330d97069 stub out a header to put 3dNow! instructions into. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115429 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 23:06:23 +00:00
Chris Lattner
d476914607 fix a regression introduced in r115243, in which the instruction 
backing int_x86_ssse3_pshuf_w got removed.  This caused PR8280.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115422 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 21:32:15 +00:00
Nick Lewycky
d0669493b8 Wind these directories back too. File adds and removes are properly represented 
in patches. :-(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 01:16:59 +00:00
Nick Lewycky
0e7fdf5f09 Continue reverting r115363. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115395 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 01:08:17 +00:00
Nick Lewycky
c57707dd87 Revert patches r115363 r115367 r115391 due to build breakage: 
llvm[2]: Updated LibDeps.txt because dependencies changed
llvm[2]: Checking for cyclic dependencies between LLVM libraries.
find-cycles.pl: Circular dependency between *.a files:
find-cycles.pl:   libLLVMMSP430AsmPrinter.a libLLVMMSP430CodeGen.a



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115393 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 01:06:42 +00:00
Jim Grosbach
0e69aff03a Update CMake files for recent AsmPrinter->InstPrinter changes. Can someone who 
is more familiar with CMake please review?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115391 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 00:39:56 +00:00
Eric Christopher
890dbbec57 Start on lowering global addresses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115390 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-02 00:32:44 +00:00
Jim Grosbach
443e625d8a PrintSpecial() can go away now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 23:27:48 +00:00
Eric Christopher
c9932f6f60 Stub out constant GV handling, fixes C++ eh tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 23:24:42 +00:00
Jim Grosbach
78890f41f4 Nuke the rest of the :comment references 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 23:21:38 +00:00
Jim Grosbach
adde5da638 Nuke a bunch of no-longer-needed comment-only asm strings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 23:09:33 +00:00
Jim Grosbach
7722980950 Now that the asmprinter itself isn't in the subdir, rename 'AsmPrinter' to 
'InstPrinter' to fall into line with the other MC-ized assembly printer
using targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 22:57:18 +00:00
Evan Cheng
055028215d Fix r115332: correctly model AGU / NEON mux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 22:52:29 +00:00
Owen Anderson
e3cc84a43d Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now, 
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 22:45:50 +00:00
Jim Grosbach
6314ef9e81 Move the asmprinter and MC lowering out of the AsmPrinter (soon to be 
InstPrinter) subdir

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115363 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 22:45:38 +00:00
Jim Grosbach
7ac1609a3b Rename the AsmPrinter directory to InstPrinter for those targets that have 
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 22:39:28 +00:00
Evan Cheng
ef0ccad725 Fix scheduling infor for vmovn and vshrn which I broke accidentially. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115354 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 21:48:06 +00:00
Evan Cheng
df9da6a033 Add operand cycles for vldr / vstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 21:40:30 +00:00
Eric Christopher
e6ca6771e3 Direct calls only for arm fast isel for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 21:33:12 +00:00
Evan Cheng
cae6a12a99 NEON scheduling info fix. vmov reg, reg are single cycle instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 20:50:58 +00:00
Eric Christopher
45547b844d Fix thinko on store instructions. Fixes test_indvars failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 20:46:04 +00:00
Owen Anderson
00d4f48168 Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115341 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 20:33:47 +00:00
Owen Anderson
aa9f0a57d0 Provide an option to restore old-style if-conversion heuristics for Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 20:28:06 +00:00
Evan Cheng
7c3423f413 Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115332 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 19:41:46 +00:00
Jim Grosbach
bffa1a5cf3 grammar 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 14:57:48 +00:00
Benjamin Kramer
b0f96facd6 Delete token *after* reading from it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 12:25:27 +00:00
Kalle Raiskila
8258135c90 Zap some redundant 'ori $?, $?, 0' from SPU. 
Also remove some code that died in the process.
One now non-existant ori is checked for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 09:20:01 +00:00
Eric Christopher
14df88282b Implement double return values in calls. Fixes 
SingleSource/Regression/C/casts.c.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115246 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 00:00:11 +00:00