Commit Graph

7734 Commits

Author SHA1 Message Date
Arnold Schwaighofer
2e750c12e9 ARM NEON: Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers.

The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract
the element from the vector instead.

radar://13191881

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 15:27:05 +00:00
Reed Kotler
8a20844e27 Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175486 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 03:56:57 +00:00
Reed Kotler
f801675207 Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 00:20:58 +00:00
Chad Rosier
69c65b0d93 Comment out the rdar number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 21:59:15 +00:00
Chad Rosier
848c25ddfa [fast-isel] Remove an invalid assert.
If the memcpy has an odd length with an alignment of 2, this would incorrectly
assert on the last 1 byte copy.
rdar://13202135

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 21:46:28 +00:00
Benjamin Kramer
98fbe27ac8 Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 20:55:12 +00:00
Vincent Lejeune
e3111964a0 R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 14:11:28 +00:00
Reed Kotler
bb01b3cb93 Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 05:43:03 +00:00
Reed Kotler
dabfebb5c6 Expand pseudo/macro BteqzT8SltX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 04:04:26 +00:00
Reed Kotler
a8601bb4ff Expand macro/pseudo BteqzT8CmpX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 03:06:29 +00:00
Reed Kotler
da4afa72f7 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 00:59:04 +00:00
Benjamin Kramer
5d0c7941cb Force a cpu for test. It failed on atom due to different scheduling decisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 18:26:11 +00:00
Jakub Staszak
f753480caa Replace "check:" wth "CHECK:".
Also fix one test by changing "vpermilps" to "vpshufd".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 12:16:56 +00:00
Bill Wendling
901d80065c Reinitialize the ivars in the subtarget so that they can be reset with the new features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 01:36:26 +00:00
Chad Rosier
b56606274d [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.
If the frame pointer is omitted, and any stack changes occur in the inline
assembly, e.g.: "pusha", then any C local variable or C argument references
will be incorrect.  

I pass no judgement on anyone who would do such a thing. ;)
rdar://13218191

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 01:25:28 +00:00
Bill Wendling
ba6867d0ce Temporary revert of 175320.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 23:22:32 +00:00
Bill Wendling
9be8b4fc92 Reinitialize the ivars in the subtarget.
When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 23:18:01 +00:00
Paul Redmond
86cdbc9c29 enable SDISel sincos optimization for GNU environments
- add sincos to runtime library if target triple environment is GNU
- added canCombineSinCosLibcall() which checks that sincos is in the RTL and
  if the environment is GNU then unsafe fpmath is enabled (required to
  preserve errno)
- extended sincos-opt lit test

Reviewed by: Hal Finkel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175283 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 18:45:18 +00:00
Tim Northover
1e8839302b AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 09:33:43 +00:00
Tim Northover
148ac534fc AArch64: refactor frame handling to use movz/movk for overlarge offsets.
In the near future litpools will be in a different section, which means that
any access to them is at least two instructions. This makes the case for a
movz/movk pair (if total offset <= 32-bits) even more compelling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 09:33:26 +00:00
Reed Kotler
5cf38fd763 Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 01:04:38 +00:00
Nadav Rotem
6cc4b8d1eb Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 18:28:52 +00:00
Weiming Zhao
7248451c43 Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 18:10:21 +00:00
Vincent Lejeune
7867885737 R600: Do not fold single instruction with more that 3 kcache read
It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175183 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 16:57:19 +00:00
Kristof Beyls
b1d081230e Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 14:46:12 +00:00
Elena Demikhovsky
60b3e18d67 Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).
Added a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 08:20:26 +00:00
Michel Danzer
d4addbe78a R600: Add lit tests for texture sampling instruction selection.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 07:43:51 +00:00
Andrew Trick
05fdb82535 Reapply "s/grep/FileCheck/ in some tests"
This reverts commit fd1335e982.

Use a triple this time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 03:45:08 +00:00
Andrew Trick
fd1335e982 Revert "s/grep/FileCheck/ in some tests"
This reverts commit 8b75e6bc35.

The FileCheck tests are not equivalent:

test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input
; CHECK: jmp init
         ^
<stdin>:1:2: note: scanning from here
 .section __TEXT,__text,regular,pure_instructions
 ^
<stdin>:13:2: note: possible intended match here
 jmp _init ## TAILCALL
 ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 03:00:57 +00:00
Weiming Zhao
c0c2816fb3 temporarily revert the patch due to some conflicts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 23:24:40 +00:00
Anshuman Dasgupta
666e0d3bc4 Hexagon: add support for predicate-GPR copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 22:56:34 +00:00
Tom Stellard
76308d8d28 R600: Add support for 128-bit parameters
NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 22:05:20 +00:00
Eli Bendersky
fa7c9efcd3 s/grep/FileCheck/ in some tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 22:00:37 +00:00
Eli Bendersky
8b75e6bc35 s/grep/FileCheck/ in some tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:46:38 +00:00
Weiming Zhao
3019fbbe6a Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:43:02 +00:00
Chad Rosier
5867302b16 [ms-inline asm] Fix up test case for non-Darwin platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:41:58 +00:00
Jyotsna Verma
f6563427c4 Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:38:46 +00:00
Chad Rosier
7b0bc3fe3e [ms-inline-asm] Add support for memory references that have non-immediate
displacements.
rdar://12974533


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 21:33:44 +00:00
Reed Kotler
6b9d461780 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 20:28:27 +00:00
David Peixotto
af7c042af1 PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 19:21:47 +00:00
Benjamin Kramer
f09e02f01a X86: Disable generation of rep;movsl when %esi is used as a base pointer.
This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.

Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 13:40:35 +00:00
Reed Kotler
8080696103 Make jumptables work for -static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 08:32:14 +00:00
Elena Demikhovsky
d29804f80d Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 08:02:04 +00:00
Eric Christopher
23571f4f2c Check i1 as well as i8 variables for 8 bit registers for x86 inline
assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 06:01:05 +00:00
Eric Christopher
a4e8694053 Finish obviously broken thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 06:01:00 +00:00
Paul Redmond
de53477c91 Fix the lit test added in r174972
Patch by: Kevin Schoedel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174974 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 16:07:27 +00:00
Jyotsna Verma
6b8d2026ba Hexagon: Add support to generate predicated absolute addressing mode
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 16:06:23 +00:00
Paul Redmond
5c97450df7 PR14562 - Truncation of left shift became undef
DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32))
into (shl i32 v, 32) into undef. To prevent this, check the shift count
against the final result size.

Patch by: Kevin Schoedel
Reviewed by: Nadav Rotem


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 15:21:21 +00:00
Justin Holewinski
7eacad03ef [NVPTX] Disable vector registers
Vectors were being manually scalarized by the backend.  Instead,
let the target-independent code do all of the work.  The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 14:18:49 +00:00
Arnold Schwaighofer
d9316dacf5 ARM NEON: Handle v16i8 and v8i16 reverse shuffles
Lower reverse shuffles to a vrev64 and a vext instruction instead of the default
legalization of storing and loading to the stack. This is important because we
generate reverse shuffles in the loop vectorizer when we reverse store to an
array.

  uint8_t Arr[N];
  for (i = 0; i < N; ++i)
    Arr[N - i - 1] = ...

radar://13171760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 01:58:32 +00:00