Anton Korobeynikov
2eeeff8371
Some bits of A9 scheduling: VFP
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:19:18 +00:00
Jakob Stoklund Olesen
fddb7667ca
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
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When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 03:10:20 +00:00
Jim Grosbach
1118b5e490
vml[as] are slow on 1136jf-s also.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01 00:13:43 +00:00
Jim Grosbach
7ec7a0e96b
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
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Re-commit. This time complete with testsuite updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 23:47:34 +00:00
Jim Grosbach
78e496e165
need to fix 'make check' tests first. revert for a moment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 23:34:05 +00:00
Jim Grosbach
bd17bc96bf
switch the flag for using NEON for SP floating point to a subtarget 'feature'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 23:32:19 +00:00
Jim Grosbach
6b2e8dc9a0
switch the use-vml[as] instructions flag to a subtarget 'feature'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 23:11:16 +00:00
Anton Korobeynikov
631379e79c
Add substarget feature for FP16
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:38 +00:00
David Goodwin
ebb5cb9216
Add ARMv6 itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18 18:39:57 +00:00
Anton Korobeynikov
f95215f551
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02 00:10:38 +00:00
David Goodwin
9843a93e83
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 22:19:57 +00:00
David Goodwin
471850ab84
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 21:46:35 +00:00
David Goodwin
0dad89fa94
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 00:10:16 +00:00
David Goodwin
127221fbdc
Checkpoint NEON scheduling itineraries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-23 21:38:08 +00:00
David Goodwin
546952fd60
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 22:38:43 +00:00
David Goodwin
767a952a6f
Make NEON single-precision FP support the default for cortex-a8 (again).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 23:32:33 +00:00
David Goodwin
ce3c1f2a0e
Disable NEON single-precision FP support for Cortex-A8, for now...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 16:40:57 +00:00
David Goodwin
1f0e404c87
By default, for cortex-a8 use NEON for single-precision FP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 16:01:19 +00:00
David Goodwin
42a83f2d15
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 17:53:06 +00:00
Evan Cheng
6762d91c05
Add fake v7 itineraries for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76612 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21 18:54:14 +00:00
Evan Cheng
34a0fa362d
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 01:46:35 +00:00
Evan Cheng
8557c2bcb8
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19 01:51:50 +00:00
Anton Korobeynikov
fbbf1eeccf
Separate V6 from V6T2 since the latter has some extra nice instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73085 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 21:20:36 +00:00
Anton Korobeynikov
d4022c3fbb
Add placeholder for thumb2 stuff
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29 23:41:08 +00:00
Anton Korobeynikov
6d7d2aa38a
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 19:51:43 +00:00
Bob Wilson
1f595bb429
Use CallConvLower.h and TableGen descriptions of the calling conventions
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for ARM. Patch by Sandeep Patel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 19:07:39 +00:00
Evan Cheng
027fdbe3ba
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24 07:34:46 +00:00
Evan Cheng
d87293ce78
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-06 08:47:38 +00:00
Evan Cheng
edda31c412
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 18:35:52 +00:00
Chris Lattner
4ee451de36
Remove attribution from file headers, per discussion on llvmdev.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Evan Cheng
0ff94f7fcc
Initial JIT support for ARM by Raul Fernandes Herbster.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-07 01:37:15 +00:00
Lauro Ramos Venancio
a8e9562906
Add a processor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36765 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-04 22:16:30 +00:00
Evan Cheng
a8e2989ece
ARM backend contribution from Apple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19 07:51:42 +00:00
Evan Cheng
0f3ac8d8d4
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 00:12:58 +00:00
Evan Cheng
c01d497255
Remove PointerType from class Target
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 21:20:27 +00:00
Rafael Espindola
7bc59bc395
added a skeleton of the ARM backend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00