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12713 Commits

Author SHA1 Message Date
Rafael Espindola
787d41aaa0 Add test for previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:41:34 +00:00
Johnny Chen
35563fee7b Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:14:35 +00:00
Evan Cheng
d67705faaa Look pass copies when determining whether hoisting would end up inserting more copies. rdar://9266679 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:09:18 +00:00
Johnny Chen
e679d3331b Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:34:12 +00:00
Bill Wendling
5d7a5a4f53 Revert r129235 pending a vetting of the EH rewrite. 
--- Reverse-merging r129235 into '.':
D    test/Feature/bb_attrs.ll
U    include/llvm/BasicBlock.h
U    include/llvm/Bitcode/LLVMBitCodes.h
U    lib/VMCore/AsmWriter.cpp
U    lib/VMCore/BasicBlock.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/AsmParser/LLLexer.cpp
U    lib/AsmParser/LLToken.h
U    lib/Bitcode/Reader/BitcodeReader.cpp
U    lib/Bitcode/Writer/BitcodeWriter.cpp



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129259 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-10 23:18:04 +00:00
Bill Wendling
d7bb295d22 Beginning of the Great Exception Handling Rewrite. 
* Add a "landing pad" attribute to the BasicBlock.
* Modify the bitcode reader and writer to handle said attribute.

Later: The verifier will ensure that the landing pad attribute is used in the
appropriate manner. I.e., not applied to the entry block, and applied only to
basic blocks that are branched to via a `dispatch' instruction.

(This is a work-in-progress.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-10 00:04:27 +00:00
Chris Lattner
15f8951799 fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately, 
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 19:41:05 +00:00
Chris Lattner
008c93e884 look for the verboten argument slot access in any order, thanks to Frits 
for pointing this out


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 17:00:34 +00:00
Benjamin Kramer
c18214a6e0 Don't store Twine temporaries, it's not safe. 
And don't append the name over and over again in the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129210 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 11:26:27 +00:00
Eli Friedman
18a2e50a9b Add back a couple checks removed by r129128; the fact that an intitializer 
is an array of structures doesn't imply it's a ConstantArray of
ConstantStruct.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129207 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 09:11:09 +00:00
Chris Lattner
f5bf464b70 fix PR9523, a crash in looprotate on a non-canonical loop made out of indirectbr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 07:25:58 +00:00
Chris Lattner
0403b473dd Fix a bug where RecursivelyDeleteTriviallyDeadInstructions could 
delete the instruction pointed to by CGP's current instruction
iterator, leading to a crash on the testcase.  This fixes PR9578.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 07:05:44 +00:00
Eli Friedman
9055ccdb6b PR9604; try to deal with RAUW updates correctly in the AST. I'm not convinced 
it's completely safe to cache the AST across LICM runs even with this fix,
but this fix can't hurt.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129198 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 06:55:46 +00:00
Eli Friedman
83d13a046f Test for r129190. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129197 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 06:39:43 +00:00
Chris Lattner
b99e000d79 fix two completely broken tests, which were matching due to PR9629. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129195 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 06:34:38 +00:00
Chris Lattner
9f264597d8 remove a bunch of CHECK lines that aren't checking what 
they thought they were, because alternation was expanding
wrong in {{}}'s.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 06:31:06 +00:00
Chris Lattner
b3452ea35c have dag combine zap "store undef", which can be formed during call lowering 
with undef arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129185 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 02:32:02 +00:00
Chris Lattner
4ae6a4d696 don't test for codegen of 'store undef' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 02:31:26 +00:00
Devang Patel
f03a3383f9 Add radar number for future reference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 23:52:04 +00:00
Devang Patel
fb6e8d6554 Do not emit DW_AT_upper_bound and DW_AT_lower_bound for unbouded array. 
If lower bound is more then upper bound then consider it is an unbounded array.
An array is unbounded if non-zero lower bound is same as upper bound.
If lower bound and upper bound are zero than array has one element.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 21:55:10 +00:00
Evan Cheng
4da0c7c0c9 Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 21:37:21 +00:00
Johnny Chen
c636074afc Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:41:22 +00:00
Johnny Chen
40de2b3f15 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:18:07 +00:00
Johnny Chen
084b5df5ae MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it. 
Add tests for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 17:29:58 +00:00
Johnny Chen
97fdff1d3f Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 00:29:09 +00:00
Rafael Espindola
9974b8b3cb Update tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 23:51:25 +00:00
Devang Patel
60d490cdc7 Do not let debug info interfer with branch folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 23:11:25 +00:00
Johnny Chen
3cf3059b11 Add a VEXT test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 22:04:01 +00:00
Evan Cheng
274d8d4eba Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 20:31:12 +00:00
Rafael Espindola
ce8463f1fb Add support for .skip. 
Patch by Roman Divacky.
Fixes PR9361.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 20:26:23 +00:00
Andrew Trick
5469976506 Added a check in the preRA scheduler for potential interference on a 
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:54:57 +00:00
Akira Hatanaka
9777e7afd4 Fix handling of functions with internal linkage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:51:44 +00:00
Johnny Chen
22dc4d9f59 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:28:58 +00:00
Johnny Chen
8dbda0b51b Add sanity checking for invalid register encodings for saturating instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:02:08 +00:00
Johnny Chen
4d4e25740b Add some more comments about checkings of invalid register numbers. 
And two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 18:33:19 +00:00
Devang Patel
949666ea16 While hoisting common code from if/else, hoist debug info intrinsics if they match. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 17:27:36 +00:00
Tanya Lattner
0433b21c98 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 15:24:20 +00:00
Johnny Chen
f16f4e09ec Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:37:34 +00:00
Eli Friedman
0e382192c1 PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoad 
is equivalent to any other relevant value; it isn't true in general.
If it is equivalent, the LoopPromoter will tell the AST the equivalence.
Also, delete the PreheaderLoad if it is unused.

Chris, since you were the last one to make major changes here, can you check
that this is sane?



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:35:06 +00:00
Johnny Chen
8424a60fc9 The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:05:52 +00:00
Evan Cheng
2c69f8eec6 Change -arm-divmod-libcall to a target neutral option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 00:58:44 +00:00
Johnny Chen
2455268cdd Should also check SMLAD for invalid register values. 
rdar://problem/9246650


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 00:50:25 +00:00
Owen Anderson
df298c9ea6 Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 23:35:59 +00:00
Johnny Chen
d8b4c4d74f A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 22:14:48 +00:00
Johnny Chen
4d81c9a6ba A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 20:49:02 +00:00
Johnny Chen
a9611549fe Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 18:27:46 +00:00
Nadav Rotem
d496f88c0c This testcase passed even without the fix. Added the target info to make the 
test fail (without the fix). Thanks Dan.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128999 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 11:18:29 +00:00
Johnny Chen
6a1220eeca Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 01:18:32 +00:00
Johnny Chen
2c868d1eef Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register 
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:28:00 +00:00
Johnny Chen
c3281c10c9 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:57:07 +00:00