Commit Graph

198 Commits

Author SHA1 Message Date
Jack Carter
571dd98ea4 Mips ELF: Mark object file as ABI compliant
When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 19:47:15 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:27 +00:00
Reed Kotler
2bb955a693 Remove some uneeded pseudos in the presence of the naked function attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 23:17:24 +00:00
Jack Carter
a9a5c537ad Mips specific inline asm operand modifier 'D'
Modifier 'D' is to use the second word of a double integer.

We had previously implemented the pure register varient of 
the modifier and this patch implements the memory reference.



#include "stdio.h"

int b[8] = {0,1,2,3,4,5,6,7};
void main()
{
    int i;
    
    // The first word. Notice, no 'D'
    {asm (
    "lw    %0,%1;"
    : "=r" (i)
    : "m" (*(b+4))
    );}
    
    printf("%d\n",i);

    // The second word
    {asm (
    "lw    %0,%D1;"
    : "=r" (i)
    : "m" (*(b+4))
    );}
    
    printf("%d\n",i);
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 23:19:50 +00:00
Reed Kotler
a430cb613b This patch enables llvm to switch between compiling for mips32/mips64
and mips16 on a per function basis.

Because this patch is somewhat involved I have provide an overview of the
key pieces of it.

The patch is written so as to not change the behavior of the non mixed
mode. We have tested this a lot but it is something new to switch subtargets
so we don't want any chance of regression in the mainline compiler until
we have more confidence in this.

Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1.
For that reason there are derived versions of the register info, frame info, 
instruction info and instruction selection classes.

Now we register three separate passes for instruction selection.
One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then
one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and
MipsSEISelDAGToDAG.cpp).

When the ModuleISel pass runs, it determines if there is a need to switch
subtargets and if so, the owning pointers in MipsTargetMachine are
appropriately changed.

When 16Isel or SEIsel is run, they will return immediately without doing
any work if the current subtarget mode does not apply to them.

In addition, MipsAsmPrinter needs to be reset on a function basis.

The pass BasicTargetTransformInfo is substituted with a null pass since the
pass is immutable and really needs to be a function pass for it to be
used with changing subtargets. This will be fixed in a follow on patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:46:01 +00:00
Jack Carter
ccb3c9c270 ELF symbol table field st_other support,
excluding visibility bits.

Mips (MicroMips) specific STO handling .

The st_other field settig for STO_MIPS_MICROMIPS

Contributer: Zoran Jovanovic




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 22:04:37 +00:00
Reed Kotler
79cd411809 Remove a final dependency on the form field in tablegen; which is a remnant
of the old jit and which we don't intend to support in mips16 or micromips.
This dependency is for the testing of whether an instruction is a pseudo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 21:05:58 +00:00
Reed Kotler
5cf38fd763 Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 01:04:38 +00:00
Akira Hatanaka
6c59c9f57c [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 21:50:15 +00:00
Jack Carter
9c5b94b6be This patch changes a static_cast to dyn_cast
for MipsELFStreamer objects.

Contributer: Jack Carter
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 07:47:41 +00:00
Jack Carter
dba14301f0 This patch implements runtime Mips specific
setting of ELF header e_flags.

Contributer: Jack Carter
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30 02:16:36 +00:00
Jack Carter
c91cbb9b0c This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Support for Mips register information sections.

Mips ELF object files have a section that is dedicated
to register use info. Some of this information such as
the assumed Global Pointer value is used by the linker
in relocation resolution.

The register info file is .reginfo in o32 and .MIPS.options
in 64 and n32 abi files.

This patch contains the changes needed to create the sections,
but leaves the actual register accounting for a future patch.


Contributer: Jack Carter
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18 21:20:38 +00:00
Chandler Carruth
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Akira Hatanaka
e8068692f9 [mips] Set HWEncoding field of registers. Use delete function
getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 20:04:40 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Akira Hatanaka
173192fa71 [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directive
"set .noat" so that the assembler doesn't issue warnings when register $AT is
used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167310 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-02 20:56:25 +00:00
Micah Villmow
3574eca1b0 Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 16:38:25 +00:00
Jack Carter
8e71e617c9 The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands.
If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler.

This code was originally called from  MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically.

The test cases have been checked in for a number of weeks now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 23:09:40 +00:00
Akira Hatanaka
cc46fe591a MIPS DSP: add code necessary for pseudo instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 01:59:07 +00:00
Dmitri Gribenko
2de0572cae Remove redundant semicolons which are null statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 21:26:47 +00:00
Jack Carter
a7570a3d86 There are some Mips instructions that are lowered by the
assembler such as shifts greater than 32. In the case 
of direct object, the code gen needs to do this lowering 
since the assembler is not involved.

With the advent of the llvm-mc assembler, it also needs 
to do the same lowering.

This patch makes that specific lowering code accessible 
to both the direct object output and the assembler.

This patch does not affect generated output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163287 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 02:31:34 +00:00
Jack Carter
3185f9a2ea The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31 18:06:48 +00:00
Jack Carter
714313b482 The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 20:07:41 +00:00
Jack Carter
69dba7e204 Some instructions are passed to the assembler to be
transformed to the final instruction variant. An
example would be dsrll which is transformed into 
dsll32 if the shift value is greater than 32.

For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 19:07:39 +00:00
Jack Carter
a0f14afee1 Mips specific inline asm operand modifier 'M':
Print the high order register of a double word register operand.

In 32 bit mode, a 64 bit double word integer will be represented
by 2 32 bit registers. This modifier causes the high order register
to be used in the asm expression. It is useful if you are using 
doubles in assembler and continue to control register to variable
relationships.

This patch also fixes a related bug in a previous patch:

    case 'D': // Second part of a double word register operand
    case 'L': // Low order register of a double word register operand
    case 'M': // High order register of a double word register operand

I got 'D' and 'M' confused. The second part of a double word operand
will only match 'M' for one of the endianesses. I had 'L' and 'D'
be the opposite twins when 'L' and 'M' are.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18 06:41:36 +00:00
Jack Carter
e035f65b16 Doubleword Shift Left Logical Plus 32
Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63

Here is a description of DSLL:

Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits

Description: GPR[rd] <- GPR[rt] << (sa+32)

The 64-bit doubleword contents of GPR rt are shifted left, inserting
 zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.

This patch implements the direct object output of these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 15:14:51 +00:00
Jack Carter
9a1199459d This change removes an "initialization" warning.
Even though variable in question could not 
be initialized before use, the code was such that 
the compiler had no way of knowing that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11 21:41:49 +00:00
Jack Carter
bb78930489 Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands 
   are defined by the name of the variable they are marked with in
   the inline assembler code. This is a way to specify that the 
   operand just refers to the low order register for that variable.
   
   It is the opposite of modifier 'D' which specifies the high order
   register.
   
   Example:
   
 main()
{

    long long ll_input = 0x1111222233334444LL;
    long long ll_val = 3;
    int i_result = 0;

    __asm__ __volatile__( 
		   "or	%0, %L1, %2"
	     : "=r" (i_result) 
	     : "r" (ll_input), "r" (ll_val)); 
}

   Which results in:
   
   	lui	$2, %hi(_gp_disp)
	addiu	$2, $2, %lo(_gp_disp)
	addiu	$sp, $sp, -8
	addu	$2, $2, $25
	sw	$2, 0($sp)
	lui	$2, 13107
	ori	$3, $2, 17476     <-- Low 32 bits of ll_input
	lui	$2, 4369
	ori	$4, $2, 8738      <-- High 32 bits of ll_input
	addiu	$5, $zero, 3  <-- Low 32 bits of ll_val
	addiu	$2, $zero, 0  <-- High 32 bits of ll_val
	#APP
	or	$3, $4, $5        <-- or i_result, high 32 ll_input, low 32 of ll_val
	#NO_APP
	addiu	$sp, $sp, 8
	jr	$ra

If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.

There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 22:41:20 +00:00
Jack Carter
020f07f571 Changes per review of commit 159787
Mips specific inline asm operand modifier D.
   
   Comment changes and predicate change.
   
   


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 02:44:22 +00:00
Jack Carter
244a84ee57 Mips specific inline asm operand modifier D.
Print the second half of a double word operand.
   
   The include list was cleaned up a bit as well.
   
   Also the test case was modified to test for both
   big and little patterns.
   


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 23:58:21 +00:00
Jack Carter
f38ad8efd0 Changed the formatting sequence of a curly brace to
the comment per code review feedback.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159376 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28 20:46:26 +00:00
Jack Carter
7c3cd4d24e The Mips specific inline asm operand modifier 'z' has the
following description in the gnu sources:

    Print $0 if operand is zero otherwise print the op normally.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28 01:33:40 +00:00
Bill Wendling
0bcbd1df7a Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.

The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28 00:05:13 +00:00
Jack Carter
d5e11ad51a The inline asm operand modifier 'c' is suppose
to be generic across architectures. It has the
following description in the gnu sources:

    Substitute immediate value without immediate syntax

Several Architectures such as x86 have local implementations
of operand modifier 'c' which go beyond the above description
slightly. To make use of the generic modifiers without overriding
local implementation one can make a call to the base class method
for AsmPrinter::PrintAsmOperand() in the locally derived method's 
"default" case in the switch statement. That way if it is already
defined locally the generic version will never get called.

This change is needed when test/CodeGen/generic/asm-large-immediate.ll
failed on a native Mips board. The test was assuming a generic
implementation was in place.

Affected files:

    lib/Target/Mips/MipsAsmPrinter.cpp:
        Changed the default case to call the base method.
    lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
        Added 'c' to the switch cases.
    test/CodeGen/Mips/asm-large-immediate.ll
        Mips compiled version of the generic one

Contributer: Jack Carter



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158925 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21 17:14:46 +00:00
Akira Hatanaka
864f66085c Fix coding style violations. Remove white spaces and tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14 21:10:56 +00:00
Akira Hatanaka
63b37f122d Remove code in MipsAsmPrinter and MipsMCInstLower.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158434 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14 01:20:12 +00:00
Akira Hatanaka
158413930f Bundle jump/branch instructions with the instructions in the delay slot in
delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen.

This change, along with the fix in r158154, enables machine verification
to be run after delay slot filling.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158426 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-13 23:25:52 +00:00
Akira Hatanaka
942918d13e disable use of directive .set nomicromips
until this directive is pushed in gas to open source fsf

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-13 02:41:14 +00:00
Akira Hatanaka
4c8acecfe3 Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157867 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-02 00:05:11 +00:00
Eric Christopher
6ab75b4dcb Add support for the mips inline asm 'm' output modifier.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157709 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 19:05:19 +00:00
Akira Hatanaka
6a1a2b1395 Remove the code that emits MIPS' .cprestore directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157493 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25 20:42:55 +00:00
Akira Hatanaka
c784395a79 Turn on mips16 pseudo op when compiling for mips16.
Expand test case for this.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157410 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24 18:37:43 +00:00
Eric Christopher
75f89b54b5 Add support for the 'd' mips inline asm output modifier.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-19 00:51:56 +00:00
Eric Christopher
550c25e974 Add support for the mips 'x' inline asm modifier.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18 17:39:35 +00:00
Akira Hatanaka
4147e4d054 Make the following changes in MipsAsmPrinter.cpp:
- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 00:48:43 +00:00
Eric Christopher
05b7a50210 Add support for the 'X' inline asm operand modifier.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:48:22 +00:00
Craig Topper
420761a0f1 Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 07:30:17 +00:00
Akira Hatanaka
f93b863066 Emit all directives except for ".cprestore" during asm printing rather than emit
them as machine instructions. Directives ".set noat" and ".set at" are now
emitted only at the beginning and end of a function except in the case where
they are emitted to enclose .cpload with an immediate operand that doesn't fit
in 16-bit field or unaligned load/stores.

Also, make the following changes:
- Remove function isUnalignedLoadStore and use a switch-case statement to
  determine whether an instruction is an unaligned load or store.

- Define helper function CreateMCInst which generates an instance of an MCInst
  from an opcode and a list of operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28 00:22:50 +00:00
Craig Topper
79aa3417eb Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17 18:46:09 +00:00
Akira Hatanaka
6e1beea6bf Remove unused header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152447 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 23:28:30 +00:00
Jia Liu
bb481f8820 remove blanks, and some code format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 07:46:26 +00:00
Akira Hatanaka
648f00c2f0 Add an option to use a virtual register as the global base register instead of
reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register. 

example:

.cpload $25       // set $gp.
...
.cprestore 16     // store $gp to stack slot 16($sp).
...
jalr $25          // function call. clobbers $gp.
lw $gp, 16($sp)   // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25          // function call.
lw $gp, 16($sp)   // not emitted if $gp is not live after this instruction.
...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 22:34:47 +00:00
Ahmed Charles
b0934ab7d8 Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 11:37:01 +00:00
Jia Liu
c5707112e7 remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 08:55:11 +00:00
Jia Liu
8f5e8c1cd6 add Emacs tag and fix some comment error in file headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 01:23:50 +00:00
Bruno Cardoso Lopes
ce8524c016 Cleanup Mips code and rename some variables. Patch by Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 21:09:41 +00:00
Akira Hatanaka
9dfd4399a9 Detect unaligned loads/stores that have been added for Mips64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 03:07:37 +00:00
Akira Hatanaka
8209968306 Tidy up. Simplify logic. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:52:25 +00:00
Akira Hatanaka
044a784fa5 Expand .cprestore directive to multiple instructions if the offset does not fit
in a 16-bit field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 03:09:05 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Akira Hatanaka
421455f1ea This patch makes the following changes necessary for MIPS' direct code emission.
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-23 22:19:28 +00:00
Akira Hatanaka
73c38f0aa2 Remove MipsMCSymbolRefExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 18:20:08 +00:00
Bruno Cardoso Lopes
47b92f3d83 Mips MC object code emission improvements:
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144414 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 22:58:42 +00:00
Bruno Cardoso Lopes
ce1a538ab5 Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144139 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08 22:26:47 +00:00
Benjamin Kramer
5908536673 Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 20:37:06 +00:00
Akira Hatanaka
68ad5673e8 Fix function isUnalignedLoadStore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 22:04:01 +00:00
Akira Hatanaka
cb518ee5dd Add patterns for unaligned load and store instructions and enable the
instruction selector to generate them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 02:24:10 +00:00
Akira Hatanaka
e33ca9ce1f Add enums and functions for symbols Mips64 uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22 03:09:07 +00:00
Akira Hatanaka
2464810ac2 Add a base class for Mips TargetMachines and add Mips64 TargetMachines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 03:00:58 +00:00
Akira Hatanaka
46ac94ba8b O64 will not be supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139421 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:22:48 +00:00
Akira Hatanaka
8ddf6531b8 Drop support for Mips1 and Mips2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00
Evan Cheng
3e74d6fdd2 Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:08:43 +00:00
Akira Hatanaka
511961a44c Add support for half-word unaligned loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137848 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 18:49:18 +00:00
Akira Hatanaka
614051a1c5 Fix handling of double precision loads and stores when Mips1 is targeted.
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16 03:51:51 +00:00
Akira Hatanaka
5c21c9e78e Define unaligned load and store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 21:30:06 +00:00
Evan Cheng
4b64e8a9e1 Separate MCInstPrinter registration from AsmPrinter registration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:20:24 +00:00
Akira Hatanaka
794bf17cbe Lower MachineInstr to MC Inst and print to .s files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 23:56:50 +00:00
Akira Hatanaka
03236be44a Rather than having printMemOperand change the way memory operands are printed
based on a modifier, split it into two functions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:54:20 +00:00
Akira Hatanaka
aa08ea0530 Change visibility of MipsAsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:10:52 +00:00
Akira Hatanaka
d3ac47f805 Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 18:57:00 +00:00
Akira Hatanaka
e280519ba6 Add missing return statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134622 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 18:27:36 +00:00
Akira Hatanaka
c4f24eb584 Improve Mips back-end's handling of DBG_VALUE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:04:43 +00:00
Akira Hatanaka
21afc63ea7 Re-apply 132758 and 132768 which were speculatively reverted in 132777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 00:40:49 +00:00
Eric Christopher
6f3661fdcd Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132777 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 16:03:19 +00:00
Akira Hatanaka
c53cc48ca9 Initial support for inline asm memory operand constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132768 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 03:31:05 +00:00
Bruno Cardoso Lopes
d979686bb4 This patch implements the thread local storage. Implemented are General
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 02:53:58 +00:00
Akira Hatanaka
ce98deb9f5 Enable printing of immediates that do not fit in 16-bit. .cprestore can have
offsets that are larger than 0x10000.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 21:22:21 +00:00
Akira Hatanaka
f8928c07e7 Fix MipsAsmPrinter::printSavedRegsBitmaskChange. Remove functions and variables
in MipsFunctionInfo that are no longer used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 20:34:30 +00:00
Akira Hatanaka
4552c9a3b3 Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 21:51:11 +00:00
Akira Hatanaka
0bf3dfbef6 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 21:00:26 +00:00
Akira Hatanaka
dc1652fd31 Insert space before ';' to prevent warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128750 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 00:15:58 +00:00
Akira Hatanaka
e2e436a6bc Simplifies logic for printing target flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 21:41:06 +00:00
Akira Hatanaka
a4485c4964 Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 18:57:38 +00:00
Bruno Cardoso Lopes
ca8a2aa921 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 20:01:52 +00:00
Bruno Cardoso Lopes
81092dc20a Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 17:51:39 +00:00
Anton Korobeynikov
16c29b5f28 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 12:39:04 +00:00
Bruno Cardoso Lopes
ab8d53a56a Match a pattern generated by a dag combiner opt where:
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07 19:00:20 +00:00
Anton Korobeynikov
d0c3817669 Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 21:19:35 +00:00
Chris Lattner
1139691e3a move all the target's asmprinters into the main target. The piece
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:43:56 +00:00
Anton Korobeynikov
6c5cfec73e Separate MIPS asmprinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68383 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03 10:41:41 +00:00