Jim Grosbach
18f30e6f5e
Clean up 80 column violations. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 21:53:11 +00:00
Rafael Espindola
42d075c4fb
Remove the TargetRegisterClass member from CalleeSavedInfo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 20:02:30 +00:00
Eli Friedman
962f549d20
Fix comment so it doesn't include comments which are irrelevant to the x86
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backend. Add a FIXME noting what can be fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 19:35:46 +00:00
Dan Gohman
71c62a2977
Use comments to document non-obvious code rather than
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mailing list archives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 19:13:40 +00:00
Bob Wilson
91a74da036
Rename canCombinedSubRegIndex method to something more grammatically correct
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and tidy up the comment describing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 18:54:47 +00:00
Rafael Espindola
20fae65181
Replace ARM's getCalleeSavedRegClasses with a simpler solution
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 17:54:50 +00:00
Rafael Espindola
691820a1a0
Remove unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 15:44:20 +00:00
Rafael Espindola
6f07bd6ae8
cleanup
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 13:53:17 +00:00
Rafael Espindola
ce48c1de82
Remove uses of getCalleeSavedRegClasses from outside the
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backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 12:39:06 +00:00
Eli Friedman
a993f0a45f
Don't try to custom-lower 64-bit add-with-overflow and friends on x86-32; the
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x86 backend currently doesn't know how to handle them.
This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either. We do get a better error message, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105305 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 00:27:18 +00:00
Eli Friedman
b242563741
Remove outdated README entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 00:10:36 +00:00
Dan Gohman
d8acddda58
Fix the allocation of shadow space for the Win64 calling convention
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in X86FastISel. Patch by Jan Sjodin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105290 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-01 21:09:47 +00:00
Bruno Cardoso Lopes
7f5b0d8099
Refactor some SSE 2 unpack instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-01 17:02:50 +00:00
Kalle Raiskila
11fe24624a
Fix handling of 'load' nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105269 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-01 13:34:47 +00:00
Anton Korobeynikov
4ed81ecbcd
Some A9 load/store cleanups
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 19:25:39 +00:00
Anton Korobeynikov
8207fce96f
Some rough approximations for load/stores on A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 19:25:34 +00:00
Anton Korobeynikov
1098ef5fa4
NEON/VFP stuff can be issued only via Pipe1 on A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105107 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 19:25:29 +00:00
Anton Korobeynikov
1845a387e1
Add some integer instruction itineraries for A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105106 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 19:25:17 +00:00
Evan Cheng
9c044674e6
Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29 01:35:22 +00:00
Jakob Stoklund Olesen
05ce489871
Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices
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were overspecified when inheriting sub-subregisters, for instance:
R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.
This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:48:29 +00:00
Evan Cheng
c10f5434b4
Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:25:23 +00:00
Dale Johannesen
2f05cc06a2
Fix comment typos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:24:28 +00:00
Bruno Cardoso Lopes
f39e0ce4ec
More SSE 1 & 2 merge, this time with logical instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 22:47:03 +00:00
Kevin Enderby
31cc9655b6
MC/X86: Add alias for movzx.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 21:20:21 +00:00
Kevin Enderby
5e394429ab
MC/X86: Add alias for fwait.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 20:59:10 +00:00
Kevin Enderby
31b6c5b2f3
Fix the use of x86 control and debug registers so that the assertion failure in
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getX86RegNum() does not happen. Patch by Shantonu Sen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 19:01:27 +00:00
Jim Grosbach
bc213209bf
correct retattr
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 18:03:48 +00:00
Jim Grosbach
c9792a3c1f
Cosmetic cleanup. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 17:51:20 +00:00
Jim Grosbach
5caeff5c01
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 17:37:40 +00:00
Bob Wilson
13ef840807
Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
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the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 00:27:15 +00:00
Jim Grosbach
0798eddd07
Update the saved stack pointer in the sjlj function context following either
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an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:49:24 +00:00
Evan Cheng
12616727c7
Use report_fatal_error, not llvm_unreachable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:45:31 +00:00
Jim Grosbach
a65850230a
back out 104862/104869. Can reuse stacksave after all. Very cool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:11:57 +00:00
Evan Cheng
84f60b7359
llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 22:08:38 +00:00
Kevin Enderby
bd658918df
MC/X86: Add aliases for Jcc variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 21:33:19 +00:00
Bob Wilson
d984eb6073
Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases
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should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 20:23:42 +00:00
Dale Johannesen
54feef2950
Mark some math lib intrinsic nodes Legal on SSE4.1.
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No functional effect as these nodes are not generated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 20:12:41 +00:00
Dan Gohman
4d3d6e1a0c
FastISel doesn't yet handle callee-pop functions.
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To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 18:43:40 +00:00
Jim Grosbach
ad9aaf038e
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
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to update the jmpbuf in the presence of VLAs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 18:23:48 +00:00
Bruno Cardoso Lopes
aa02ff1a2b
Merge basic binops SSE 1 & 2 instruction classes. This is a step towards refactoring
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common code between SSE versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 18:17:40 +00:00
Daniel Dunbar
dcbab9cf5a
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected
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to be matched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:21:28 +00:00
Jakob Stoklund Olesen
c8b9f6ce23
Give SubRegIndex names to all ARM subregisters. This will be required by
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TableGen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:15:03 +00:00
Daniel Dunbar
cb8326dc09
MC: Add TargetMachine support for setting the value of MCRelaxAll with
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-filetype=obj.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen
160a3bf74d
Add StringRef::compare_numeric and use it to sort TableGen register records.
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This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:47:28 +00:00
Jim Grosbach
23ff7cff52
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
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ISD::. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:22:18 +00:00
Kevin Enderby
b106543592
Fix the x86 move to/from segment register instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:10:45 +00:00
Daniel Dunbar
95506d40c5
MC: Change RelaxInstruction to only take the input and output instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104713 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:15:06 +00:00
Dan Gohman
d9c2af5409
Fix a typo in a comment that Gabor noticed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:03:53 +00:00
Daniel Dunbar
8488252855
MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
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before encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:45:29 +00:00
Jakob Stoklund Olesen
ca561ffcf3
Replace the SubRegSet tablegen class with a less error-prone mechanism.
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A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:27:12 +00:00