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14831 Commits

Author SHA1 Message Date
Eric Christopher
423c9e3e58 Add some section and constant support for darwin TLS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 21:02:07 +00:00
Bob Wilson
7f43fd84db Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests. 
Obvious in retrospect but not fun to debug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103969 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 20:31:13 +00:00
Evan Cheng
6206124250 Turn on -neon-reg-sequence by default. 
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 19:51:20 +00:00
Evan Cheng
9c207ac0dc No reason not to run the NEON domain croassing fix up pass in thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 01:11:46 +00:00
Dale Johannesen
f7f5a2760a Revert 103911; it broke a test that expects bitconvert 
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine).  The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103914 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 20:19:04 +00:00
Dale Johannesen
f9b2242927 Make x86-64 64-bit bitconvert work when SSE is not available. 
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103911 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 18:22:38 +00:00
Anton Korobeynikov
bd91ea53f8 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 09:15:36 +00:00
Anton Korobeynikov
ded05e34b6 Add support for thiscall calling convention. 
Patch by Charles Davis and Steven Watanabe!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 09:08:45 +00:00
Anton Korobeynikov
4878b8415f Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 08:54:20 +00:00
Evan Cheng
8f6de385d6 Model vst lane instructions with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103898 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 03:27:48 +00:00
Dale Johannesen
8d908ebd19 Fix uint64->{float, double} conversion to do rounding correctly in 32-bit. 
The implementation in LegalizeIntegerTypes to handle this as 
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people.  Use this implementation only
when it is safe.  This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)

Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.

7885399, 5901940.  This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 18:51:12 +00:00
Anton Korobeynikov
a9790d739a Some cheap DAG combine goodness for multiplication with a particular constant. 
This can be extended later on to handle more "complex" constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 18:16:59 +00:00
Anton Korobeynikov
418d1d954d "trap" pseudo-op turned out to be apple-local. 
Temporary emit it as raw bytes until it will be added to binutils as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 17:19:20 +00:00
Evan Cheng
7189fd03fa Model 128-bit vld lane with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 07:53:37 +00:00
Evan Cheng
4782b1e2ca v4i64 and v8i64 are only synthesizable when NEON is available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103855 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 02:20:21 +00:00
Evan Cheng
06b666c705 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 02:18:07 +00:00
Evan Cheng
7092c2bfcb Model 64-bit lane vld with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 01:36:29 +00:00
Evan Cheng
b990a2f249 Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE 
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 23:21:14 +00:00
Evan Cheng
12c24690c7 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103833 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 22:54:52 +00:00
Bill Wendling
23ead99283 SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and 
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 22:17:42 +00:00
Dan Gohman
4ee637c730 BR is a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103826 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 22:00:27 +00:00
Bill Wendling
f84d60b649 Several tail call tests apparently rely upon this being "adjusts stack" instead 
of "has calls". That's probably wrong, but it needs further
investigation. Revert to the original behavior until this is settled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103824 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:58:35 +00:00
Bill Wendling
55ed945bfd This should happen if there are no calls, not if it just doesn't adjust the 
stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103813 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:38:44 +00:00
Bill Wendling
0fc546b053 Revert r103804. The comment is correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:28:24 +00:00
Bill Wendling
d33fa0f9e0 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:17:29 +00:00
Bill Wendling
b92187a410 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:14:32 +00:00
Dan Gohman
71ea4e5b05 Lowering of atomic instructions can result in operands being 
used more than once. If ISel had put a kill flag on one of them,
it's not valid to transfer the kill flag to each new instance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 21:01:44 +00:00
Kevin Enderby
c3ce05c594 Fix so "int3" is correctly accepted, added "into" and fixed "int" with an 
argument, like "int $4", to not get an Assertion error.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103791 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 19:16:02 +00:00
Evan Cheng
5c6aba2e3a Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 18:54:59 +00:00
Dan Gohman
effc8c5269 Set isTerminator on TRAP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103778 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 16:46:02 +00:00
Dan Gohman
c0c32ae5c2 Don't use isBarrier for the PowerPC sync instruction. isBarrier is for 
control barriers, not memory ordering barriers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103777 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 16:42:16 +00:00
Dan Gohman
7f357ec6d2 Add mayLoad and mayStore flags to instructions which missed them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103776 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 16:34:55 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 02:13:41 +00:00
Evan Cheng
7f68719517 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 00:21:45 +00:00
Evan Cheng
c4ca40eb5e Add comment about the pseudo registers QQ, each of which is a pair of Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 20:02:08 +00:00
Bob Wilson
1190c14b54 Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers. 
Do not use those for Thumb1 functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 19:58:24 +00:00
Oscar Fuentes
ed36aac081 CMake: fixes 64 bit Visual Studio IDE build. Fixes bug 4936. 
Patch by Dimitry Andric!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103727 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 19:34:06 +00:00
Anton Korobeynikov
61aeed11cd Properly set thread-local flag on globals during cpp emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 07:41:57 +00:00
Daniel Dunbar
1860e7dcfd Fix -Asserts warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 03:19:36 +00:00
Evan Cheng
69b9f9883e Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 01:12:06 +00:00
Evan Cheng
d929f77738 Expand VMOVQQ into a pair of VMOVQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:17:02 +00:00
Evan Cheng
020cc1b4d0 Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:16:46 +00:00
Chris Lattner
b5505d0ee3 reapply r103668 with a fix. Never make "minor syntax changes" 
after testing before committing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103681 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:02:47 +00:00
Chris Lattner
3519f9d7d1 revert r103668 for now, it is apparently breaking things. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103677 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 23:40:59 +00:00
Chris Lattner
0de8e3f10a moffset forms of moves are x86-32 only, make the parser 
lower them to the correct x86-64 instructions since we 
don't have a clean way to handle this in td files yet.
rdar://7947184


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 23:13:36 +00:00
Evan Cheng
431300797b Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 23:13:12 +00:00
Chris Lattner
2745f6e920 fix the encoding of the obscure "moffset" forms of moves, i386 
part first.  rdar://7947184


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 22:48:24 +00:00
Evan Cheng
a4d73d01c4 Remove a dead fixme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 20:20:22 +00:00
Rafael Espindola
18c1021ec1 Add support for movi32 of global values to the new (MC) asm printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 05:16:34 +00:00
Evan Cheng
5bdc2aa264 vst instructions are modeled as this: 
v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
      = VSTxx <addr>, v1025, v1026

The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
      = VSTxx <addr>, v1024:5, v1024:6

The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.

As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.

Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 01:42:50 +00:00
Daniel Dunbar
0481449a05 MC/X86: Extend suffix matching hack to match 'q' suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103535 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 00:54:20 +00:00
Daniel Dunbar
a5f1d57f65 MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can 
be diced into atoms, and adjust getAtom() to take this into account.
 - This fixes relocations to symbols in fixed size literal sections, for
   example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103532 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 00:38:17 +00:00
Dan Gohman
a6cb641f48 Add initial kill flag support to FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 23:54:07 +00:00
Evan Cheng
9647f3d981 Avoid breaking vstd when reg_sequence is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 21:07:36 +00:00
Bill Wendling
f6d8481ada Simplify this logic of creating a default Features object. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103507 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 20:46:04 +00:00
Duncan Sands
16d8f8bd91 I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 20:16:09 +00:00
Dan Gohman
99dca4fde7 Remove the "WantsWholeFile" concept, as it's no longer needed. CBE 
and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 19:57:55 +00:00
Dan Gohman
ff7a562751 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263 Remove the TargetLowering::getSubtarget() virtual function, which 
was unused. TargetMachine::getSubtarget() is used instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 16:21:03 +00:00
Kalle Raiskila
2320a44b90 Make SPU backend not assert on jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 11:00:02 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 07:26:32 +00:00
Bill Wendling
3cbae239bb Don't create a StringRef with a NULL value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 01:33:39 +00:00
Evan Cheng
0ce537a9db Model some vst3 and vst4 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 01:19:40 +00:00
Bill Wendling
81043ee5dc The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a 
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.

Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103451 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 00:30:02 +00:00
Evan Cheng
e9e2ba05de Model some vld3 instructions with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a Model vld2 / vst2 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 17:34:18 +00:00
Kalle Raiskila
26c4cf4c6f Fix encoding of 'sf' and 'sfh' instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 08:13:49 +00:00
Nathan Jeffords
bb59732d18 updated handling dllexport in X86AsmPrinter 
changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-09 08:40:06 +00:00
Nathan Jeffords
071de920a0 made COFF target dllexport logic apply to all subtargets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-09 05:52:28 +00:00
Chris Lattner
b54b9ddaaf break coff symbol definition stuff out into proper MCStreamer callbacks, 
patch by Nathan Jeffords!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103346 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-08 19:54:22 +00:00
Jim Grosbach
4b77f6a85a Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:34:55 +00:00
Devang Patel
ed66bf5125 Use overloaded operators instead of DIDescriptor::getNode() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:19:32 +00:00
Kalle Raiskila
021b5ef903 Testing svn access with a note added to documentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103271 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:06:28 +00:00
Chris Lattner
eb40a0fd98 switch MCSectionCOFF from a syntactic to semantic representation, 
patch by Peter Housel!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103267 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 17:17:41 +00:00
Evan Cheng
435d499177 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:54:08 +00:00
Dan Gohman
0d881042c0 When rematerializing, use the debug location of the original 
instruction, rather than a location near where the new instruction
is being inserted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:28:10 +00:00
Evan Cheng
c10b5afbe8 Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 00:24:52 +00:00
Daniel Dunbar
c26ae5ab7e MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. 
- This fixes "leal 0, %eax", for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 22:39:14 +00:00
Chris Lattner
e1611f26e3 fix rdar://7947167 - llvm-mc doesn't match movsq 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 21:48:14 +00:00
Sean Callanan
1a8b789a4b Eliminated the classification of control registers into %ecr_ 
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:59:00 +00:00
Daniel Dunbar
a5d0b54ec1 MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since 
we don't currently support relaxing them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:34:01 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1 Add a missing break statement to fix unintentional fall-through 
(replacing the previous patch for the same issue).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7 Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3 Fix "warning: extra ';' inside a struct or union" when building llvm with clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128 Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 05:08:57 +00:00
Eric Christopher
f865cb5c1f Revert r103156 since it was breaking the build bots. 
Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 02:29:06 +00:00
Evan Cheng
9c35ee2099 Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:54:03 +00:00
Evan Cheng
4ffc22ae00 Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:52:03 +00:00
Evan Cheng
d31c5496d7 Cosmetic changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:34:11 +00:00
Evan Cheng
7f2f436267 storeRegToStackSlot has forgotten about QPR_8 register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:32:54 +00:00
Jim Grosbach
29402132f3 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 23:44:43 +00:00
Sean Callanan
be192dd1e9 Fixed a sign-extension bug in the X86 disassembler 
that was causing PC-relative branch targets to be
evaluated incorrectly.  Also added support for
checking operand values to the llvm-mc tester.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103128 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 22:47:27 +00:00
Evan Cheng
676b2dfd27 Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 22:15:40 +00:00
Dan Gohman
9f2cda73e4 No-ops emitted for scheduling don't correspond with anything in the 
user's source, so don't arbitrarily assign them a debug location.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 20:58:01 +00:00
Jim Grosbach
b1dc393bd5 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 18:28:36 +00:00
Evan Cheng
d2c2d1809f Trim include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103103 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 18:27:57 +00:00
Eric Christopher
f4f06906b8 Revert 102941, we're going to do this via attr and can just 
hack the code to turn it off when debugging.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 07:35:59 +00:00
Eric Christopher
d2760d1cba Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103057 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 22:13:03 +00:00
Evan Cheng
94cc6d3a2b With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:39:49 +00:00
Evan Cheng
826bdfa603 Do not pre-allocate for registers which form a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:38:12 +00:00
Chris Lattner
d4ac35b350 "on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'." 
Patch by Kalle Raiskila!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 17:58:46 +00:00
Daniel Dunbar
e9f0fb4179 MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of 
instructions which have no direct register usage.

Darwin 'as' accepts:
  add $0, (%rax)
but rejects
  mov $0, (%rax)
for example.

Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103015 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 17:31:02 +00:00
Daniel Dunbar
c918d6043b MC/X86: Add "support" for matching ATT style mnemonic prefixes. 
- The idea is that when a match fails, we just try to match each of +'b', +'w',
   +'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
   it. If all match, we assume it is width generic, and take the 'l' form.

 - This would be a horrible hack, if it weren't so simple. Therefore it is an
   elegant solution! Chris gets the credit for this particular elegant
   solution. :)

 - Next step to making this more robust is to have the X86 matcher generate the
   mnemonic prefix information. Ideally we would also compute up-front exactly
   which mnemonic to attempt to match, but this may require more custom code in
   the matcher than is really worth it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103012 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 16:12:42 +00:00
Gabor Greif
2f256f4561 fix operand indexes when outputting InvokeInsts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103003 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 09:23:54 +00:00
Kevin Enderby
a0161cd6f8 Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode 
changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102991 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 00:42:46 +00:00
Jim Grosbach
6e62b4ef14 rdar://7937137 - dbg values not being handled in thumb1 version of 
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 00:11:37 +00:00
Dale Johannesen
08673d2950 Implement builtin_return_address(x) and builtin_frame_address(x) 
on PPC for x!=0.  7624113.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102972 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 22:59:34 +00:00
Kevin Enderby
9d0838fba8 Changed llvm-mc to use the same suffixes with floating point compare 
instructions as the Mac OS X darwin assembler.  Some of which like 'fcoml'
assembled to different opcodes.  While some of the suffixes were just different.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102958 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 21:31:40 +00:00
Kevin Enderby
eb612347f4 Fixed the encoding of two of the X86 movq instuctions. The Move quadword from 
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102952 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 21:03:31 +00:00
Kevin Enderby
3c979b06c0 Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value 
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value.  Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte.  Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 20:45:05 +00:00
Eric Christopher
0b12348ddf Add an option, defaulting to off, to disable the sse domain crossing opts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102941 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 19:54:02 +00:00
Dan Gohman
3a2a4846a6 Add a README entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-03 14:31:00 +00:00
Duncan Sands
57b6e9eb6c Remove the -enable-sjlj-eh option, which doesn't do anything. 
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102865 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-02 15:36:26 +00:00
Chris Lattner
241d3fea7a fix some inconsistent line endings, patch by Jakub Staszak! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 17:36:49 +00:00
Anton Korobeynikov
1b17614a72 Do folding for indirect branches, where possible 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 12:28:21 +00:00
Anton Korobeynikov
69d5b48bc3 Implement indirect branches on MSP430 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 12:04:32 +00:00
Anton Korobeynikov
650a8e49f9 Long branch target oparands are not pc-rel. 
This should fix PR6603.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102834 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 12:04:22 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 00:01:06 +00:00
Dan Gohman
acbfc157d2 Fix a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 22:38:11 +00:00
Dan Gohman
3335a22a37 Make this code less confusing. Instead of reassigning BB, just operate 
on the original variables, so it's easier to see what is being done
to which blocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102759 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 20:14:26 +00:00
Dan Gohman
71edb241a1 Remove the -disable-16bit command-line option, which is now obsolete. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 18:30:26 +00:00
Evan Cheng
1361796dd0 Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 01:12:32 +00:00
Dan Gohman
ffce6f1343 Don't leave Base.FrameIndex uninitialized, so that it doesn't 
print randomly in debug output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 23:30:41 +00:00
Dale Johannesen
8c5358c936 Make naked functions work on PPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102657 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 19:32:19 +00:00
Devang Patel
67a444ca36 Print variable scope name in DEBUG_VALUE comment. Useful in some cases. e.g. 
##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
	##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
	##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
	##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
	##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 18:52:10 +00:00
Evan Cheng
3f54c64a98 Load folding tail call should not use ebp / rbp after it's popped. PEI 
should use esp / rsp to reference frame instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 05:08:22 +00:00
Mon P Wang
b9a01bcf48 Add support for assemblers that don't support periods in a name 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 04:00:56 +00:00
Evan Cheng
8601a3d4de Frame index can be negative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 01:13:30 +00:00
Kevin Enderby
9ac7282117 Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the 
Operand size override prefix to be part of their records.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102556 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 23:20:40 +00:00
Jim Grosbach
d100755bab Add sizes non-floating point versions for the eh sjlj intrinsic expansions. 
rdar://7895451



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 20:33:09 +00:00
Jakob Stoklund Olesen
7261fb2a6f Teach X86FloatingPoint that a register can be killed multiple times by the same 
instruction.

This instruction would crash the pass:

  INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>

Now it doesn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 18:28:37 +00:00
Evan Cheng
2bce5f4b56 Enable i16 to i32 promotion by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 08:30:49 +00:00
Evan Cheng
39cfeecae5 Unbreak the build. Only form shld / shrd after legalization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 02:25:18 +00:00
Devang Patel
28ff35d030 Emit debug info for byval parameters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102486 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:39:28 +00:00
Evan Cheng
8b1190a540 Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:18:01 +00:00
Chris Lattner
a7b611c10d further simplify EmitAlignment by eliminating the 
ForcedAlignBits argument, tweaking the single client of it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102484 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:08:40 +00:00
Stuart Hastings
5a6a65be46 Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102477 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 00:35:10 +00:00
Devang Patel
a00adba6a7 Use MachineOperand::is* predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102472 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 22:24:37 +00:00
Evan Cheng
1c45acf510 Fix obvious typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 21:46:03 +00:00
Evan Cheng
b3716e3e28 SRA promotion is also not free. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 19:48:31 +00:00
Chris Lattner
ee9eb411ff on darwin empty functions need to codegen into something of non-zero length, 
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:37:21 +00:00
Bob Wilson
5dfa87ecc6 Handle register-to-register copies within the tGPR class. 
Radar 7896289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:20:08 +00:00
Dale Johannesen
3f282aa94b Handle target-specific form of DBG_VALUE in AsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:07:31 +00:00
Dale Johannesen
efc3a6348a Add PPC AsmPrinter handling for target-specific form of 
DBG_VALUE, and a cautionary comment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:05:01 +00:00
Evan Cheng
552f09a0d7 Promoting 16-bit cmp / test aren't free. Don't do it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 19:06:11 +00:00
Evan Cheng
fc4d530ad6 Remove a redundant comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 08:16:57 +00:00
Evan Cheng
0965217e74 Add PPC specific emitFrameIndexDebugValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102325 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:39:36 +00:00
Evan Cheng
62b50656ce Add ARM specific emitFrameIndexDebugValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:39:25 +00:00
Evan Cheng
962021bc7f - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. 
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:38:55 +00:00
Dale Johannesen
f822e733af Stop abusing EmitInstrWithCustomInserter for target-dependent 
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-25 21:33:54 +00:00
Evan Cheng
c82c20b315 Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-24 04:44:57 +00:00
Dan Gohman
6e8fd90602 Change TargetData's algorithm for computing defualt vector type 
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 19:41:15 +00:00
Stuart Hastings
e3ff9ba40c Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 19:03:32 +00:00
Evan Cheng
2808ccb775 Fix X86ISD::CMP i16 to i32 promotion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 18:21:16 +00:00
Jim Grosbach
3a1287b470 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 23:24:18 +00:00
Dan Gohman
f81eca0ab9 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel 
and into SelectionDAGBuilder and FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 20:46:50 +00:00
Evan Cheng
07c4e1085d - It's not safe to promote rotates (at least not trivially). 
- Some code refactoring.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102111 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 20:19:46 +00:00
Johnny Chen
c048f1d12c Modified some assert() msg strings; no other functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 18:37:48 +00:00
Evan Cheng
e566763b19 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 03:18:23 +00:00
Evan Cheng
5528e7bcb1 isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:47:12 +00:00
Evan Cheng
fe5dcbc27d Trim include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101978 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:39:06 +00:00
Dan Gohman
f0757b0edc Add more const qualifiers on TargetMachine and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:34:56 +00:00
Johnny Chen
52d2b0ed00 Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:01:19 +00:00
Bill Wendling
a040fffefb Handle a displacement location in 64-bit as an RIP-relative displacement. It 
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:

target triple = "x86_64-apple-darwin"

define double @func(double %a) {
  %tmp1 = fmul double %a, 5.000000e-01            ; <double> [#uses=1]
  ret double %tmp1
}

define i32 @main() nounwind {
  %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
  ret i32 0
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101965 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 00:34:04 +00:00
Chris Lattner
d6139425f5 teach the x86 address matching stuff to handle 
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 23:18:40 +00:00
Dale Johannesen
7609017dc3 Because of the EMMS problem, right now we have to support 
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 22:34:09 +00:00
Johnny Chen
d6b5d72c0f Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), 
instead of just asserting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 21:29:28 +00:00
Johnny Chen
ef37e3abb7 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', 
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 17:28:50 +00:00
Chris Lattner
aa2776e934 teach cellspu how to return i8 and i16 from calls, 
patch by Kalle Raiskila!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 05:36:09 +00:00
Chris Lattner
d7aba875c1 disable optimizations in this directory for MSVC9. This avoids 
an optimizer infinite loop on the file, PR6866.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 01:11:32 +00:00
Johnny Chen
3974ade503 Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where 
d==15 is considered illegal.  Return false instead of assert().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 01:01:57 +00:00
Eric Christopher
6d972fd087 Remove the palignr intrinsics now that we lower them to vector shuffles, 
shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 00:59:54 +00:00
Johnny Chen
6bcf52f00a More IT instruction error-handling improvements from fuzzing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 00:15:41 +00:00
Johnny Chen
d0f3c46d16 Better error handling of invalid IT mask '0000', instead of just asserting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 23:02:58 +00:00
Dan Gohman
1f65453d0a Delete an unnecessary reference to SelectionDAGISel::BB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101824 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 22:48:45 +00:00
Johnny Chen
22e401f5d4 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 21:19:52 +00:00
Evan Cheng
4c26e93e89 More progress on promoting i16 operations to i32 for x86. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 19:29:22 +00:00
Johnny Chen
d6cc53cfe4 Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand 
instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 17:16:40 +00:00
Johnny Chen
4b7df442a8 ARM disassembler did not react to recent changes to the NEON instruction table. 
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 16:20:34 +00:00
Anton Korobeynikov
d456a47dd3 Add missed part of prev. commit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-18 20:41:42 +00:00
Anton Korobeynikov
928eb49cae Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-18 20:31:01 +00:00
Chris Lattner
34e9d17d1b fix PR6332, allowing an index of zero into a zero sized array 
even if the element of the array has no size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 19:02:33 +00:00
Chris Lattner
eef6d78be1 teach the x86 asm parser how to handle segment prefixes 
in memory operands.  rdar://7874844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 18:56:34 +00:00
Dan Gohman
3fb150a902 Fix -Wcast-qual warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 17:42:52 +00:00
Chris Lattner
89f94926b0 remove a dead variable, PR6856 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 17:28:00 +00:00
Dan Gohman
0d805c33d1 Add const qualifiers to TargetLoweringObjectFile usage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 16:44:48 +00:00
Dan Gohman
82d5eaf23e Use const_cast instead of a C-style cast to cast away const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101639 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 16:43:55 +00:00
Dan Gohman
383b5f6b91 Delete now-unnecessary const_casts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101637 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 15:32:28 +00:00
Dan Gohman
b6f778a8f6 Use cast instead of dyn_cast when assuming success. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101636 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 15:31:16 +00:00
Dan Gohman
d858e90f03 Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 15:26:15 +00:00
Dan Gohman
1e93df6f0b Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 14:41:14 +00:00
Chandler Carruth
2329d66a9f Name these stub files consistently with the SPU and PPC targets' conventions. 
Also rename the classes appropriately. The CMake build already used these
names.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101631 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 08:50:29 +00:00
Chris Lattner
65de1b9eb3 a bunch of ssse3 instructions are misencoded to think they have an 
i8 field when they really do not.  This fixes rdar://7840289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 07:38:24 +00:00
Evan Cheng
e5b51ac770 More work to allow dag combiner to promote 16-bit ops to 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 06:13:15 +00:00
Bob Wilson
9f3f061d74 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this 
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 05:30:19 +00:00