Daniel Dunbar
0481449a05
MC/X86: Extend suffix matching hack to match 'q' suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103535 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 00:54:20 +00:00
Daniel Dunbar
a5f1d57f65
MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
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be diced into atoms, and adjust getAtom() to take this into account.
- This fixes relocations to symbols in fixed size literal sections, for
example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103532 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 00:38:17 +00:00
Dan Gohman
a6cb641f48
Add initial kill flag support to FastISel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 23:54:07 +00:00
Evan Cheng
9647f3d981
Avoid breaking vstd when reg_sequence is not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 21:07:36 +00:00
Bill Wendling
f6d8481ada
Simplify this logic of creating a default Features object.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 20:46:04 +00:00
Duncan Sands
16d8f8bd91
I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it
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to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 20:16:09 +00:00
Dan Gohman
99dca4fde7
Remove the "WantsWholeFile" concept, as it's no longer needed. CBE
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and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 19:57:55 +00:00
Dan Gohman
ff7a562751
Implement a bunch more TargetSelectionDAGInfo infrastructure.
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Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263
Remove the TargetLowering::getSubtarget() virtual function, which
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was unused. TargetMachine::getSubtarget() is used instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 16:21:03 +00:00
Kalle Raiskila
2320a44b90
Make SPU backend not assert on jump tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 11:00:02 +00:00
Evan Cheng
fb3611daad
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 07:26:32 +00:00
Bill Wendling
3cbae239bb
Don't create a StringRef with a NULL value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 01:33:39 +00:00
Evan Cheng
0ce537a9db
Model some vst3 and vst4 with reg_sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 01:19:40 +00:00
Bill Wendling
81043ee5dc
The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
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string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.
Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 00:30:02 +00:00
Evan Cheng
e9e2ba05de
Model some vld3 instructions with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a
Model vld2 / vst2 with reg_sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 17:34:18 +00:00
Kalle Raiskila
26c4cf4c6f
Fix encoding of 'sf' and 'sfh' instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 08:13:49 +00:00
Nathan Jeffords
bb59732d18
updated handling dllexport in X86AsmPrinter
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changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-09 08:40:06 +00:00
Nathan Jeffords
071de920a0
made COFF target dllexport logic apply to all subtargets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-09 05:52:28 +00:00
Chris Lattner
b54b9ddaaf
break coff symbol definition stuff out into proper MCStreamer callbacks,
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patch by Nathan Jeffords!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-08 19:54:22 +00:00
Jim Grosbach
4b77f6a85a
Clean up the conditional for handling of sign_extend_inreg based on
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whether the extract instructions are available.
rdar://7956878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:34:55 +00:00
Devang Patel
ed66bf5125
Use overloaded operators instead of DIDescriptor::getNode()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:19:32 +00:00
Kalle Raiskila
021b5ef903
Testing svn access with a note added to documentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:06:28 +00:00
Chris Lattner
eb40a0fd98
switch MCSectionCOFF from a syntactic to semantic representation,
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patch by Peter Housel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103267 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 17:17:41 +00:00
Evan Cheng
435d499177
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 01:54:08 +00:00
Dan Gohman
0d881042c0
When rematerializing, use the debug location of the original
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instruction, rather than a location near where the new instruction
is being inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 01:28:10 +00:00
Evan Cheng
c10b5afbe8
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 00:24:52 +00:00
Daniel Dunbar
c26ae5ab7e
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
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- This fixes "leal 0, %eax", for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 22:39:14 +00:00
Chris Lattner
e1611f26e3
fix rdar://7947167 - llvm-mc doesn't match movsq
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 21:48:14 +00:00
Sean Callanan
1a8b789a4b
Eliminated the classification of control registers into %ecr_
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and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Daniel Dunbar
a5d0b54ec1
MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since
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we don't currently support relaxing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:34:01 +00:00
Dan Gohman
34dcc6fadc
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
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doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1
Add a missing break statement to fix unintentional fall-through
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(replacing the previous patch for the same issue).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 05:08:57 +00:00
Eric Christopher
f865cb5c1f
Revert r103156 since it was breaking the build bots.
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Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 02:29:06 +00:00
Evan Cheng
9c35ee2099
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:54:03 +00:00
Evan Cheng
4ffc22ae00
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:52:03 +00:00
Evan Cheng
d31c5496d7
Cosmetic changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:34:11 +00:00
Evan Cheng
7f2f436267
storeRegToStackSlot has forgotten about QPR_8 register class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:32:54 +00:00
Jim Grosbach
29402132f3
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
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instructions to subtarget features and update tests to reflect.
PR5717.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 23:44:43 +00:00
Sean Callanan
be192dd1e9
Fixed a sign-extension bug in the X86 disassembler
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that was causing PC-relative branch targets to be
evaluated incorrectly. Also added support for
checking operand values to the llvm-mc tester.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 22:47:27 +00:00
Evan Cheng
676b2dfd27
Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 22:15:40 +00:00
Dan Gohman
9f2cda73e4
No-ops emitted for scheduling don't correspond with anything in the
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user's source, so don't arbitrarily assign them a debug location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:58:01 +00:00
Jim Grosbach
b1dc393bd5
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
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Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 18:28:36 +00:00
Evan Cheng
d2c2d1809f
Trim include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103103 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 18:27:57 +00:00
Eric Christopher
f4f06906b8
Revert 102941, we're going to do this via attr and can just
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hack the code to turn it off when debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 07:35:59 +00:00
Eric Christopher
d2760d1cba
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 22:13:03 +00:00
Evan Cheng
94cc6d3a2b
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:39:49 +00:00
Evan Cheng
826bdfa603
Do not pre-allocate for registers which form a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:38:12 +00:00
Chris Lattner
d4ac35b350
"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."
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Patch by Kalle Raiskila!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 17:58:46 +00:00
Daniel Dunbar
e9f0fb4179
MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of
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instructions which have no direct register usage.
Darwin 'as' accepts:
add $0, (%rax)
but rejects
mov $0, (%rax)
for example.
Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103015 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 17:31:02 +00:00
Daniel Dunbar
c918d6043b
MC/X86: Add "support" for matching ATT style mnemonic prefixes.
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- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 16:12:42 +00:00
Gabor Greif
2f256f4561
fix operand indexes when outputting InvokeInsts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103003 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 09:23:54 +00:00
Kevin Enderby
a0161cd6f8
Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode
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changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:42:46 +00:00
Jim Grosbach
6e62b4ef14
rdar://7937137 - dbg values not being handled in thumb1 version of
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eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:11:37 +00:00
Dale Johannesen
08673d2950
Implement builtin_return_address(x) and builtin_frame_address(x)
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on PPC for x!=0. 7624113.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102972 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 22:59:34 +00:00
Kevin Enderby
9d0838fba8
Changed llvm-mc to use the same suffixes with floating point compare
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instructions as the Mac OS X darwin assembler. Some of which like 'fcoml'
assembled to different opcodes. While some of the suffixes were just different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102958 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 21:31:40 +00:00
Kevin Enderby
eb612347f4
Fixed the encoding of two of the X86 movq instuctions. The Move quadword from
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mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 21:03:31 +00:00
Kevin Enderby
3c979b06c0
Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value
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caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value. Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte. Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 20:45:05 +00:00
Eric Christopher
0b12348ddf
Add an option, defaulting to off, to disable the sse domain crossing opts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 19:54:02 +00:00
Dan Gohman
3a2a4846a6
Add a README entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 14:31:00 +00:00
Duncan Sands
57b6e9eb6c
Remove the -enable-sjlj-eh option, which doesn't do anything.
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Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-02 15:36:26 +00:00
Chris Lattner
241d3fea7a
fix some inconsistent line endings, patch by Jakub Staszak!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 17:36:49 +00:00
Anton Korobeynikov
1b17614a72
Do folding for indirect branches, where possible
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 12:28:21 +00:00
Anton Korobeynikov
69d5b48bc3
Implement indirect branches on MSP430
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 12:04:32 +00:00
Anton Korobeynikov
650a8e49f9
Long branch target oparands are not pc-rel.
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This should fix PR6603.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102834 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 12:04:22 +00:00
Dan Gohman
af1d8ca44a
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
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changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:01:06 +00:00
Dan Gohman
acbfc157d2
Fix a typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30 22:38:11 +00:00
Dan Gohman
3335a22a37
Make this code less confusing. Instead of reassigning BB, just operate
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on the original variables, so it's easier to see what is being done
to which blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30 20:14:26 +00:00
Dan Gohman
71edb241a1
Remove the -disable-16bit command-line option, which is now obsolete.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30 18:30:26 +00:00
Evan Cheng
1361796dd0
Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30 01:12:32 +00:00
Dan Gohman
ffce6f1343
Don't leave Base.FrameIndex uninitialized, so that it doesn't
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print randomly in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 23:30:41 +00:00
Dale Johannesen
8c5358c936
Make naked functions work on PPC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 19:32:19 +00:00
Devang Patel
67a444ca36
Print variable scope name in DEBUG_VALUE comment. Useful in some cases. e.g.
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##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 18:52:10 +00:00
Evan Cheng
3f54c64a98
Load folding tail call should not use ebp / rbp after it's popped. PEI
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should use esp / rsp to reference frame instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102596 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 05:08:22 +00:00
Mon P Wang
b9a01bcf48
Add support for assemblers that don't support periods in a name
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 04:00:56 +00:00
Evan Cheng
8601a3d4de
Frame index can be negative.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 01:13:30 +00:00
Kevin Enderby
9ac7282117
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the
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Operand size override prefix to be part of their records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 23:20:40 +00:00
Jim Grosbach
d100755bab
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
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rdar://7895451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 20:33:09 +00:00
Jakob Stoklund Olesen
7261fb2a6f
Teach X86FloatingPoint that a register can be killed multiple times by the same
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instruction.
This instruction would crash the pass:
INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>
Now it doesn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 18:28:37 +00:00
Evan Cheng
2bce5f4b56
Enable i16 to i32 promotion by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 08:30:49 +00:00
Evan Cheng
39cfeecae5
Unbreak the build. Only form shld / shrd after legalization.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 02:25:18 +00:00
Devang Patel
28ff35d030
Emit debug info for byval parameters.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102486 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 01:39:28 +00:00
Evan Cheng
8b1190a540
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 01:18:01 +00:00
Chris Lattner
a7b611c10d
further simplify EmitAlignment by eliminating the
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ForcedAlignBits argument, tweaking the single client of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 01:08:40 +00:00
Stuart Hastings
5a6a65be46
Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102477 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 00:35:10 +00:00
Devang Patel
a00adba6a7
Use MachineOperand::is* predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102472 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-27 22:24:37 +00:00
Evan Cheng
1c45acf510
Fix obvious typos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102467 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-27 21:46:03 +00:00
Evan Cheng
b3716e3e28
SRA promotion is also not free.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-27 19:48:31 +00:00
Chris Lattner
ee9eb411ff
on darwin empty functions need to codegen into something of non-zero length,
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otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 23:37:21 +00:00
Bob Wilson
5dfa87ecc6
Handle register-to-register copies within the tGPR class.
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Radar 7896289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 23:20:08 +00:00
Dale Johannesen
3f282aa94b
Handle target-specific form of DBG_VALUE in AsmPrinter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 20:07:31 +00:00
Dale Johannesen
efc3a6348a
Add PPC AsmPrinter handling for target-specific form of
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DBG_VALUE, and a cautionary comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 20:05:01 +00:00
Evan Cheng
552f09a0d7
Promoting 16-bit cmp / test aren't free. Don't do it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 19:06:11 +00:00
Evan Cheng
fc4d530ad6
Remove a redundant comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102326 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 08:16:57 +00:00
Evan Cheng
0965217e74
Add PPC specific emitFrameIndexDebugValue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:39:36 +00:00
Evan Cheng
62b50656ce
Add ARM specific emitFrameIndexDebugValue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:39:25 +00:00
Evan Cheng
962021bc7f
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
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- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:38:55 +00:00
Dale Johannesen
f822e733af
Stop abusing EmitInstrWithCustomInserter for target-dependent
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form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-25 21:33:54 +00:00
Evan Cheng
c82c20b315
Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-24 04:44:57 +00:00
Dan Gohman
6e8fd90602
Change TargetData's algorithm for computing defualt vector type
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alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 19:41:15 +00:00
Stuart Hastings
e3ff9ba40c
Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 19:03:32 +00:00
Evan Cheng
2808ccb775
Fix X86ISD::CMP i16 to i32 promotion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 18:21:16 +00:00
Jim Grosbach
3a1287b470
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
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extraction. This fixes PR5998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 23:24:18 +00:00
Dan Gohman
f81eca0ab9
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
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and into SelectionDAGBuilder and FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 20:46:50 +00:00
Evan Cheng
07c4e1085d
- It's not safe to promote rotates (at least not trivially).
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- Some code refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 20:19:46 +00:00
Johnny Chen
c048f1d12c
Modified some assert() msg strings; no other functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 18:37:48 +00:00
Evan Cheng
e566763b19
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
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optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 03:18:23 +00:00
Evan Cheng
5528e7bcb1
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:47:12 +00:00
Evan Cheng
fe5dcbc27d
Trim include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:39:06 +00:00
Dan Gohman
f0757b0edc
Add more const qualifiers on TargetMachine and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:34:56 +00:00
Johnny Chen
52d2b0ed00
Thumb instructions which have reglist operands at the end and predicate operands
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before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:01:19 +00:00
Bill Wendling
a040fffefb
Handle a displacement location in 64-bit as an RIP-relative displacement. It
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fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:
target triple = "x86_64-apple-darwin"
define double @func(double %a) {
%tmp1 = fmul double %a, 5.000000e-01 ; <double> [#uses=1]
ret double %tmp1
}
define i32 @main() nounwind {
%1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
ret i32 0
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 00:34:04 +00:00
Chris Lattner
d6139425f5
teach the x86 address matching stuff to handle
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(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.
This finishes off PR1135. Before we compiled the block to:
to:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
leaq 2(%rdx), %r9
movl %esi, (%rdi,%r9,4)
leaq 1(%rdx), %r9
movl %esi, (%rdi,%r9,4)
addq $3, %rdx
movl %esi, (%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
Now we produce:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
movl %esi, 8(%rdi,%rdx,4)
movl %esi, 4(%rdi,%rdx,4)
movl %esi, 12(%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 23:18:40 +00:00
Dale Johannesen
7609017dc3
Because of the EMMS problem, right now we have to support
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user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 22:34:09 +00:00
Johnny Chen
d6b5d72c0f
Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),
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instead of just asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 21:29:28 +00:00
Johnny Chen
ef37e3abb7
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
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transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 17:28:50 +00:00
Chris Lattner
aa2776e934
teach cellspu how to return i8 and i16 from calls,
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patch by Kalle Raiskila!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 05:36:09 +00:00
Chris Lattner
d7aba875c1
disable optimizations in this directory for MSVC9. This avoids
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an optimizer infinite loop on the file, PR6866.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 01:11:32 +00:00
Johnny Chen
3974ade503
Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where
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d==15 is considered illegal. Return false instead of assert().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 01:01:57 +00:00
Eric Christopher
6d972fd087
Remove the palignr intrinsics now that we lower them to vector shuffles,
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shifts and null vectors. Autoupgrade these to what we'd lower them to.
Add a testcase to exercise this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 00:59:54 +00:00
Johnny Chen
6bcf52f00a
More IT instruction error-handling improvements from fuzzing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 00:15:41 +00:00
Johnny Chen
d0f3c46d16
Better error handling of invalid IT mask '0000', instead of just asserting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 23:02:58 +00:00
Dan Gohman
1f65453d0a
Delete an unnecessary reference to SelectionDAGISel::BB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 22:48:45 +00:00
Johnny Chen
22e401f5d4
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
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Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 21:19:52 +00:00
Evan Cheng
4c26e93e89
More progress on promoting i16 operations to i32 for x86. Work in progress.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 19:29:22 +00:00
Johnny Chen
d6cc53cfe4
Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand
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instructions should have Rd (Inst{11-8}) != 0b1111.
Ref: A6.3 32-bit Thumb instruction encoding
A6.3.11 Data-processing (shifted register)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 17:16:40 +00:00
Johnny Chen
4b7df442a8
ARM disassembler did not react to recent changes to the NEON instruction table.
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VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 16:20:34 +00:00
Anton Korobeynikov
d456a47dd3
Add missed part of prev. commit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:41:42 +00:00
Anton Korobeynikov
928eb49cae
Make processor FUs unique for given itinerary. This extends the limit of 32
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FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:31:01 +00:00
Chris Lattner
34e9d17d1b
fix PR6332, allowing an index of zero into a zero sized array
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even if the element of the array has no size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 19:02:33 +00:00
Chris Lattner
eef6d78be1
teach the x86 asm parser how to handle segment prefixes
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in memory operands. rdar://7874844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 18:56:34 +00:00
Dan Gohman
3fb150a902
Fix -Wcast-qual warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:42:52 +00:00
Chris Lattner
89f94926b0
remove a dead variable, PR6856
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:28:00 +00:00
Dan Gohman
0d805c33d1
Add const qualifiers to TargetLoweringObjectFile usage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 16:44:48 +00:00
Dan Gohman
82d5eaf23e
Use const_cast instead of a C-style cast to cast away const.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101639 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 16:43:55 +00:00
Dan Gohman
383b5f6b91
Delete now-unnecessary const_casts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101637 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:32:28 +00:00
Dan Gohman
b6f778a8f6
Use cast instead of dyn_cast when assuming success.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101636 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:31:16 +00:00
Dan Gohman
d858e90f03
Use const qualifiers with TargetLowering. This eliminates several
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const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:26:15 +00:00
Dan Gohman
1e93df6f0b
Move per-function state out of TargetLowering subclasses and into
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MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 14:41:14 +00:00
Chandler Carruth
2329d66a9f
Name these stub files consistently with the SPU and PPC targets' conventions.
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Also rename the classes appropriately. The CMake build already used these
names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101631 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 08:50:29 +00:00
Chris Lattner
65de1b9eb3
a bunch of ssse3 instructions are misencoded to think they have an
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i8 field when they really do not. This fixes rdar://7840289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 07:38:24 +00:00
Evan Cheng
e5b51ac770
More work to allow dag combiner to promote 16-bit ops to 32-bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 06:13:15 +00:00
Bob Wilson
9f3f061d74
Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
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may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 05:30:19 +00:00
Chris Lattner
9484689f14
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101581 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:52:30 +00:00
Eric Christopher
551754c495
Revert 101465, it broke internal OpenGL testing.
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Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101579 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:37:20 +00:00
Johnny Chen
de0ade4939
Cast to (uint64_t) instead of relying on the "ul" suffix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:30:28 +00:00
Dan Gohman
53c5e42ab9
Add skeleton target-specific SelectionDAGInfo files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:04:22 +00:00
Johnny Chen
af5b0e851e
Fixed logic error. Should check Builder for validity before calling SetSession
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on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 23:02:25 +00:00
Johnny Chen
c7b65914e0
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
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case. Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.
Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 22:40:20 +00:00
Chris Lattner
aef1fea3d3
add a missing break back, patch by Nico Schmidt!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 21:15:15 +00:00
Dan Gohman
37f32ee7ff
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 20:11:05 +00:00
Johnny Chen
16fda6982b
In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
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this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 19:57:21 +00:00
Johnny Chen
2fb10f17d8
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
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to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 19:33:23 +00:00
Johnny Chen
d73d187e33
Remove the assert() from printAddrMode2OffsetOperand(). " #0 and #-0" are
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considered legal instructions.
Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 19:10:52 +00:00
Gabor Greif
4ec2258ffb
reapply r101434
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with a fix for self-hosting
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 15:33:14 +00:00
Evan Cheng
64b7bf71e8
Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
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x86 support is off by default. It can be enabled with -promote-16bit.
Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 06:14:10 +00:00
Evan Cheng
47b7b9f228
Use getAL() rather than a major constant.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 05:46:06 +00:00
Gabor Greif
607a7ab3da
back out r101423 and r101397, they break llvm-gcc self-host on darwin10
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 01:16:20 +00:00
Johnny Chen
1cfa094562
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
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am2offset. Modified the instruction table entry and added a new test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 23:12:47 +00:00
Evan Cheng
3a1588a2e3
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 22:20:34 +00:00
Gabor Greif
2ff961f668
reapply r101364, which has been backed out in r101368
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with a fix
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101397 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 20:51:13 +00:00
Evan Cheng
0ea7d219ec
ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
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llvm is generating poor code for dynamic alloca, I'll fix that later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 18:42:28 +00:00
Johnny Chen
c8866980fe
DEBUG() print out "Unknown format" msg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101382 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 18:13:51 +00:00
Dan Gohman
8c407d4596
ReuseFrameIndexVals is used in multiple files, so it can't be static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 17:34:58 +00:00
Dan Gohman
82bcd23693
EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
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can't be static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 17:20:57 +00:00
Dan Gohman
b35798347e
Fix a bunch of namespace polution.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 17:08:50 +00:00
Gabor Greif
9ee1720811
back out r101364, as it trips the linux nightlybot on some clang C++ tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 12:46:56 +00:00
Gabor Greif
165dac08d1
rotate CallInst operands, i.e. move callee to the back
...
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 10:49:53 +00:00
Chris Lattner
2392ae7d73
Implement rdar://7860110 (also in target/readme.txt) narrowing
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a load/or/and/store sequence into a narrower store when it is
safe. Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.
This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll
into:
movl %eax, 36(%rdi)
instead of:
movl $4294967295, %eax ## imm = 0xFFFFFFFF
andq 32(%rdi), %rax
shlq $32, %rcx
addq %rax, %rcx
movq %rcx, 32(%rdi)
and each of the testcases into a single store. Each of them used
to compile into craziness like this:
_test4:
movl $65535, %eax ## imm = 0xFFFF
andl (%rdi), %eax
shll $16, %esi
addl %eax, %esi
movl %esi, (%rdi)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 04:48:01 +00:00
Dan Gohman
ae541aad5c
Add more const qualifiers for LLVM IR pointers in CodeGen.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 04:33:49 +00:00
Anders Carlsson
0dbdca5a85
Fix build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101335 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 03:11:28 +00:00
Dan Gohman
46510a73e9
Add const qualifiers to CodeGen's use of LLVM IR constructs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 01:51:59 +00:00
Eric Christopher
cff6f85454
Allow lowering for palignr instructions for mmx sized vectors. Add
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patterns to handle the lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101331 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 01:40:20 +00:00
Johnny Chen
44398693e7
Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 01:20:56 +00:00
Johnny Chen
d1ec11a850
Fixed another assert exposed by fuzzing. Now, the DisassembleVFPLdStMulFrm()
...
function checks whether we have a valid submode for VLDM/VSTM (must be either
"ia" or "db") before calling ARM_AM::getAM5Opc(AMSubMode, unsigned char).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 22:37:17 +00:00
Jim Grosbach
e7b52526d3
Add -arm-long-calls option to force calls to be indirect. This makes the
...
kernel linker happier when dealing with kexts.
Radar 7805069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 22:28:31 +00:00
Johnny Chen
2fd100a4cb
For t2BFI disassembly, apply the same error checking as in r101205.
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Change the error msg to read "Encoding error: msb < lsb".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 22:04:45 +00:00
Johnny Chen
d907d2566a
Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
...
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.
Since getRegisterEnum() is used all over the place, to change the code to check
for encoding error after each call would not only bloat the code, but also make
it less readable. An Err flag is added to the ARMBasicMCBuilder where a client
can set a non-zero value to indicate some kind of error condition while building
up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false
if a non-zero value is detected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101290 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 21:03:13 +00:00
Bob Wilson
164cd8b8d3
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
...
does not have a legal type. The legalizer does not know how to handle those
nodes. Radar 7854640.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 20:45:23 +00:00
Dan Gohman
6465265ae1
Delete unneeeded arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 20:17:22 +00:00
Dan Gohman
2520864773
Factor out EH landing pad code into a separate function, and constify
...
a bunch of stuff to support it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 19:53:31 +00:00
Johnny Chen
6f72ab345d
Fixed another assert exposed by fuzzing. Now, when an encoding error occurs
...
involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler
just returns false, instead of assert, to indicate disassembly error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 02:05:29 +00:00
Johnny Chen
efcdac0c41
Fixed an assert() exposed by fuzzing. Now, instead of assert when an invalid
...
instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder
instance and the client just returns false to indicate disassembly error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 01:17:37 +00:00
Douglas Gregor
533ae9b71d
Unbreak CMake build by improving the EnhancedDisassembly makefile a
...
bit (we're not trying to build a shared library yet) and generating
the X86GenEDInfo.inc and ARMGenEDInfo.inc files as necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101188 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 22:47:43 +00:00
Bob Wilson
6a234f07fa
Handle a v2f64 formal parameter that is split between registers and memory
...
such that the entire second half is in memory. Radar 7855014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101181 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 22:03:22 +00:00
Sean Callanan
9899f70a74
Fixed a nasty layering violation in the edis source
...
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 21:21:57 +00:00
Johnny Chen
8a87ffb925
Changed getSOImmValRotate()'s hunt retry logic to ignore the low order 6 bits,
...
instead of 7, because we are only looking for even rotate amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 20:35:16 +00:00
Evan Cheng
fc5a03e469
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101162 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 18:50:27 +00:00
Eric Christopher
97e6992e3e
Temporarily revert r101075, it's causing invalid iterator assertions
...
in a nightly tester.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 18:37:58 +00:00
Dan Gohman
81bf03eb5c
Eliminate MachineBasicBlock::const_livein_iterator and make
...
MachineBasicBlock::livein_iterator a const_iterator, because
clients shouldn't ever be using the iterator interface to
mutate the livein set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 16:57:55 +00:00
Dan Gohman
c5e43c958e
Use MachineBasicBlock::isLiveIn.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 16:53:51 +00:00
Bob Wilson
b123b8bee0
Replace r101053 with a fix for getSOImmValRotate() so that it will correctly
...
recognize all the valid rotated immediates. This fixes the disassembler
issue and will also help codegen for some unusual constant values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 02:11:48 +00:00
Chris Lattner
43ac721e3b
add llvm codegen support for -ffunction-sections and -fdata-sections,
...
patch by Sylvere Teissier!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101106 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 00:36:43 +00:00
Evan Cheng
82865a10f8
Use .set expression for x86 pic jump table reference to reduce assembly relocation. rdar://7738756
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101085 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-12 23:07:17 +00:00
Bill Wendling
2aae6ae572
Micro-optimization:
...
If we have this situation:
jCC L1
jmp L2
L1:
...
L2:
...
We can get a small performance boost by emitting this instead:
jnCC L2
L1:
...
L2:
...
This testcase shows an example of this:
float func(float x, float y) {
double product = (double)x * y;
if (product == 0.0)
return product;
return product - 1.0;
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-12 22:19:57 +00:00
Johnny Chen
bb6e9d8cf7
Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
...
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).
[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done
(gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------
mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.
Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0 0x00007fff88c65886 in __kill ()
#1 0x00007fff88d05eae in abort ()
#2 0x00007fff88cf2ef0 in __assert_rtn ()
#3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running. Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-12 18:46:53 +00:00
Chris Lattner
5106dcd078
Implement support for varargs functions without any fixed
...
parameters in the CBE by implicitly adding a fixed argument.
This allows eliminating a work-around from DAE. Patch by
Sylvere Teissier!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-10 19:12:44 +00:00
Bob Wilson
ec80e2693a
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
...
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 20:41:18 +00:00
Chris Lattner
dc8446330f
"On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment.
...
this patch disables .lcomm in favour of '.local .comm'
Patch by Kalle Raisklia!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 18:27:03 +00:00
Chris Lattner
287df1bc03
delete a forwarding function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 21:34:17 +00:00
Chris Lattner
74aae4726a
move elf section uniquing to MCContext. Along the way
...
merge XCore's section into MCSectionELF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 21:26:26 +00:00
Chris Lattner
22772214de
remove the TargetLoweringObjectFileMachO::getMachoSection
...
api and update clients to use MCContext instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 20:40:11 +00:00
Gabor Greif
f042f97d7e
use abstract interface in two more places
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 13:50:42 +00:00
Gabor Greif
e964af6ff8
fix compile
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 13:08:11 +00:00
Gabor Greif
2fa16e7083
use abstract interface
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 12:52:19 +00:00
Benjamin Kramer
1bd7335a17
Use twines to simplify calls to report_fatal_error. For code size and readability.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 10:44:28 +00:00
Evan Cheng
c3b0c341e7
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 07:37:57 +00:00
Eric Christopher
419e223f5d
mpsadbw is not commutative.
...
Fixes PR3440.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 00:52:02 +00:00
Sean Callanan
8f993b8c24
Added support for ARM disassembly to edis.
...
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 00:48:21 +00:00
Ted Kremenek
28e830d25f
Update CMake build.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 23:05:23 +00:00
Chris Lattner
75361b69f3
rename llvm::llvm_report_error -> llvm::report_fatal_error
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:58:41 +00:00
Chris Lattner
e3a601b648
add newlines at end of files.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100706 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:54:55 +00:00
Johnny Chen
b72e59e361
Missed this one line for the previous checkin to fix build warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100697 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:21:03 +00:00
Johnny Chen
efd518e1fd
Fixed warnings pointed out by clang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:03:27 +00:00
Johnny Chen
7e4823c51f
Fixed warnings pointed out by clang.
...
Next to work on is ARMDisassemblerCore.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100695 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 21:52:48 +00:00
Sean Callanan
5edca81626
Fixed a bug where the disassembler would allow an immediate
...
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter. Now, the
disassembler rejects instructions with out-of-range values
for that immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 21:42:19 +00:00
Johnny Chen
c22e2fcf72
Fixed 3 warnings pointed out by clang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 21:23:48 +00:00
Johnny Chen
3c500e6947
Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
...
ARMDecoderEmitter.cpp, with FIXME comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:53:12 +00:00
Sean Callanan
90b7097f92
Added an AsmLexer for the ARM target, which uses
...
a simple mapping of register names to IDs to
identify register tokens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:29:34 +00:00
Dale Johannesen
375be7730a
Educate GetInstrSizeInBytes implementations that
...
DBG_VALUE does not generate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 19:51:44 +00:00
Anton Korobeynikov
4b38debf59
Remove late ARM codegen optimization pass committed by accident.
...
It is not ready for public yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:23:27 +00:00
Anton Korobeynikov
e1676011c6
Split A8/A9 itins - they already were too big.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:22:11 +00:00
Anton Korobeynikov
895867326e
Add some crude itin approximation for VFP load / stores on A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:22:03 +00:00
Anton Korobeynikov
67867135ec
Add some crude approximation for neon load/store instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:58 +00:00
Anton Korobeynikov
9113052a1f
Add some A8-based approximation for instructions with unknown cycle times
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100669 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:52 +00:00
Anton Korobeynikov
ebd4cb43c2
Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:46 +00:00
Anton Korobeynikov
9ad709b523
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:41 +00:00
Anton Korobeynikov
f3da92b2f2
Fix A8 FP NEON MAC itins
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100666 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:33 +00:00
Anton Korobeynikov
924369d58e
A9 NEON FP itins
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100665 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:27 +00:00
Anton Korobeynikov
ec69dfa7ca
Some permute goodness for A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:22 +00:00
Anton Korobeynikov
5ca13c6ee3
More shift itins for A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:16 +00:00
Anton Korobeynikov
ecc6406072
More fixes for itins
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:10 +00:00
Anton Korobeynikov
95102073e8
Fix invalid itins for 32-bit varians of VMLAL and friends
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:21:04 +00:00
Anton Korobeynikov
7930ac19e7
Add MAC stuff for A9
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:58 +00:00
Anton Korobeynikov
d76da03e91
Fix invalid NEON MAC itins on A8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:53 +00:00
Anton Korobeynikov
dc0bab70cf
Fix itins for VPAL
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100658 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:47 +00:00
Anton Korobeynikov
0a3e2b591c
Fix itins for VABA
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:42 +00:00
Anton Korobeynikov
fc2b08438c
Correct VMVN itinerary: operand is read in the second cycle, not in the first.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:36 +00:00
Anton Korobeynikov
e715b1e43a
More A9 itineraries
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:29 +00:00
Anton Korobeynikov
1c03f2493f
Correct itinerary class for VPADD
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:24 +00:00
Anton Korobeynikov
4ac0af851f
VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:18 +00:00
Anton Korobeynikov
f8b5c63617
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:13 +00:00
Anton Korobeynikov
268b7446cf
Some easy NEON scheduling goodness for A9
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100651 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:20:07 +00:00