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47 Commits

Author SHA1 Message Date
Johnny Chen
aeb326aad7 Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-25 22:54:29 +00:00
Johnny Chen
e43b6c9695 Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94455 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-25 21:56:35 +00:00
Jakob Stoklund Olesen
c5b7ef1519 Remove the JustSP single-register regclass. 
It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-13 00:43:06 +00:00
Jakob Stoklund Olesen
24b34f8f3e Add a SPR register class to the ARM target. 
Certain Thumb instructions require only SP (e.g. tSTRspi).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91944 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 23:54:44 +00:00
Evan Cheng
3f4e47be0a Add QPR_8 as a superreg class of SPR_8 and DPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85869 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:50:57 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:39 +00:00
Jim Grosbach
2f1abe2dae Restrict Thumb1 register allocation to low registers, even for instructions that 
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84982 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 00:19:24 +00:00
Jim Grosbach
7388037dd1 FIXME no longer applies. R12 and R3 are available for allocation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84977 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 23:07:42 +00:00
Jim Grosbach
6009751244 Enable allocation of R3 in Thumb1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:57:03 +00:00
Anton Korobeynikov
2a52122b30 Fix merge problem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81658 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-13 01:12:15 +00:00
Anton Korobeynikov
20c35ec427 Define proper subreg sets for arm - this should fix bunch of subtle problems 
with subreg - superreg mapping and also fix PR4965.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81657 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-13 00:59:43 +00:00
Anton Korobeynikov
e56f9085b1 Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to 
constraint the register usage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81635 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-12 22:21:08 +00:00
Anton Korobeynikov
6ca0b9e722 Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and 
makes the code faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81220 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-08 15:22:32 +00:00
David Goodwin
7bfdca0206 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 21:02:22 +00:00
Evan Cheng
3425df44b5 In thumb mode, r7 is used as frame register. This fixes pr4681. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 18:46:17 +00:00
Evan Cheng
d600522608 Add VFP3 D registers to the DPR register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:03:41 +00:00
Evan Cheng
3b6627b944 Fix a obvious copy-n-paste bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76727 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 06:12:40 +00:00
Evan Cheng
91449a883d Model fpscr to prevent fcmped / fcmpezs etc from being deleted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76390 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 02:12:31 +00:00
Bob Wilson
e622087e20 Fix an obvious copy-and-paste error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75566 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 00:23:44 +00:00
Bob Wilson
60206140a1 Revert 75309. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75562 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 00:01:42 +00:00
Bob Wilson
1e44ed88eb Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of 
quad registers and the Q4PR class holds sets of 4 quad registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75309 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 23:09:06 +00:00
Bob Wilson
5bafff36c7 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 23:27:02 +00:00
Bob Wilson
54fc124d72 For Darwin on ARMv6 and newer, make register r9 available for use as a 
caller-saved register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 21:01:46 +00:00
Evan Cheng
cd828618b8 Remove UseThumbBacktraces. Just check if subtarget is darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 23:14:30 +00:00
Anton Korobeynikov
0eebf653a7 The attached patches implement most of the ARM AAPCS-VFP hard float 
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 22:53:56 +00:00
Evan Cheng
925492279a Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 19:08:58 +00:00
Jim Grosbach
30eae3c022 PR2985 / <rdar://problem/6584986> 
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-07 20:34:09 +00:00
Dan Gohman
6f0d024a53 Rename MRegisterInfo to TargetRegisterInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-10 18:45:23 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Anton Korobeynikov
f191c80cd7 Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-11 19:50:10 +00:00
Evan Cheng
16b6598325 Added ARM::CPSR to represent ARM CPSR status register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:17:13 +00:00
Evan Cheng
ba647becb9 Specify S registers as D registers' sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 21:20:10 +00:00
Evan Cheng
bf822eb6a3 Change register allocation order to Dale's suggestion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35021 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 02:56:40 +00:00
Evan Cheng
cb20998b3f ARM always use register scavenger. No longer reserves R12. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34999 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 02:46:23 +00:00
Evan Cheng
36230cdda4 Make requiresRegisterScavenging determination on a per MachineFunction basis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 00:59:19 +00:00
Evan Cheng
41a4d562f7 Temporary: make R12 available in ARM mode if RegScavenger is being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34709 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 00:22:44 +00:00
Evan Cheng
15991bf775 Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34701 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-27 23:03:55 +00:00
Evan Cheng
24f7fb3267 Comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33633 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-29 22:23:02 +00:00
Evan Cheng
dc77540d95 hasFP() is now a virtual method of MRegisterInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-23 00:57:47 +00:00
Evan Cheng
75e18c403e Clean up ARM PEI code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33389 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-20 02:09:25 +00:00
Evan Cheng
a8e2989ece ARM backend contribution from Apple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-19 07:51:42 +00:00
Rafael Espindola
7ae68ab3bc initial support for frame pointers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31197 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-26 13:31:26 +00:00
Rafael Espindola
9e071f0ae3 fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-02 19:30:56 +00:00
Rafael Espindola
27185190e6 add floating point registers 
implement SINT_TO_FP


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30673 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-29 21:20:16 +00:00
Chris Lattner
5ea64fd9eb Constify some methods. Patch provided by Anton Vayvod, thanks! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-17 22:00:08 +00:00
Rafael Espindola
58421d7d08 initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-18 00:08:07 +00:00
Rafael Espindola
7bc59bc395 added a skeleton of the ARM backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-14 22:18:28 +00:00